# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/aspeed,ast2x00-scu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Aspeed System Control Unit

description:
  The Aspeed System Control Unit manages the global behaviour of the SoC,
  configuring elements such as clocks, pinmux, and reset.
  In AST2700 SOC which has two soc connection, each soc have its own scu
  register control, ast2700-scu0 for soc0, ast2700-scu1 for soc1.

maintainers:
  - Joel Stanley <joel@jms.id.au>
  - Andrew Jeffery <andrew@aj.id.au>

properties:
  compatible:
    items:
      - enum:
          - aspeed,ast2400-scu
          - aspeed,ast2500-scu
          - aspeed,ast2600-scu
          - aspeed,ast2700-scu0
          - aspeed,ast2700-scu1
      - const: syscon
      - const: simple-mfd

  reg:
    maxItems: 1

  ranges: true

  '#address-cells':
    minimum: 1
    maximum: 2

  '#size-cells':
    const: 1

  '#clock-cells':
    const: 1

  '#reset-cells':
    const: 1

patternProperties:
  '^p2a-control@[0-9a-f]+$':
    description: >
      PCI-to-AHB Bridge Control

      The bridge is available on platforms with the VGA enabled on the Aspeed
      device. In this case, the host has access to a 64KiB window into all of
      the BMC's memory. The BMC can disable this bridge. If the bridge is
      enabled, the host has read access to all the regions of memory, however
      the host only has read and write access depending on a register
      controlled by the BMC.
    type: object
    additionalProperties: false

    properties:
      compatible:
        enum:
          - aspeed,ast2400-p2a-ctrl
          - aspeed,ast2500-p2a-ctrl
      reg:
        maxItems: 1

      memory-region:
        maxItems: 1
        description:
          A reserved_memory region to be used for the PCI to AHB mapping

    required:
      - compatible
      - reg

  '^pinctrl(@[0-9a-f]+)?$':
    type: object
    additionalProperties: true
    properties:
      compatible:
        contains:
          enum:
            - aspeed,ast2400-pinctrl
            - aspeed,ast2500-pinctrl
            - aspeed,ast2600-pinctrl

    required:
      - compatible

  '^interrupt-controller@[0-9a-f]+$':
    type: object
    additionalProperties: true
    properties:
      compatible:
        contains:
          enum:
            - aspeed,ast2500-scu-ic
            - aspeed,ast2600-scu-ic0
            - aspeed,ast2600-scu-ic1
            - aspeed,ast2700-scu-ic0
            - aspeed,ast2700-scu-ic1
            - aspeed,ast2700-scu-ic2
            - aspeed,ast2700-scu-ic3

  '^silicon-id@[0-9a-f]+$':
    description: Unique hardware silicon identifiers within the SoC
    type: object
    additionalProperties: false

    properties:
      compatible:
        items:
          - enum:
              - aspeed,ast2400-silicon-id
              - aspeed,ast2500-silicon-id
              - aspeed,ast2600-silicon-id
              - aspeed,ast2700-silicon-id
          - const: aspeed,silicon-id

      reg:
        description:
          The reg should be the unique silicon id register, and not backwards
          compatible one in eg. the 2600.
        minItems: 1
        items:
          - description: silicon id information registers
          - description: unique chip id registers

required:
  - compatible
  - reg
  - ranges
  - '#address-cells'
  - '#size-cells'
  - '#clock-cells'
  - '#reset-cells'

additionalProperties: false

examples:
  - |
    syscon@1e6e2000 {
        compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
        reg = <0x1e6e2000 0x1a8>;
        #clock-cells = <1>;
        #reset-cells = <1>;

        #address-cells = <1>;
        #size-cells = <1>;
        ranges = <0x0 0x1e6e2000 0x1000>;

        p2a-control@2c {
            compatible = "aspeed,ast2400-p2a-ctrl";
            reg = <0x2c 0x4>;
        };

        silicon-id@7c {
            compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id";
            reg = <0x7c 0x4>, <0x150 0x8>;
        };
    };
...
