# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/qcom,pcie-sa8255p.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm SA8255p based firmware managed and ECAM compliant PCIe Root Complex

maintainers:
  - Bjorn Andersson <andersson@kernel.org>
  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

description:
  Qualcomm SA8255p SoC PCIe root complex controller is based on the Synopsys
  DesignWare PCIe IP which is managed by firmware, and configured in ECAM mode.

properties:
  compatible:
    const: qcom,pcie-sa8255p

  reg:
    description:
      The base address and size of the ECAM area for accessing PCI
      Configuration Space, as accessed from the parent bus. The base
      address corresponds to the first bus in the "bus-range" property. If
      no "bus-range" is specified, this will be bus 0 (the default).
    maxItems: 1

  ranges:
    description:
      As described in IEEE Std 1275-1994, but must provide at least a
      definition of non-prefetchable memory. One or both of prefetchable Memory
      may also be provided.
    minItems: 1
    maxItems: 2

  interrupts:
    minItems: 8
    maxItems: 8

  interrupt-names:
    items:
      - const: msi0
      - const: msi1
      - const: msi2
      - const: msi3
      - const: msi4
      - const: msi5
      - const: msi6
      - const: msi7

  power-domains:
    maxItems: 1

  dma-coherent: true
  iommu-map: true

required:
  - compatible
  - reg
  - ranges
  - power-domains
  - interrupts
  - interrupt-names

allOf:
  - $ref: /schemas/pci/pci-host-bridge.yaml#

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>

    soc {
        #address-cells = <2>;
        #size-cells = <2>;

        pci@1c00000 {
            compatible = "qcom,pcie-sa8255p";
            reg = <0x4 0x00000000 0 0x10000000>;
            device_type = "pci";
            #address-cells = <3>;
            #size-cells = <2>;
            ranges = <0x02000000 0x0 0x40100000 0x0 0x40100000 0x0 0x1ff00000>,
                     <0x43000000 0x4 0x10100000 0x4 0x10100000 0x0 0x40000000>;
            bus-range = <0x00 0xff>;
            dma-coherent;
            linux,pci-domain = <0>;
            power-domains = <&scmi5_pd 0>;
            iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
                        <0x100 &pcie_smmu 0x0001 0x1>;
            interrupt-parent = <&intc>;
            interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
                         <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
            interrupt-names = "msi0", "msi1", "msi2", "msi3",
                                   "msi4", "msi5", "msi6", "msi7";

            #interrupt-cells = <1>;
            interrupt-map-mask = <0 0 0 0x7>;
            interrupt-map = <0 0 0 1 &intc GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
                            <0 0 0 2 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
                            <0 0 0 3 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
                            <0 0 0 4 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;

            pcie@0 {
                device_type = "pci";
                reg = <0x0 0x0 0x0 0x0 0x0>;
                bus-range = <0x01 0xff>;

                #address-cells = <3>;
                #size-cells = <2>;
                ranges;
            };
        };
    };
