trial-ttcn3_bts_tests:sysmo 101

Took 51 min

All Failed Tests

Name	Age	Duration
TC_chan_act_a52	2	22 sec
TC_chan_act_a53	31	23 sec
TC_chan_act_stress	1	24 sec
TC_conn_fail_crit Regression	3	40 sec
TC_deact_sacch	31	54 sec
TC_encr_cmd_a52	1	33 sec
TC_encr_cmd_a53	31	29 sec
TC_ho_rach	31	41 sec
TC_meas_res_sign_sdcch4	31	39 sec
TC_meas_res_sign_sdcch8	31	40 sec
TC_meas_res_sign_tchf	31	44 sec
TC_meas_res_sign_tchh	31	39 sec
TC_meas_res_sign_tchh_toa256	31	40 sec
TC_meas_res_speech_tchf	5	28 sec
TC_meas_res_speech_tchf_facch	2	39 sec
TC_meas_res_speech_tchh	5	40 sec
TC_meas_res_speech_tchh_facch	2	39 sec
TC_meas_res_speech_tchh_toa256	4	40 sec
TC_ms_pwr_ctrl_constant	6	26 sec
TC_ms_pwr_ctrl_pf_ewma	5	26 sec
TC_paging_imsi_200percent Regression	2	39 sec
TC_paging_imsi_80percent Regression	2	39 sec
TC_paging_tmsi_200percent	2	39 sec
TC_paging_tmsi_80percent	2	39 sec
TC_rach_load_count	31	2 sec
TC_rach_load_idle_below_thresh	31	2 sec
TC_rach_load_idle_thresh0	31	2 sec
TC_rach_max_ta	31	35 sec
TC_rll_est_req_ACCH_3	31	23 sec
TC_rll_rel_ind_ACCH_0	31	24 sec
TC_rll_rel_ind_ACCH_3	31	27 sec
TC_rll_rel_req	31	33 sec
TC_rll_unit_data_req_ACCH	31	35 sec
TC_rsl_bs_pwr_static_ass Regression	2	32 sec
TC_rsl_bs_pwr_static_power_control Regression	2	44 sec
TC_rsl_chan_initial_ms_pwr	31	30 sec
TC_rsl_chan_initial_ta	31	39 sec
TC_rsl_modify_encr	31	40 sec
TC_rsl_ms_pwr_ctrl	3	44 sec
TC_rsl_ms_pwr_dyn_active	31	24 sec
TC_rsl_ms_pwr_dyn_active2	31	15 sec
TC_rsl_ms_pwr_dyn_ass_updown	31	15 sec
TC_rsl_ms_pwr_dyn_down	31	15 sec
TC_rsl_ms_pwr_dyn_max	31	15 sec
TC_rsl_ms_pwr_dyn_up	31	15 sec
TC_sacch_chan_act	31	40 sec
TC_sacch_chan_act_ho_async	31	25 sec
TC_sacch_chan_act_ho_sync	31	16 sec
TC_sacch_filling	31	42 sec
TC_sacch_info_mod	31	42 sec
TC_sacch_multi	31	52 sec
TC_sacch_multi_chg	31	35 sec
TC_si_sched_1 Regression	2	40 sec
TC_si_sched_13	2	39 sec
TC_si_sched_13_2bis_2ter_2quater	31	41 sec
TC_si_sched_2bis Regression	2	39 sec
TC_si_sched_2quater	31	39 sec
TC_si_sched_2ter Regression	2	40 sec
TC_si_sched_2ter_2bis Regression	2	40 sec
TC_si_sched_default	2	39 sec
TC_tch_sign_l2_fill_frame	31	22 sec
TC_tch_sign_l2_fill_frame_dtxd	31	27 sec
TC_tx_power_ramp_adm_state_change	31	19 sec
TC_tx_power_start_ramp_down_bcch	31	27 sec
TC_tx_power_start_ramp_up_bcch	31	39 sec

All Tests

Class	Failed	Skipped	Passed	Total	Duration
ttcn3_bts_tests	65+8	0	36-8	101	51 min