#92 (Feb 6, 2026, 8:55:01 AM)

Started by timer

This run spent:

• 0.25 sec waiting;
• 1 min 46 sec build duration;
• 1 min 46 sec total from scheduled to completion.

• origin/master

• HLR_Tests.TC_gsup_ul_subscriber_data
• HLR_Tests.TC_mo_ussd_unknown
• HLR_Tests.TC_mo_ussd_euse_disc
• HLR_Tests.TC_mo_ussd_iuse_imsi
• HLR_Tests.TC_mo_ussd_iuse_msisdn
• HLR_Tests.TC_mo_ussd_euse
• HLR_Tests.TC_mo_ussd_euse_continue
• HLR_Tests.TC_mo_ussd_euse_defaultroute
• HLR_Tests.TC_mo_sss_reject

1. bts: f_TC_tx_power_ramp_adm_state_change(): drop unused last_rx_lvl (details)
2. bts: f_TC_acch_overpower(): use f_wait_ramp_up() (details)
3. bts: fix verdict string in f_verify_ramp_up() (details)