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"https://jenkins.osmocom.org/jenkins/user/fixeria", "fullName" : "Vadim Yanitskiy" }, "authorEmail" : "vyanitskiy@sysmocom.de", "comment" : "bts: TC_rsl_chan_initial_ta: misc improvements\u000a\u000aChange-Id: Ifc2c850104b3710679485042ab5b7a758d0ae000\u000aRelated: OS#6919\u000a", "date" : "2026-01-22 19:15:23 +0700", "id" : "8a64553f86ced946fdd6bc7b07ec2e04c3db39f5", "msg" : "bts: TC_rsl_chan_initial_ta: misc improvements", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/BTS_Tests.ttcn" ], "commitId" : "7c513d15cd40ce95308859127a1f43f3b8682b30", "timestamp" : 1769084123000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/fixeria", "fullName" : "Vadim Yanitskiy" }, "authorEmail" : "vyanitskiy@sysmocom.de", "comment" : "bts: TC_rsl_chan_initial_ta: fix sporadic failures\u000a\u000aIt may happen that an UL SACCH block is received by the BTS before a DL\u000aSACCH block is generated and delivered to the testcase. In this case,\u000athe Timing Advance control loop may update the initial TA value that\u000awas set during RSL CHANnel ACTIVation.\u000a\u000aBy default, trxcon transmits UL SACCH blocks with TA=0, which is exactly\u000awhat triggers the TA control loop in this situation.\u000a\u000aTo avoid this, we explicitly signal the expected TA value to trxcon by\u000apre-populating the UL SACCH cache. This is done by sending a DATA.req\u000acontaining a measurement report in advance, before establishing DCCH,\u000aso that subsequent UL SACCH blocks carry the correct TA and do not\u000aactivate the control loop.\u000a\u000aAdditionally, take the opportunity to add missing f_L1CTL_PARAM().\u000aThis compensates for the artificial delay introduced by\u000af_trxc_fake_toffs256(), further reducing the risk of triggering\u000athe TA control loop.\u000a\u000aChange-Id: Iebb043ccc710750dff937e2281c23d343b85bda1\u000aRelated: OS#6919\u000a", "date" : "2026-01-22 19:15:23 +0700", "id" : "7c513d15cd40ce95308859127a1f43f3b8682b30", "msg" : "bts: TC_rsl_chan_initial_ta: fix sporadic failures", "paths" : [ { "editType" : "edit", "file" : "bts/BTS_Tests.ttcn" } ] }, { "_class" : "hudson.plugins.git.GitChangeSet", "affectedPaths" : [ "bts/osmo-bts.cfg" ], "commitId" : "c3ab9ec33f37c6837fb8bcb0fa0bbd2e98781fb7", "timestamp" : 1769169386000, "author" : { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/pespin", "fullName" : "Pau Espin Pedrol" }, "authorEmail" : "pespin@sysmocom.de", "comment" : "bts: limit stderr logging to NOTICE to avoid long write() to ext4 fs\u000a\u000astderr being redirected to a file in the ext4 filesystem sometimes ends\u000aup in write() syscall taking >500ms, which means the entire osmo-bts\u000aprocess stalls during that time and we miss clock updates up to a\u000athreshold which makes osmo-bts process exit with an error.\u000a\u000aLet's decrease logging verbosity to NOTICE for now with the aim to not\u000arun into those stalls during normal operation, while we can re-eanble\u000athis manually when debugging the write() issue.\u000a\u000aRelated: OS#6794\u000aChange-Id: I74c4abf7571d2a0f9ee22402a949dbde02896d7d\u000a", "date" : "2026-01-23 12:56:26 +0100", "id" : "c3ab9ec33f37c6837fb8bcb0fa0bbd2e98781fb7", "msg" : "bts: limit stderr logging to NOTICE to avoid long write() to ext4 fs", "paths" : [ { "editType" : "edit", "file" : "bts/osmo-bts.cfg" } ] } ], "kind" : "git" }, "culprits" : [ { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/fixeria", "fullName" : "Vadim Yanitskiy" }, { "absoluteUrl" : "https://jenkins.osmocom.org/jenkins/user/pespin", "fullName" : "Pau Espin Pedrol" } ] }