2026-03-01 01:31:20.175 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.36.20:5700'
2026-03-01 01:31:20.175 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.36.20:5802)
2026-03-01 01:31:20.175 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.36.20:5801)
2026-03-01 01:31:20.175 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.36.22:6700'
2026-03-01 01:31:20.175 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.36.22:6802)
2026-03-01 01:31:20.175 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.36.22:6801)
2026-03-01 01:31:20.175 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.36.20:5700/1'
2026-03-01 01:31:20.176 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.36.20:5804)
2026-03-01 01:31:20.176 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.36.20:5803)
2026-03-01 01:31:20.176 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.36.20:5700/2'
2026-03-01 01:31:20.176 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.36.20:5806)
2026-03-01 01:31:20.176 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.36.20:5805)
2026-03-01 01:31:20.176 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.36.20:5700/3'
2026-03-01 01:31:20.176 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.36.20:5808)
2026-03-01 01:31:20.176 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.36.20:5807)
2026-03-01 01:31:20.176 [INFO] fake_trx.py:429 Init complete
2026-03-01 01:31:20.176 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-01 01:31:20.708 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:20.708 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:20.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:20.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:20.709 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:20.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:24.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:24.716 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:24.716 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:24.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:24.717 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 0 -> 1
2026-03-01 01:31:24.723 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:31:24.724 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:31:24.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:24.725 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:24.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:24.726 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:31:24.726 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:24.727 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 0 -> 1
2026-03-01 01:31:24.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:24.730 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:31:24.730 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:31:24.731 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:24.731 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:24.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:24.731 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:31:24.731 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:24.731 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 0 -> 1
2026-03-01 01:31:24.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:24.734 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:31:24.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:31:24.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:24.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:24.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:24.735 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:31:24.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:24.735 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 0 -> 1
2026-03-01 01:31:24.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:31:24.738 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:31:24.738 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:31:24.738 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:24.743 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:31:25.221 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:31:25.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:25.287 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:31:25.290 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:31:25.291 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:31:25.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:25.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:25.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:25.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:25.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:25.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:25.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:25.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:25.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:25.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:25.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:25.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:25.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:25.693 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:31:25.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:25.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:25.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:25.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:25.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:25.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:25.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:25.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:25.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:25.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:25.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:25.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:25.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:25.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:25.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:25.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:25.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:25.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:25.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:25.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:25.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:26.166 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:31:26.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:26.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:26.386 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:26.386 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:26.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:26.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:26.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:26.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:26.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:26.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:26.396 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:26.396 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:26.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:26.639 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:31:26.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:26.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:26.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:26.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:26.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:26.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:26.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:26.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:27.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:27.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:27.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:27.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:27.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:27.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:27.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:27.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:27.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:27.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:27.089 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:27.089 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:27.111 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:31:27.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:27.173 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:27.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:27.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:27.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:27.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:27.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:27.568 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:27.568 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:27.581 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:31:27.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:27.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:27.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:27.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:27.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:27.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:27.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:27.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:27.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:27.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:27.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:27.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:27.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:27.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:27.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:27.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:27.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:28.053 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:31:28.526 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:31:28.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:28.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:28.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:28.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:28.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:28.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:28.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:28.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:28.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:28.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:28.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:28.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:28.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:28.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:28.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:28.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:28.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:28.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:28.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:28.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:28.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:28.999 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:31:29.471 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:31:29.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:29.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:29.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:29.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:29.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:29.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:29.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:29.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:29.632 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:29.633 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:29.633 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:29.633 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:29.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:29.741 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:29.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:29.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:29.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:29.944 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:31:30.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:30.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:30.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:30.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:30.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:30.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:30.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:30.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:30.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:30.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:30.174 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:30.174 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:30.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:30.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:30.415 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:31:30.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:30.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:30.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:30.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:30.888 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:31:31.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:31.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:31.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:31.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:31.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:31.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:31.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:31.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:31.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:31.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:31.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:31.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:31.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:31.360 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:31:31.395 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:31.395 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:31.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:31.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:31.831 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:31:32.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:32.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:32.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:32.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:32.219 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:32.219 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:32.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:32.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:32.220 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:32.220 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:32.220 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:32.220 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:32.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:32.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:32.304 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:31:32.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:32.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:32.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:32.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:32.777 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:31:33.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:33.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:33.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:33.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:33.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:33.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:33.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:33.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:33.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:33.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:33.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:33.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:33.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:33.249 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:31:33.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:33.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:33.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:33.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:33.721 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:31:34.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:34.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:34.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:34.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:34.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:34.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:34.083 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:34.083 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:34.083 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:34.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:34.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:34.191 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:31:34.226 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:34.226 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:34.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:34.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:34.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:34.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:34.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:34.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:34.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:34.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:34.627 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:34.627 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:34.664 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:31:34.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:34.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:34.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:34.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:34.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:34.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:34.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:34.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:34.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:34.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:34.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:34.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:34.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:34.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:34.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:34.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:34.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:34.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.134 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:31:35.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:35.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:35.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:35.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:35.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:35.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:35.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.329 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:35.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:35.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:35.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:35.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:35.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:35.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:35.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.607 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:31:35.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:35.804 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:35.804 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:35.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:35.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:35.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:35.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:35.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:35.825 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:35.825 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:35.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:35.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:35.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:35.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:35.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:36.078 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:31:36.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:36.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:36.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:36.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:36.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:36.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:36.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:36.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:36.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:36.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:36.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:36.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:36.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:36.549 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:31:36.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:36.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:36.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:36.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:36.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:36.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:36.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:36.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:36.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:36.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:36.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:36.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:36.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:36.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:36.963 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:36.963 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:36.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:37.020 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:31:37.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:37.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:37.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:37.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:37.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:37.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:37.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:37.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:37.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:37.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:37.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:37.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:37.491 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:31:37.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:37.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:37.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:37.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.554 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:37.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:37.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:37.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:37.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:37.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:37.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:37.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:37.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:37.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:31:37.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:31:37.965 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:31:37.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:38.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:31:38.025 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:31:38.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:38.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:38.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:31:38.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:38.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:38.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:38.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:38.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:38.424 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:38.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:38.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:38.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:38.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:38.429 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:31:38.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:38.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:38.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:38.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2959 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:38.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2959 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:38.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2959 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:38.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2959 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:38.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2959 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:38.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2959 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:43.431 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:43.431 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:43.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:43.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:43.432 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:43.432 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:43.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:43.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:43.440 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:43.440 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:43.440 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:31:43.445 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:31:43.446 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:31:43.446 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:43.446 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:43.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:43.447 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:31:43.447 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:43.448 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:31:43.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:43.450 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:31:43.450 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:31:43.450 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:43.451 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:43.451 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:43.451 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:31:43.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:43.452 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:31:43.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:43.453 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:31:43.453 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:31:43.453 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:43.453 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:43.453 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:43.453 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:31:43.454 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:43.454 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:31:43.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:31:43.457 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:31:43.458 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:31:43.458 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:31:43.458 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.458 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:43.463 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:31:43.939 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:31:43.979 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:31:43.980 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:31:43.981 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:31:43.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:43.998 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:43.998 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:43.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:44.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 01:31:44.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.407 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:31:44.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:44.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:44.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:44.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:44.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:44.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 01:31:44.871 [DEBUG] clck_gen.py:113 IND CLOCK 306
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2026-03-01 01:31:45.337 [DEBUG] clck_gen.py:113 IND CLOCK 408
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2026-03-01 01:31:45.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:45.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:45.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:45.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:45.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 01:31:45.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:45.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 01:31:45.802 [DEBUG] clck_gen.py:113 IND CLOCK 510
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2026-03-01 01:31:46.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 01:31:46.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.188 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.267 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:31:46.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.389 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:46.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:46.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:46.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:46.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:46.486 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:46.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:46.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:46.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:46.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:46.491 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:46.491 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:46.491 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:31:46.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:46.491 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:46.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:46.492 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=662 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:46.492 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=662 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:46.492 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=662 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:46.492 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=662 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:46.492 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=662 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:46.492 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=662 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:51.494 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:51.494 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:51.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:51.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:51.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:51.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:51.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:51.503 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:51.503 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:51.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:51.504 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:31:51.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:31:51.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:31:51.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:51.508 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:51.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:51.508 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:31:51.509 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:51.509 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:31:51.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:51.511 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:31:51.511 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:31:51.511 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:51.511 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:51.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:51.512 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:31:51.512 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:51.512 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:31:51.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:51.514 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:31:51.514 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:31:51.514 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:51.514 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:51.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:51.514 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:31:51.515 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:51.515 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:31:51.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.519 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:31:51.520 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:31:51.520 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:31:51.520 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.520 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:51.521 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:51.524 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:31:52.002 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:31:52.053 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:31:52.055 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:31:52.057 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:31:52.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:52.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:52.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:52.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:52.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:52.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:52.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:52.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:52.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:52.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:52.096 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:52.096 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:52.096 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:52.096 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:52.096 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:52.096 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:52.097 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:31:52.097 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:52.097 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:52.097 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:52.097 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:52.097 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:52.097 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:57.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:57.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:57.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:57.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:57.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:57.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:57.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:57.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:57.109 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:57.110 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:31:57.110 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:31:57.115 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:31:57.115 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:31:57.115 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:57.115 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:57.115 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:57.115 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:31:57.116 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:31:57.116 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:31:57.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:57.120 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:31:57.120 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:31:57.120 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:57.120 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:57.120 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:57.120 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:31:57.121 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:31:57.121 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:31:57.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:57.124 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:31:57.124 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:31:57.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:57.125 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:31:57.125 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:57.125 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:31:57.125 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:31:57.125 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:31:57.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:57.130 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:31:57.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:31:57.130 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:31:57.130 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:31:57.130 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:31:57.130 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:31:57.132 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:31:57.132 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:31:57.132 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:31:57.137 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:31:57.614 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:31:57.666 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:31:57.667 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:31:57.670 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:31:57.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:31:57.688 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:31:57.688 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:31:57.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:31:57.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:31:57.706 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:31:57.706 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:31:57.706 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:31:57.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:31:57.711 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:31:57.711 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:31:57.711 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:31:57.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:31:57.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:31:57.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:31:57.711 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:57.712 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:57.712 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:57.712 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:57.712 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:31:57.712 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:32:02.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:32:02.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:32:02.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:32:02.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:32:02.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:32:02.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:32:02.724 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:32:02.725 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:32:02.725 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:02.726 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:32:02.726 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:32:02.728 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:32:02.729 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:32:02.729 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:32:02.729 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:02.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:32:02.730 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:32:02.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:32:02.730 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:32:02.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:02.732 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:32:02.732 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:32:02.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:32:02.732 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:02.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:32:02.732 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:32:02.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:32:02.733 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:32:02.733 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:02.735 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:32:02.735 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:32:02.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:32:02.735 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:02.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:32:02.735 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:32:02.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:32:02.735 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:32:02.736 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:32:02.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:32:02.740 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:32:02.740 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:32:02.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:02.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:02.745 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:32:03.222 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:32:03.268 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:32:03.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:03.270 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:32:03.272 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:32:03.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:03.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:03.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:03.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:03.411 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:03.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:03.411 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:03.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:32:03.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:32:03.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:32:03.412 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:32:03.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:32:03.412 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:32:03.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:32:03.413 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=145 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:32:03.413 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=145 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:32:03.413 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=145 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:32:03.413 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=145 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:32:03.413 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=145 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:32:03.413 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=145 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:32:08.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:32:08.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:32:08.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:32:08.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:32:08.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:32:08.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:32:08.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:32:08.423 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:32:08.423 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:08.423 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:32:08.423 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:32:08.426 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:32:08.426 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:32:08.427 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:32:08.427 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:08.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:32:08.427 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:32:08.428 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:32:08.428 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:32:08.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:08.429 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:32:08.430 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:32:08.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:32:08.430 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:08.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:32:08.430 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:32:08.430 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:32:08.431 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:32:08.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:08.433 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:32:08.433 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:32:08.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:32:08.433 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:32:08.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:32:08.433 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:32:08.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:32:08.433 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:32:08.433 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:08.436 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:32:08.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:32:08.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:32:08.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:32:08.436 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:32:08.437 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:32:08.437 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:32:08.437 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:32:08.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:08.442 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:32:08.920 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:32:08.967 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:32:08.970 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:32:08.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:08.972 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:32:08.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:08.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:08.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:09.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:09.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:09.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:09.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:09.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:09.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:09.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:09.023 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:09.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:09.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:09.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:09.393 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:32:09.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:09.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:09.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:09.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:09.866 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:32:10.339 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:32:10.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:10.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:10.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:10.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:10.811 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:32:11.284 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:32:11.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:11.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:11.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:11.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:11.757 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:32:12.229 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:32:12.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:12.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:12.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:12.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:12.703 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:32:13.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:13.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:13.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:13.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:13.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:13.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:13.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:13.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:13.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:13.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:13.134 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:13.134 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:13.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:13.175 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:32:13.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:13.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:13.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:13.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:13.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:13.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:32:13.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:32:13.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:32:13.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:32:13.647 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:32:14.121 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:32:14.593 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:32:15.065 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:32:15.536 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:32:16.010 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:32:16.482 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:32:16.955 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:32:17.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:17.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:17.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:17.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:17.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:17.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:17.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:17.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:17.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:17.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:17.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:17.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:17.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:17.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:17.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:17.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:17.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:17.427 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:32:17.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:17.900 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:32:18.372 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:32:18.843 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:32:19.317 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:32:19.789 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:32:20.261 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:32:20.732 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:32:21.206 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:32:21.678 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:32:21.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:21.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:21.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:21.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:21.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:21.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:21.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:21.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:21.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:21.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:21.875 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:21.875 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:21.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:21.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:21.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:21.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:21.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:22.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:22.150 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:32:22.621 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:32:23.094 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:32:23.567 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:32:24.039 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:32:24.510 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:32:24.984 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:32:25.456 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:32:25.928 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:32:26.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:26.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:26.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:26.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:26.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:26.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:26.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:26.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:26.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:26.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:26.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:26.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:26.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:26.210 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:26.210 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:26.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:26.210 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:26.401 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:32:26.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:26.873 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:32:27.346 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:32:27.819 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:32:28.292 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:32:28.764 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:32:29.238 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:32:29.710 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:32:30.181 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:32:30.655 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:32:30.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:30.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:30.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:30.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:30.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:30.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:30.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:30.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:30.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:30.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:30.763 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:30.763 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:30.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:30.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:30.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:30.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:30.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:31.128 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:32:31.600 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:32:31.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:32.073 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:32:32.546 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:32:33.019 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:32:33.493 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:32:33.965 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:32:34.439 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:32:34.912 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:32:35.384 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:32:35.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:35.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:35.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:35.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:35.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:35.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:35.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:35.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:35.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:35.646 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:35.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:35.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:35.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:35.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:35.665 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:35.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:35.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:35.857 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:32:36.330 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:32:36.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:36.803 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:32:37.273 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:32:37.747 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:32:38.220 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:32:38.693 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:32:39.166 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:32:39.639 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:32:40.112 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:32:40.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:40.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:40.511 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:40.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:40.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:40.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:40.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:40.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:40.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:40.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:40.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:40.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:40.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:40.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:40.584 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:32:40.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:40.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:40.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:40.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:41.056 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:32:41.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:41.528 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:32:42.001 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:32:42.474 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:32:42.946 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 01:32:43.420 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 01:32:43.893 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 01:32:44.366 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 01:32:44.839 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 01:32:45.311 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 01:32:45.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:45.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:45.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:45.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:45.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:45.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:45.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:45.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:45.407 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:45.407 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:45.407 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:45.407 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:45.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:45.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:45.455 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:45.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:45.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:45.782 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 01:32:46.253 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 01:32:46.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:46.726 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 01:32:47.198 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 01:32:47.670 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 01:32:48.144 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 01:32:48.617 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 01:32:49.089 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 01:32:49.560 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 01:32:50.033 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 01:32:50.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:50.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:50.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:50.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:50.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:50.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:50.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:50.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:50.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:50.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:50.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:50.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:50.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:32:50.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:50.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:50.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:50.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:50.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:50.506 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 01:32:50.979 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 01:32:51.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:51.452 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 01:32:51.924 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 01:32:52.397 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 01:32:52.870 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 01:32:53.342 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 01:32:53.815 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 01:32:54.289 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 01:32:54.761 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 01:32:55.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:55.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:55.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:55.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:55.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:55.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:55.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:55.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:55.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:55.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:55.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:55.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:55.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:55.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:55.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:55.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:55.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:55.235 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 01:32:55.707 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 01:32:55.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:56.180 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 01:32:56.654 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 01:32:57.126 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 01:32:57.598 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 01:32:58.069 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 01:32:58.543 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 01:32:59.015 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 01:32:59.487 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 01:32:59.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:59.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:59.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:59.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:59.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:32:59.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:32:59.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:32:59.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:59.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:59.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:59.867 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:32:59.867 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:32:59.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:32:59.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:32:59.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:32:59.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:59.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:32:59.958 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 01:33:00.432 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 01:33:00.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:00.904 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 01:33:01.376 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 01:33:01.847 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 01:33:02.318 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 01:33:02.788 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 01:33:03.259 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 01:33:03.733 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 01:33:04.205 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 01:33:04.678 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 01:33:04.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:04.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:04.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:04.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:04.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:04.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:04.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:04.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:04.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:04.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:04.740 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:04.740 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:04.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:04.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:04.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:04.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:04.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:04.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:05.151 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 01:33:05.623 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 01:33:06.095 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 01:33:06.569 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 01:33:07.041 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 01:33:07.513 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 01:33:07.984 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 01:33:08.458 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 01:33:08.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:08.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:08.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:08.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:08.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:08.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:08.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:08.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:08.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:08.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:08.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:08.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:08.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:08.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:08.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:08.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:08.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:08.930 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 01:33:09.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:09.402 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 01:33:09.873 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 01:33:10.347 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 01:33:10.819 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 01:33:11.291 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 01:33:11.762 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 01:33:12.235 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 01:33:12.707 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 01:33:13.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:13.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:13.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:13.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:13.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:13.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:13.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:13.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:13.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:13.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:13.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:13.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:13.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:13.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:13.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:13.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:13.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:13.179 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 01:33:13.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:13.650 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 01:33:14.121 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 01:33:14.595 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 01:33:15.067 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 01:33:15.539 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 01:33:16.013 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 01:33:16.485 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 01:33:16.957 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 01:33:17.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:17.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:17.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:17.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:17.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:17.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:17.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:17.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:17.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:17.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:17.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:17.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:17.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:17.430 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 01:33:17.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:17.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:17.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:17.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:17.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:17.903 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 01:33:18.375 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 01:33:18.846 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 01:33:19.319 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 01:33:19.791 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 01:33:20.264 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 01:33:20.736 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 01:33:21.209 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 01:33:21.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:21.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:21.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:21.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:21.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:21.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:21.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:21.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:21.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:21.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:21.661 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:21.661 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:21.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:21.681 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 01:33:21.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:21.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:21.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:21.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:22.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:22.152 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 01:33:22.626 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 01:33:23.098 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 01:33:23.570 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 01:33:24.044 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 01:33:24.516 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 01:33:24.988 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 01:33:25.459 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 01:33:25.933 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 01:33:26.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:26.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:26.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:26.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:26.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:26.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:26.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:26.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:26.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:26.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:26.095 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:26.095 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:26.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:26.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:26.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:26.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:26.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:26.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:26.405 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 01:33:26.877 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 01:33:27.348 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 01:33:27.821 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 01:33:28.293 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 01:33:28.766 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 01:33:29.239 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 01:33:29.712 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 01:33:30.184 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 01:33:30.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:30.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:30.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:30.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:30.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:30.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:30.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:30.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:30.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:30.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:30.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:30.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:30.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:30.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:30.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:30.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:30.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:30.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:30.655 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 01:33:31.125 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 01:33:31.596 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 01:33:32.070 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 01:33:32.542 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 01:33:33.014 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 01:33:33.485 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 01:33:33.959 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 01:33:34.431 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-01 01:33:34.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:34.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:34.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:34.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:34.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:34.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:34.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:34.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:34.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:34.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:34.638 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:34.638 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:34.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:34.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:34.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:34.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:34.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:34.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:34.903 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-01 01:33:35.374 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-01 01:33:35.847 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-01 01:33:36.320 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-01 01:33:36.791 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-01 01:33:37.263 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-01 01:33:37.736 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-01 01:33:38.208 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-01 01:33:38.680 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-01 01:33:38.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:38.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:38.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:38.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:38.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:38.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:38.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:38.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:38.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:33:38.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:33:38.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:33:38.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:33:38.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:33:38.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:33:38.891 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:33:43.899 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:33:43.899 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:33:43.899 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:33:43.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:33:43.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:33:43.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:33:43.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:33:43.908 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:33:43.909 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:43.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:33:43.909 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:33:43.912 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:33:43.912 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:33:43.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:33:43.913 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:43.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:33:43.913 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:33:43.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:33:43.913 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:33:43.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:43.917 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:33:43.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:33:43.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:33:43.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:43.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:33:43.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:33:43.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:33:43.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:33:43.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:43.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:33:43.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:33:43.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:33:43.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:43.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:33:43.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:33:43.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:33:43.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:33:43.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:43.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:43.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:43.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:43.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:43.929 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:33:43.929 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:33:43.929 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:33:43.929 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:33:43.929 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:43.929 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:43.929 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:33:43.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:33:43.931 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:43.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:33:48.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:33:48.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:33:48.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:33:48.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:33:48.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:33:48.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:33:48.947 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:33:48.947 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:48.947 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:33:48.947 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:33:48.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:33:48.954 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:33:48.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:33:48.954 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:48.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:33:48.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:33:48.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:33:48.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:33:48.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:48.961 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:33:48.961 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:33:48.961 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:33:48.961 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:48.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:33:48.962 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:33:48.962 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:33:48.962 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:33:48.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:48.967 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:33:48.967 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:33:48.967 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:33:48.968 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:33:48.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:33:48.968 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:33:48.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:33:48.968 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:33:48.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:48.974 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.975 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:33:48.976 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:33:48.976 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:33:48.976 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:33:48.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:33:48.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:48.981 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:33:49.459 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:33:49.507 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:33:49.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:49.510 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:33:49.514 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:33:49.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:49.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:49.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:49.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:49.547 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:49.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:49.548 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:49.548 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:49.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:49.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:49.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:49.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:49.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:49.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:49.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:49.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:49.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:49.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:49.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:49.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:49.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:49.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:49.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:49.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:49.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:49.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:49.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:49.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:49.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:49.931 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:33:49.979 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:49.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:49.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:49.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:50.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:50.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:50.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:50.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:50.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:50.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:50.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.165 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:50.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:50.165 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:50.165 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:50.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:50.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:50.220 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:50.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:50.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:50.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:50.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:50.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:50.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:50.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:50.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:50.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:50.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:50.402 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:33:50.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:50.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:50.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:50.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:50.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.860 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:50.860 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:50.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:50.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:50.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:50.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:50.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:50.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:50.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:50.873 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:33:50.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:50.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:50.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:50.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:50.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:50.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:50.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:50.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:51.344 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:33:51.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:51.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:51.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:51.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:51.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:51.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:51.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:51.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:51.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:51.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:51.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:51.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:51.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:51.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:51.455 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:51.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:51.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:51.815 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:33:51.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:51.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:51.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:51.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:51.921 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=637 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:51.921 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=637 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:51.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:51.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:51.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:51.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:51.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:51.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:51.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:51.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:51.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:51.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:51.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:51.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:51.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:51.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:51.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:51.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:51.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:52.287 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:33:52.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:52.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:52.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:52.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:52.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:52.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:52.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:52.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:52.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:52.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:52.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:52.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:52.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:52.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:52.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:52.532 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:52.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:52.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:52.760 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:33:52.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:52.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:52.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:52.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:53.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:53.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:53.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:53.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:53.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:53.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:53.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.027 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:53.027 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:53.027 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:53.027 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:53.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:53.083 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:53.084 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:53.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.233 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:33:53.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:53.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:53.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:53.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:53.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:53.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:53.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:53.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:53.567 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:53.567 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:53.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:33:53.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:53.615 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:53.616 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:53.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:53.706 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:33:53.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:53.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:53.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:53.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:54.179 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:33:54.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:54.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:54.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:54.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:54.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:54.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:54.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:54.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:54.474 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:54.474 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:54.474 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:54.474 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:54.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:54.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:54.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:54.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:54.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:54.651 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:33:54.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:54.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:54.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:54.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:54.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:54.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:54.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:54.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:54.954 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:54.954 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:54.954 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:54.954 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:54.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:54.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:54.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:54.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:54.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.122 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:33:55.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:55.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:55.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:55.473 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=1404 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:55.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:55.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:55.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:55.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:55.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:55.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:55.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:55.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:55.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:55.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:55.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.593 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:33:55.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:55.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:55.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:55.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:55.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:55.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:55.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:55.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:55.771 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:55.771 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:55.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:55.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:55.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:55.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:55.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.064 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:33:56.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:56.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:56.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:56.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:56.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:56.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:56.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:56.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:56.262 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:56.262 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:56.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:56.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:56.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:56.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.537 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:33:56.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:56.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:56.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:56.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:56.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:56.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:56.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:56.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:56.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:56.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:56.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:56.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:56.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:56.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:56.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.007 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:33:57.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:57.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:57.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:57.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:57.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:57.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:57.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.232 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:57.232 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:57.232 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:57.232 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:57.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:57.290 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:57.290 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:57.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:57.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:57.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:57.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:57.414 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:57.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:57.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:57.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:57.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:57.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:57.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:57.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:57.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:57.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.479 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:33:57.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:57.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:57.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:57.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:57.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:57.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:57.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:57.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:57.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:57.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:57.951 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:33:57.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:57.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:57.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:57.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:57.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:58.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:58.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:58.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:58.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:58.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:58.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:58.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:33:58.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:58.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:58.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:58.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:33:58.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:33:58.423 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:33:58.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:58.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:33:58.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:33:58.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:58.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:58.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:33:58.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:33:58.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:33:58.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:33:58.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:33:58.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:33:58.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:33:58.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:33:58.885 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:33:58.885 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:33:58.885 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:33:58.885 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:33:58.885 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:33:58.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:33:58.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:33:58.885 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2142 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:58.885 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2142 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:58.885 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2142 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:58.885 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2142 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:58.885 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2142 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:33:58.885 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2142 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:03.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:34:03.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:34:03.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:34:03.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:34:03.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:34:03.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:34:03.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:34:03.897 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:34:03.897 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:03.897 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:34:03.897 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:34:03.899 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:34:03.900 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:34:03.900 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:34:03.900 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:03.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:34:03.901 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:34:03.901 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:34:03.901 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:34:03.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:03.902 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:34:03.902 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:34:03.903 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:34:03.903 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:03.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:34:03.903 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:34:03.903 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:34:03.903 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:34:03.903 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:03.905 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:34:03.905 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:34:03.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:34:03.905 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:03.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:34:03.905 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:34:03.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:34:03.905 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:34:03.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:34:03.909 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:34:03.909 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:34:03.909 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:03.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:03.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:03.914 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:34:04.391 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:34:04.433 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:34:04.435 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:34:04.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:04.437 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:34:04.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:04.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:04.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:04.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:04.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:04.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:04.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:04.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:04.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:04.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:04.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:04.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:04.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:04.862 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:34:04.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:04.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:04.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:04.911 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:05.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:05.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:05.334 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:34:05.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:05.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:05.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:05.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:05.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:05.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:05.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:05.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:05.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:05.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:05.549 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:05.549 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:05.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:05.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:05.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:05.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:05.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:05.805 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:34:05.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:05.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:05.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:05.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:06.276 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:34:06.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:06.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:06.749 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:34:06.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:06.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:06.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:06.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:06.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:06.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:06.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:06.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:06.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:06.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:06.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:06.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:06.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:06.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:06.994 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:06.994 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:07.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:07.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:07.049 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:07.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:07.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:07.222 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:34:07.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:07.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:07.694 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:34:07.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:07.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:07.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:07.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:08.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:08.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:08.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:08.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:08.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:08.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:08.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:08.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:08.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:08.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:08.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:08.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:08.165 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:34:08.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:08.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:08.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:08.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:08.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:08.636 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:34:08.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:08.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:08.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:08.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:09.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:09.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:09.109 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:34:09.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:09.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:09.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:09.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:09.582 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:34:09.587 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:09.587 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:09.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:09.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:09.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:09.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:09.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:09.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:09.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:09.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:09.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:09.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:09.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:10.053 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:34:10.527 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:34:10.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:10.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:10.999 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:34:11.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:11.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:11.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:11.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:11.130 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=1560 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:11.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:11.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:11.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:11.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:11.151 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:11.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:11.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:11.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:11.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:11.200 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:11.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:11.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:11.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:11.472 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:34:11.942 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:34:12.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:12.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:12.416 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:34:12.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:12.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:12.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:12.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:12.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:12.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:12.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:12.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:12.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:12.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:12.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:12.656 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:12.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:12.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:12.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:12.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:12.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:12.889 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:34:13.360 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:34:13.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:13.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:13.833 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:34:14.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:14.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:14.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:14.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:14.140 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=2210 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:14.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:14.151 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:14.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:14.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:14.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:14.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:14.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:14.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:14.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:14.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:14.204 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:14.204 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:14.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:14.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:14.306 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:34:14.780 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:34:15.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:15.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:15.252 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:34:15.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:15.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:15.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:15.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:15.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:15.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:15.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:15.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:15.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:15.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:15.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:15.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:15.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:15.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:15.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:15.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:15.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:15.724 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:34:16.195 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:34:16.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:16.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:16.669 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:34:17.142 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:34:17.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:17.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:17.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:17.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:17.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:17.165 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:17.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:17.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:17.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:17.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:17.167 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:17.167 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:17.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:17.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:17.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:17.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:17.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:17.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:17.614 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:34:18.085 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:34:18.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:18.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:18.559 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:34:19.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:19.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:19.014 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:19.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:19.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:19.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:19.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:19.031 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:34:19.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:19.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:19.032 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:19.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:19.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:19.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:19.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:19.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:19.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:19.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:19.503 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:34:19.974 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:34:19.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:19.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:20.445 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:34:20.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:20.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:20.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:20.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:20.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:20.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:20.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:20.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:20.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:20.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:20.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:20.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:20.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:20.536 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:20.536 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:20.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:20.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:20.918 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:34:21.391 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:34:21.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:21.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:21.863 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:34:21.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:21.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:21.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:21.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:21.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:21.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:21.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:21.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:21.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:21.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:21.986 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:21.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:22.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:22.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:22.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:22.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:22.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:22.334 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:34:22.808 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:34:22.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:22.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:23.280 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:34:23.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:23.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:23.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:23.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:23.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:23.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:23.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:23.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:23.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:23.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:23.461 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:23.461 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:23.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:23.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:23.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:23.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:23.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:23.752 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:34:24.223 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:34:24.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:24.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:24.697 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:34:24.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:24.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:24.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:24.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:24.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:24.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:24.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:24.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:24.892 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:24.892 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:24.892 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:24.892 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:24.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:24.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:24.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:24.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:24.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:25.168 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:34:25.640 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:34:25.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:25.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:26.112 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:34:26.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:26.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:26.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:26.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:26.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:26.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:26.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:26.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:26.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:26.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:26.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:26.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:26.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:26.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:26.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:26.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:26.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:26.585 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:34:27.057 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:34:27.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:27.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:27.529 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:34:27.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:27.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:27.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:27.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:27.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:27.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:27.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:27.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:27.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:27.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:27.753 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:27.753 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:27.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:27.808 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:27.808 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:27.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:27.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:28.000 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:34:28.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:28.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:28.473 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:34:28.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:28.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:28.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:28.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:28.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:28.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:28.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:28.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:28.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:28.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:28.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:28.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:28.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:28.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:28.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:28.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:28.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:28.946 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:34:29.418 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:34:29.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:29.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:29.889 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:34:30.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:30.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:30.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:30.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:30.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:30.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:30.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:30.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:30.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:30.321 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:30.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:30.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:30.362 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:34:30.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:30.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:30.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:30.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:30.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:30.834 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:34:31.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:31.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:31.306 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:34:31.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:31.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:31.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:31.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:31.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:31.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:31.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:31.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:31.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:31.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:31.758 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:31.758 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:31.777 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:34:31.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:31.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:31.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:31.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:31.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:32.248 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:34:32.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:32.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:32.721 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:34:33.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:33.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:33.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:33.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:33.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:33.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:33.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:33.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:33.174 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:34:33.174 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:34:33.174 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:34:33.174 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:34:33.174 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:34:33.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:34:33.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:34:33.175 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:33.175 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:33.175 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:33.175 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:33.175 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:33.175 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:34:38.181 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:34:38.181 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:34:38.182 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:34:38.182 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:34:38.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:34:38.182 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:34:38.189 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:34:38.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:34:38.190 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:38.190 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:34:38.191 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:34:38.193 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:34:38.193 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:34:38.193 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:34:38.194 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:38.194 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:34:38.194 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:34:38.195 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:34:38.195 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:34:38.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:38.197 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:34:38.197 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:34:38.197 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:34:38.197 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:38.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:34:38.198 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:34:38.198 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:34:38.198 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:34:38.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:38.201 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:34:38.201 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:34:38.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:34:38.202 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:34:38.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:34:38.202 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:34:38.202 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:34:38.202 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:34:38.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:38.207 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:34:38.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:34:38.207 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:34:38.207 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:34:38.207 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:34:38.207 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.208 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:34:38.208 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:34:38.208 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:34:38.208 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.209 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:34:38.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:34:38.213 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:34:38.689 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:34:38.738 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:34:38.741 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:34:38.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:38.743 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:34:38.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:38.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:38.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:38.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:38.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:38.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:38.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:38.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:38.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:38.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:38.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:38.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:38.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:39.160 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:34:39.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:39.212 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:39.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:39.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:39.632 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:34:40.104 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:34:40.212 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:40.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:40.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:40.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:40.575 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:34:41.048 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:34:41.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:41.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:41.214 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:41.214 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:41.521 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:34:41.993 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:34:42.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:42.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:42.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:42.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:42.464 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:34:42.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:42.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:42.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:42.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:42.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:42.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:42.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:42.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:42.684 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:42.684 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:42.684 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:42.684 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:42.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:42.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:42.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:42.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:42.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:42.937 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:34:43.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:34:43.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:34:43.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:34:43.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:34:43.410 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:34:43.882 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:34:44.356 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:34:44.828 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:34:45.300 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:34:45.774 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:34:46.246 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:34:46.718 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:34:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:46.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:46.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:46.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:46.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:46.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:46.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:46.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:46.959 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:46.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:46.959 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:46.959 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:47.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:47.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:47.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:47.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:47.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:47.192 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:34:47.664 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:34:48.136 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:34:48.607 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:34:49.081 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:34:49.553 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:34:50.025 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:34:50.496 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:34:50.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:50.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:50.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:50.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:50.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:50.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:50.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:50.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:50.953 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:50.953 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:50.953 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:50.953 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:50.969 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:34:50.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:51.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:51.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:51.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:51.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:51.442 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:34:51.914 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:34:52.387 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:34:52.860 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:34:53.332 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:34:53.803 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:34:54.276 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:34:54.749 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:34:55.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:55.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:55.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:55.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:55.213 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:55.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:55.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:55.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:55.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:55.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:55.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:55.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:55.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:55.221 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:34:55.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:55.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:55.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:55.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:55.692 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:34:56.163 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:34:56.637 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:34:57.109 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:34:57.582 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:34:58.055 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:34:58.528 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:34:59.000 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:34:59.474 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:34:59.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:59.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:59.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:59.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:59.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:34:59.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:34:59.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:34:59.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:59.904 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:59.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:59.904 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:34:59.904 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:34:59.946 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:34:59.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:34:59.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:34:59.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:34:59.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:34:59.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:00.418 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:35:00.891 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:35:01.364 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:35:01.838 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:35:02.311 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:35:02.784 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:35:03.257 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:35:03.728 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:35:04.201 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:35:04.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:04.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:04.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:04.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:04.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:04.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:04.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:04.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:04.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:04.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:04.284 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:04.284 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:04.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:04.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:04.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:04.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:04.674 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:35:05.146 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:35:05.620 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:35:06.093 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:35:06.567 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:35:07.039 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:35:07.513 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:35:07.985 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:35:08.458 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:35:08.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:08.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:08.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:08.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:08.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:08.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:08.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:08.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:08.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:08.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:08.692 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:08.692 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:08.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:35:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:08.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:08.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:08.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:08.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:08.931 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:35:09.404 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:35:09.876 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:35:10.347 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:35:10.817 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:35:11.288 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:35:11.762 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:35:12.235 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:35:12.707 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 01:35:13.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:13.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:13.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:13.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:13.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:13.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:13.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:13.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:13.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:13.091 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:13.091 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:13.091 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:13.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:13.139 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:13.139 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:13.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:13.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:13.180 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 01:35:13.653 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 01:35:14.125 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 01:35:14.596 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 01:35:15.069 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 01:35:15.542 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 01:35:16.014 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 01:35:16.488 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 01:35:16.960 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 01:35:17.433 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 01:35:17.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:17.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:17.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:17.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:17.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:17.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:17.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:17.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:17.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:17.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:17.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:17.488 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:17.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:35:17.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:17.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:17.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:17.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:17.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:17.906 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 01:35:18.379 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 01:35:18.851 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 01:35:19.322 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 01:35:19.795 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 01:35:20.268 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 01:35:20.740 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 01:35:21.211 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 01:35:21.685 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 01:35:21.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:21.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:21.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:21.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:21.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:21.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:21.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:21.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:21.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:21.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:21.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:21.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:21.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:21.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:21.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:21.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:21.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:22.157 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 01:35:22.628 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 01:35:23.102 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 01:35:23.574 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 01:35:24.046 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 01:35:24.517 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 01:35:24.991 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 01:35:25.464 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 01:35:25.936 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 01:35:26.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:26.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:26.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:26.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:26.096 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:26.096 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:26.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:26.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:26.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:26.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:26.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:26.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:26.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:26.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:26.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:26.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:26.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:26.409 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 01:35:26.882 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 01:35:27.354 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 01:35:27.825 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 01:35:28.299 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 01:35:28.771 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 01:35:29.244 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 01:35:29.717 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 01:35:30.189 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 01:35:30.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:30.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:30.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:30.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:30.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:30.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:30.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:30.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:30.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:30.488 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:30.488 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:30.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:30.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:30.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:30.540 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:30.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:30.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:30.661 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 01:35:31.132 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 01:35:31.606 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 01:35:32.078 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 01:35:32.550 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 01:35:33.024 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 01:35:33.496 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 01:35:33.968 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 01:35:34.442 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 01:35:34.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:34.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:34.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:34.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:34.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:34.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:34.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:34.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:34.618 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:34.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:34.618 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:34.618 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:34.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:34.676 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:34.676 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:34.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:34.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:34.914 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 01:35:35.386 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 01:35:35.857 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 01:35:36.330 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 01:35:36.803 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 01:35:37.275 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 01:35:37.746 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 01:35:38.219 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 01:35:38.692 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 01:35:38.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:38.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:38.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:38.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:38.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:38.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:38.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:38.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:38.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:38.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:38.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:38.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:38.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:38.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:38.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:38.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:38.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:39.163 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 01:35:39.635 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 01:35:40.108 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 01:35:40.581 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 01:35:41.053 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 01:35:41.524 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 01:35:41.997 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 01:35:42.470 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 01:35:42.942 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 01:35:43.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:43.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:43.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:43.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:43.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:43.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:43.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:43.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:43.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:43.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:43.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:43.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:43.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:43.207 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:43.207 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:43.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:43.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:43.412 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 01:35:43.883 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 01:35:44.354 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 01:35:44.827 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 01:35:45.300 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 01:35:45.772 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 01:35:46.243 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 01:35:46.716 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 01:35:47.188 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 01:35:47.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:47.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:47.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:47.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:47.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:47.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:47.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:47.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:47.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:47.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:47.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:47.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:47.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:47.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:47.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:47.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:47.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:47.660 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 01:35:48.132 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 01:35:48.605 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 01:35:49.077 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 01:35:49.549 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 01:35:50.020 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 01:35:50.494 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 01:35:50.966 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 01:35:51.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:51.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:51.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:51.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:51.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:51.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:51.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:51.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:51.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:51.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:51.382 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:51.382 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:51.438 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 01:35:51.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:51.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:51.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:51.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:51.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:51.909 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 01:35:52.383 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 01:35:52.855 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 01:35:53.327 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 01:35:53.798 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 01:35:54.271 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 01:35:54.744 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 01:35:55.216 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 01:35:55.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:55.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:55.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:55.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:55.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:55.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:55.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:55.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:55.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:55.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:55.649 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:55.649 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:55.687 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 01:35:55.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:55.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:55.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:55.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:55.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:56.158 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 01:35:56.631 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 01:35:57.103 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 01:35:57.576 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 01:35:58.049 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 01:35:58.521 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 01:35:58.994 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 01:35:59.467 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 01:35:59.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:59.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:59.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:59.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:59.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:35:59.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:35:59.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:35:59.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:59.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:59.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:59.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:35:59.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:35:59.939 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 01:35:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:35:59.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:35:59.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:35:59.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:35:59.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:00.411 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 01:36:00.882 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 01:36:01.355 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 01:36:01.828 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 01:36:02.300 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 01:36:02.771 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 01:36:03.243 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 01:36:03.717 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 01:36:04.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:04.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:04.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:04.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:04.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:04.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:04.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:04.181 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:04.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:36:04.185 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:36:04.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:36:04.185 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:36:04.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:36:04.185 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:36:04.186 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:36:04.186 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:36:04.186 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:36:04.186 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:36:04.186 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:36:04.186 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:36:04.186 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:36:09.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:36:09.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:36:09.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:36:09.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:36:09.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:36:09.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:36:09.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:36:09.193 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:36:09.193 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:09.194 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:36:09.194 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:36:09.196 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:36:09.196 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:36:09.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:36:09.197 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:09.197 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:36:09.197 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:36:09.197 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:36:09.197 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:36:09.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:09.199 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:36:09.199 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:36:09.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:36:09.200 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:09.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:36:09.200 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:36:09.200 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:36:09.200 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:36:09.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:09.201 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:36:09.202 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:36:09.202 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:36:09.202 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:09.202 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:36:09.202 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:36:09.202 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:36:09.202 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:36:09.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:09.204 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:36:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:36:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:36:09.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:36:09.205 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:36:09.205 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:36:09.205 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:09.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:36:09.206 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:36:09.206 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:09.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.214 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:36:14.214 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:36:14.214 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:36:14.214 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:36:14.214 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:36:14.214 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:36:14.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:36:14.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:36:14.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:14.225 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:36:14.225 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:36:14.229 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:36:14.229 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:36:14.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:36:14.230 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:14.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:36:14.231 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:36:14.231 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:36:14.231 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:36:14.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:14.233 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:36:14.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:36:14.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:36:14.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:14.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:36:14.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:36:14.234 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:36:14.234 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:36:14.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:14.236 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:36:14.236 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:36:14.236 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:36:14.236 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:36:14.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:36:14.236 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:36:14.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:36:14.237 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:36:14.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:36:14.240 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:36:14.240 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:36:14.240 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.240 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:36:14.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:36:14.245 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:36:14.724 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:36:14.764 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:36:14.765 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:36:14.766 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:36:14.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:14.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:14.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:14.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:14.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:14.792 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:14.792 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:14.792 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:14.792 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:14.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:14.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:14.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:14.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:14.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:15.196 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:36:15.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:15.243 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:15.243 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:15.243 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:15.667 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:36:16.140 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:36:16.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:16.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:16.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:16.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:16.612 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:36:17.084 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:36:17.245 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:17.245 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:17.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:17.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:17.558 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:36:18.030 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:36:18.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:18.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:18.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:18.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:18.502 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:36:18.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:18.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:18.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:18.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:18.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:18.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:18.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:18.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:18.890 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:18.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:18.890 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:18.890 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:18.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:18.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:18.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:18.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:18.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:18.975 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:36:19.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:36:19.248 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:36:19.248 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:36:19.248 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:36:19.448 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:36:19.920 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:36:20.394 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:36:20.866 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:36:21.339 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:36:21.812 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:36:22.284 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:36:22.756 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:36:23.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:23.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:23.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:23.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:23.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:23.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:23.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:23.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:23.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:23.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:23.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:23.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:23.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:23.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:23.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:23.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:23.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:23.229 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:36:23.702 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:36:24.174 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:36:24.645 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:36:25.118 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:36:25.591 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:36:26.063 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:36:26.534 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:36:27.008 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:36:27.480 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:36:27.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:27.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:27.614 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:27.614 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:27.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:27.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:27.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:27.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:27.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:27.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:27.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:27.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:27.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:27.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:27.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:27.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:27.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:27.952 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:36:28.426 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:36:28.898 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:36:29.370 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:36:29.844 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:36:30.316 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:36:30.789 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:36:31.262 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:36:31.735 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:36:31.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:31.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:31.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:31.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:31.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:31.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:31.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:31.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:31.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:31.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:31.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:31.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:31.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:31.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:31.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:31.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:31.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:32.207 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:36:32.678 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:36:33.151 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:36:33.624 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:36:34.096 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:36:34.570 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:36:35.043 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:36:35.516 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:36:35.989 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:36:36.461 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:36:36.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:36.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:36.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:36.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:36.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:36.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:36.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:36.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:36.528 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:36.528 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:36.528 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:36.528 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:36.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:36.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:36.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:36.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:36.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:36.932 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:36:37.406 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:36:37.878 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:36:38.352 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:36:38.825 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:36:39.297 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:36:39.771 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:36:40.244 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:36:40.717 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:36:41.189 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:36:41.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:41.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:41.391 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:41.391 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:41.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:41.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:41.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:41.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:41.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:41.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:41.409 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:41.409 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:41.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:41.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:41.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:41.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:41.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:41.662 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:36:42.135 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:36:42.608 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:36:43.080 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:36:43.551 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:36:44.025 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:36:44.497 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:36:44.970 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:36:45.443 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:36:45.916 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:36:46.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:46.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:46.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:46.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:46.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:46.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:46.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:46.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:46.293 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:46.294 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:46.294 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:46.294 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:46.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:46.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:46.345 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:46.345 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:46.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:46.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:46.388 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:36:46.859 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:36:47.330 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:36:47.801 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:36:48.271 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:36:48.742 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 01:36:49.216 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 01:36:49.688 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 01:36:50.160 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 01:36:50.634 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 01:36:51.106 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 01:36:51.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:51.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:51.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:51.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:51.165 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:51.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:51.166 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:51.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:51.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:51.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:51.168 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:51.168 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:51.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:51.220 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:51.220 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:51.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:51.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:51.579 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 01:36:52.050 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 01:36:52.523 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 01:36:52.996 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 01:36:53.470 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 01:36:53.942 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 01:36:54.415 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 01:36:54.885 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 01:36:55.356 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 01:36:55.827 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 01:36:56.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:56.025 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:56.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:56.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:56.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:36:56.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:36:56.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:36:56.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:56.044 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:56.044 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:56.044 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:36:56.044 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:36:56.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:36:56.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:36:56.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:36:56.097 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:36:56.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:56.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:36:56.298 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 01:36:56.771 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 01:36:57.243 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 01:36:57.716 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 01:36:58.190 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 01:36:58.662 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 01:36:59.134 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 01:36:59.605 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 01:37:00.080 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 01:37:00.552 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 01:37:00.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:00.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:00.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:00.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:00.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:00.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:00.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:00.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:00.796 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:00.796 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:00.796 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:00.796 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:00.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:00.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:00.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:00.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:00.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:01.025 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 01:37:01.498 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 01:37:01.970 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 01:37:02.443 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 01:37:02.916 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 01:37:03.389 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 01:37:03.862 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 01:37:04.335 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 01:37:04.806 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 01:37:05.276 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 01:37:05.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:05.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:05.594 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:05.594 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:05.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:05.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:05.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:05.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:05.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:05.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:05.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:05.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:05.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:05.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:05.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:05.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:05.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:05.747 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 01:37:06.221 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 01:37:06.693 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 01:37:07.166 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 01:37:07.637 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 01:37:08.110 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 01:37:08.582 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 01:37:09.055 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 01:37:09.525 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 01:37:09.996 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 01:37:10.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:10.470 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 01:37:10.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:10.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:10.471 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:10.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:10.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:10.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:10.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:10.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:10.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:10.480 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:10.480 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:10.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:10.532 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:10.532 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:10.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:10.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:10.942 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 01:37:11.414 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 01:37:11.885 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 01:37:12.358 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 01:37:12.831 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 01:37:13.303 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 01:37:13.774 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 01:37:14.247 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 01:37:14.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:14.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:14.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:14.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:14.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:14.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:14.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:14.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:14.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:14.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:14.594 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:14.594 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:14.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:14.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:14.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:14.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:14.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:14.719 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 01:37:15.191 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 01:37:15.662 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 01:37:16.136 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 01:37:16.608 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 01:37:17.080 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 01:37:17.551 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 01:37:18.024 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 01:37:18.497 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 01:37:18.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:18.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:18.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:18.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:18.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:18.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:18.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:18.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:18.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:18.858 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:18.858 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:18.858 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:18.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:18.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:18.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:18.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:18.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:18.969 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 01:37:19.440 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 01:37:19.914 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 01:37:20.386 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 01:37:20.858 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 01:37:21.329 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 01:37:21.803 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 01:37:22.275 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 01:37:22.747 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 01:37:23.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:23.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:23.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:23.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:23.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:23.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:23.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:23.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:23.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:23.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:23.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:23.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:23.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:23.183 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:23.183 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:23.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:23.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:23.218 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 01:37:23.689 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 01:37:24.162 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 01:37:24.635 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 01:37:25.107 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 01:37:25.579 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 01:37:26.052 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 01:37:26.524 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 01:37:26.998 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 01:37:27.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:27.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:27.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:27.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:27.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:27.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:27.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:27.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:27.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:27.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:27.392 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:27.392 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:27.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:27.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:27.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:27.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:27.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:27.468 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 01:37:27.941 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 01:37:28.413 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 01:37:28.884 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 01:37:29.357 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 01:37:29.830 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 01:37:30.302 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 01:37:30.776 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 01:37:31.248 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 01:37:31.720 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 01:37:31.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:31.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:31.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:31.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:31.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:31.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:31.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:31.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:31.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:31.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:31.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:31.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:31.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:31.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:31.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:31.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:31.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:32.191 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 01:37:32.664 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 01:37:33.137 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 01:37:33.608 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 01:37:34.080 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 01:37:34.553 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 01:37:35.025 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 01:37:35.498 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 01:37:35.971 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 01:37:36.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:36.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:36.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:36.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:36.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:36.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:36.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:36.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:36.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:36.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:36.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:36.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:36.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:36.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:36.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:36.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:36.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:36.443 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 01:37:36.915 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 01:37:37.387 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 01:37:37.857 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 01:37:38.331 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 01:37:38.803 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 01:37:39.275 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 01:37:39.748 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 01:37:40.220 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-01 01:37:40.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:40.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:40.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:40.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:40.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:40.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:40.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:40.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:40.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:40.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:40.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:40.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:40.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:40.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:40.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:40.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:40.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:40.692 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-01 01:37:41.164 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-01 01:37:41.637 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-01 01:37:42.109 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-01 01:37:42.581 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-01 01:37:43.052 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-01 01:37:43.526 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-01 01:37:43.998 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-01 01:37:44.471 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-01 01:37:44.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:44.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:44.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:44.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:44.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:44.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:44.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:44.627 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:44.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:37:44.631 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:37:44.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:37:44.631 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:37:44.631 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:37:44.631 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:37:44.631 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:37:44.632 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=19519 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:37:44.632 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=19519 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:37:44.632 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=19519 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:37:44.632 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=19519 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:37:44.632 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=19519 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:37:44.632 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=19519 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:37:44.632 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=19519 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:37:49.633 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:37:49.633 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:37:49.633 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:37:49.633 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:37:49.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:37:49.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:37:49.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:37:49.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:37:49.642 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:49.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:37:49.643 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:37:49.646 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:37:49.647 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:37:49.647 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:37:49.647 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:49.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:37:49.648 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:37:49.648 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:37:49.648 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:37:49.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:49.651 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:37:49.651 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:37:49.651 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:37:49.652 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:49.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:37:49.652 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:37:49.652 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:37:49.652 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:37:49.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:49.654 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:37:49.655 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:37:49.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:37:49.655 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:49.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:37:49.655 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:37:49.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:37:49.655 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:37:49.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:37:49.659 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:37:49.659 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:37:49.659 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:37:49.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:37:49.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:37:49.661 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:49.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:37:54.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:37:54.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:37:54.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:37:54.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:37:54.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:37:54.677 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:37:54.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:37:54.679 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:54.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:37:54.679 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:37:54.682 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:37:54.683 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:37:54.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:37:54.683 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:54.683 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:37:54.684 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:37:54.684 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:37:54.684 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:37:54.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:54.685 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:37:54.686 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:37:54.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:37:54.686 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:54.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:37:54.686 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:37:54.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:37:54.687 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:37:54.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:54.688 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:37:54.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:37:54.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:37:54.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:37:54.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:37:54.688 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:37:54.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:37:54.689 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:37:54.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:37:54.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:37:54.692 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:37:54.692 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:37:54.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:37:54.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:37:54.696 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:37:55.173 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:37:55.226 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:37:55.228 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:37:55.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:55.231 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:37:55.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:55.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:55.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:55.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:55.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:55.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:55.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:55.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:55.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:55.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:55.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:55.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:55.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:55.645 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:37:55.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:55.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:55.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:55.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:56.116 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:37:56.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:56.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:56.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:56.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:56.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:56.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:56.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:56.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:56.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:56.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:56.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:56.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:56.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:56.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:56.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:56.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:56.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:56.587 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:37:56.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:56.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:56.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:56.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:57.061 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:37:57.533 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:37:57.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:57.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:57.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:57.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:57.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:57.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:57.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:57.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:57.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:57.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:57.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:57.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:57.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:57.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:57.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:57.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:57.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:57.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:57.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:57.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:57.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:58.005 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:37:58.476 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:37:58.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:58.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:58.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:58.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:58.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:58.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:58.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:58.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:58.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:37:58.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:37:58.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:37:58.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:58.934 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:58.934 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:58.934 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:37:58.934 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:37:58.946 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:37:58.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:37:58.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:37:58.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:37:58.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:58.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:37:59.417 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:37:59.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:37:59.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:37:59.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:37:59.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:37:59.891 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:38:00.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:00.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:00.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:00.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:00.363 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:38:00.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:00.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:00.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:00.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:00.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:00.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:00.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:00.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:00.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:00.419 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:00.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:00.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:00.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:00.836 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:38:01.309 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:38:01.782 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:38:01.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:01.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:01.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:01.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:01.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:01.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:01.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:01.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:01.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:01.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:01.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:01.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:01.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:01.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:01.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:01.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:01.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:02.254 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:38:02.725 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:38:03.198 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:38:03.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:03.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:03.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:03.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:03.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:03.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:03.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:03.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:03.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:03.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:03.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:03.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:03.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:03.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:03.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:03.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:03.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:03.671 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:38:04.143 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:38:04.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:04.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:04.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:04.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:04.456 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:04.456 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:04.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:04.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:04.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:04.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:04.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:04.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:04.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:04.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:04.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:04.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:04.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:04.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:04.617 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:38:05.089 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:38:05.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:05.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:05.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:05.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:05.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:05.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:05.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:05.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:05.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:05.484 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:05.484 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:05.484 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:05.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:05.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:05.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:05.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:05.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:05.561 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:38:06.032 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:38:06.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:06.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:06.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:06.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:06.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:06.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:06.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:06.503 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:38:06.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:06.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:06.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:06.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:06.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:06.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:06.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:06.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:06.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:06.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:06.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:06.974 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:38:07.448 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:38:07.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:07.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:07.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:07.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:07.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:07.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:07.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:07.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:07.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:07.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:07.884 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:07.884 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:07.920 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:38:07.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:07.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:07.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:07.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:07.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:08.392 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:38:08.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:08.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:08.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:08.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:08.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:08.848 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:08.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:08.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:08.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:08.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:08.851 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:08.851 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:08.862 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:38:08.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:08.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:08.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:08.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:08.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:09.334 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:38:09.807 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:38:09.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:09.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:09.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:09.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:09.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:09.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:09.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:09.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:09.873 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:09.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:09.873 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:09.873 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:09.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:09.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:09.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:09.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:09.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:10.279 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:38:10.751 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:38:10.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:10.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:10.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:10.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:10.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:10.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:10.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:10.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:10.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:10.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:10.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:10.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:10.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:10.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:10.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:10.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:11.222 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:38:11.696 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:38:12.168 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:38:12.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:12.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:12.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:12.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:12.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:12.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:12.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:12.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:12.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:12.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:12.370 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:12.370 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:12.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:12.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:12.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:12.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:12.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:12.640 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:38:13.111 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:38:13.584 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:38:13.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:13.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:13.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:13.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:13.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:13.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:13.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:13.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:13.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:13.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:13.798 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:13.799 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:13.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:13.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:13.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:13.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:13.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:14.057 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:38:14.529 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:38:15.000 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:38:15.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:15.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:15.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:15.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:15.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:15.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:15.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:15.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:15.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:15.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:15.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:15.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:15.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:15.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:15.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:15.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:15.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:15.473 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:38:15.946 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:38:16.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:16.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:16.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:16.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:16.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:16.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:16.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:16.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:16.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:16.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:16.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:16.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:16.418 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:38:16.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:16.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:16.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:16.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:16.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:16.889 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:38:17.362 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:38:17.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:17.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:17.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:17.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:17.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:17.781 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:17.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:17.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:17.783 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:17.783 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:17.783 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:17.783 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:17.834 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:38:17.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:17.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:17.851 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:17.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:17.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:18.306 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:38:18.777 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:38:19.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:19.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:19.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:19.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:19.226 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:19.226 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:19.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:19.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:19.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:19.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:19.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:19.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:19.248 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:38:19.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:19.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:19.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:19.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:19.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:19.722 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:38:20.194 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:38:20.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:20.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:20.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:20.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:20.656 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:20.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:20.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:20.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:20.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:38:20.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:38:20.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:38:20.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:38:20.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:38:20.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:38:20.662 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:38:20.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5611 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:20.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5611 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:20.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5611 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:20.663 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5611 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:20.663 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5611 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:20.663 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5611 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:25.664 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:38:25.664 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:38:25.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:38:25.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:38:25.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:38:25.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:38:25.670 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:38:25.671 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:38:25.671 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:38:25.671 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:38:25.671 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:38:25.674 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:38:25.675 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:38:25.675 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:38:25.675 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:38:25.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:38:25.676 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:38:25.676 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:38:25.676 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:38:25.677 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:25.680 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:38:25.680 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:38:25.680 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:38:25.681 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:38:25.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:38:25.681 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:38:25.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:38:25.681 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:38:25.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:25.684 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:38:25.684 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:38:25.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:38:25.684 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:38:25.685 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:38:25.685 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:38:25.685 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:38:25.685 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:38:25.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:25.690 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:38:25.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:38:25.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:38:25.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:38:25.690 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:38:25.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:38:25.691 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:38:25.691 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:38:25.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:38:25.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:38:25.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:38:25.696 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:38:26.172 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:38:26.226 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:38:26.228 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:38:26.230 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:38:26.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:26.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:26.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:26.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:26.260 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:26.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:26.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:26.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:26.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:26.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:26.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:26.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:26.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:26.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:26.642 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:38:26.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:26.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:26.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:26.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:27.115 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:38:27.587 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:38:27.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:27.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:27.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:27.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:28.058 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:38:28.532 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:38:28.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:28.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:28.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:28.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:29.004 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:38:29.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:29.477 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:38:29.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:29.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:29.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:29.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:29.951 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:38:30.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:30.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:30.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:30.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:30.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:30.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:30.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:30.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:30.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:30.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:30.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:30.042 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:30.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:30.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:30.423 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:38:30.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:30.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:30.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:30.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:30.896 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:38:31.369 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:38:31.841 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:38:32.314 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:38:32.785 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:38:33.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:33.258 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:38:33.731 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:38:33.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:33.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:33.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:33.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:33.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:33.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:33.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:33.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:33.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:33.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:33.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:33.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:33.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:33.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:33.945 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:33.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:33.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:34.202 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:38:34.676 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:38:35.148 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:38:35.620 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:38:36.091 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:38:36.565 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:38:36.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:37.037 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:38:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:37.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:37.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:37.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:37.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:37.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:37.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:37.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:37.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:37.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:37.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:37.509 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:38:37.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:37.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:37.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:37.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:37.980 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:38:38.451 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:38:38.922 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:38:39.395 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:38:39.867 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:38:40.340 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:38:40.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:40.814 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:38:41.286 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:38:41.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:41.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:41.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:41.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:41.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:41.361 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:41.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:41.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:41.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:41.364 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:41.364 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:41.364 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:41.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:41.412 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:41.412 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:41.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:41.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:41.758 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:38:42.229 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:38:42.703 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:38:43.175 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:38:43.647 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:38:44.118 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:38:44.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:44.589 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:38:45.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:45.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:45.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:45.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:45.028 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=4177 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:45.028 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=4177 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:38:45.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:45.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:45.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:45.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:45.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:45.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:45.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:45.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:45.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:45.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:45.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:45.062 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:38:45.535 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:38:46.007 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:38:46.481 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:38:46.953 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:38:47.425 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:38:47.896 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:38:48.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:48.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:48.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:48.335 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:48.335 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:48.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:48.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:48.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:48.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:48.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:48.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:48.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:48.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:48.369 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:38:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:48.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:48.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:48.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:48.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:48.842 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:38:49.314 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:38:49.785 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:38:50.258 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:38:50.731 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:38:51.202 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:38:51.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:51.674 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:38:52.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:52.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:52.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:52.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:52.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:38:52.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:52.068 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:52.068 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:52.068 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:38:52.068 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:38:52.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:38:52.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:38:52.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:38:52.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:52.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:52.147 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:38:52.620 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:38:53.092 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:38:53.566 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:38:54.038 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:38:54.510 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:38:54.983 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:38:55.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:55.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:38:55.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:38:55.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:38:55.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:38:55.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:38:55.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:38:55.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:38:55.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:38:55.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:38:55.390 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:38:55.390 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:38:55.390 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:38:55.390 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:38:55.390 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:38:55.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:39:00.394 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:39:00.394 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:39:00.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:39:00.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:39:00.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:39:00.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:39:00.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:39:00.403 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:39:00.403 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:00.404 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:39:00.404 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:39:00.407 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:39:00.407 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:39:00.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:39:00.408 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:00.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:39:00.408 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:39:00.408 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:39:00.408 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:39:00.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:00.410 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:39:00.410 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:39:00.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:39:00.411 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:00.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:39:00.411 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:39:00.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:39:00.411 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:39:00.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:00.412 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:39:00.412 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:39:00.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:39:00.413 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:00.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:39:00.413 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:39:00.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:39:00.413 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:39:00.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:00.415 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:39:00.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:39:00.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:39:00.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:39:00.415 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:39:00.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:39:00.416 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:39:00.416 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:39:00.416 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:00.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:00.421 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:39:00.899 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:39:00.939 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:39:00.941 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:39:00.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:00.943 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:39:00.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:00.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:00.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:00.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:00.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:00.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:00.967 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:00.967 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:00.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:01.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:01.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:01.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:01.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:01.372 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:39:01.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:01.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:01.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:01.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:01.843 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:39:02.313 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:39:02.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:02.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:02.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:02.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:02.786 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:39:03.259 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:39:03.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:03.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:03.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:03.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:03.732 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:39:04.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:04.206 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:39:04.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:04.422 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:04.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:04.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:04.678 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:39:04.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:04.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:04.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:04.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:04.753 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=936 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:04.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:04.753 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=936 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:04.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:04.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:04.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:04.754 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:04.754 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:04.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:04.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:04.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:04.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:04.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:05.152 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:39:05.421 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:05.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:05.423 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:05.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:05.625 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:39:06.097 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:39:06.571 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:39:07.043 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:39:07.516 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:39:07.774 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:07.986 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:39:08.457 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:39:08.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:08.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:08.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:08.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:08.605 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=1768 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:08.605 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=1768 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:08.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:08.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:08.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:08.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:08.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:08.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:08.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:08.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:08.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:08.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:08.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:08.931 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:39:09.403 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:39:09.876 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:39:10.350 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:39:10.822 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:39:11.293 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:39:11.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:11.767 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:39:12.239 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:39:12.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:12.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:12.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:12.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:12.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:12.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:12.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:12.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:12.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:12.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:12.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:12.478 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:12.478 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:12.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:12.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:12.711 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:39:12.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:13.185 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:39:13.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:13.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:13.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:13.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:13.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:13.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:13.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:13.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:13.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:13.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:13.443 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:13.443 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:13.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:13.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:13.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:13.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:13.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:13.657 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:39:14.130 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:39:14.603 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:39:15.076 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:39:15.548 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:39:16.019 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:39:16.493 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:39:16.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:16.965 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:39:17.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:17.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:17.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:17.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:17.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:17.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:17.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:17.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:17.041 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:17.041 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:17.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:17.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:17.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:17.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:17.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:17.436 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:39:17.909 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:39:18.382 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:39:18.855 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:39:19.328 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:39:19.800 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:39:20.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:20.272 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:39:20.744 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:39:20.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:20.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:20.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:20.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:20.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:20.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:20.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:20.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:20.895 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:20.895 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:20.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:20.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:20.929 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:20.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:20.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:21.217 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:39:21.689 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:39:22.162 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:39:22.635 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:39:23.108 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:39:23.580 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:39:23.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:24.051 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:39:24.524 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:39:24.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:24.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:24.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:24.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:24.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:24.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:24.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:24.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:24.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:24.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:24.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:24.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:24.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:24.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:24.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:24.997 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:39:25.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:25.469 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:39:25.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:25.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:25.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:25.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:25.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:25.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:25.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:25.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:25.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:25.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:25.731 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:25.731 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:25.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:25.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:25.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:25.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:25.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:25.940 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:39:26.414 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:39:26.886 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:39:27.358 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:39:27.829 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:39:28.303 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:39:28.775 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:39:28.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:29.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:29.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:29.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:29.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:29.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:29.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:29.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:29.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:29.216 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:29.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:29.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:29.247 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:39:29.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:29.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:29.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:29.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:29.718 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:39:30.189 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:39:30.662 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:39:31.135 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:39:31.607 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:39:32.078 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:39:32.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:32.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:32.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:32.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:32.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:32.516 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6931 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:32.516 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6931 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:32.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:32.517 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6931 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:32.517 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6931 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:39:32.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:32.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:32.518 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:32.518 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:32.519 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:32.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:32.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:32.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:32.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:32.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:32.551 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:39:33.024 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:39:33.496 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:39:33.969 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:39:34.442 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:39:34.914 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 01:39:35.385 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 01:39:35.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:35.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:35.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:35.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:35.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:35.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:35.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:35.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:35.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:35.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:35.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:35.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:35.856 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:35.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:35.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:35.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:35.859 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 01:39:36.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:36.331 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 01:39:36.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:36.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:36.771 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:36.771 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:36.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:36.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:36.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:36.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:36.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:36.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:36.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:36.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:36.803 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 01:39:36.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:36.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:36.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:36.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:36.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:37.274 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 01:39:37.747 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 01:39:38.220 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 01:39:38.692 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 01:39:39.163 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 01:39:39.637 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 01:39:40.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:40.109 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 01:39:40.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:40.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:40.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:40.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:40.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:40.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:40.504 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:40.504 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:40.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:40.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:40.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:40.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:40.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:40.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:40.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:40.583 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 01:39:41.055 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 01:39:41.527 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 01:39:41.998 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 01:39:42.471 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 01:39:42.944 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 01:39:43.416 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 01:39:43.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:43.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:43.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:43.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:43.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:43.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:43.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:43.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:43.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:43.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:43.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:43.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:43.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:43.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:43.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:43.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:43.887 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 01:39:44.360 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 01:39:44.832 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 01:39:45.305 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 01:39:45.776 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 01:39:46.249 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 01:39:46.721 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 01:39:46.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:47.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:47.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:47.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:47.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:47.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:47.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:47.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:47.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:47.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:47.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:47.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:39:47.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:47.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:47.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:47.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:47.193 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 01:39:47.664 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 01:39:47.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:48.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:48.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:48.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:48.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:48.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:48.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:48.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:48.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:48.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:39:48.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:39:48.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:39:48.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:39:48.073 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:39:48.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:39:48.073 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:39:53.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:39:53.077 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:39:53.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:39:53.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:39:53.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:39:53.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:39:53.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:39:53.084 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:39:53.084 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:53.084 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:39:53.084 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:39:53.086 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:39:53.086 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:39:53.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:39:53.087 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:53.087 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:39:53.087 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:39:53.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:39:53.087 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:39:53.087 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:53.089 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:39:53.089 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:39:53.089 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:39:53.089 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:53.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:39:53.089 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:39:53.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:39:53.090 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:39:53.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:53.091 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:39:53.092 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:39:53.092 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:39:53.092 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:39:53.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:39:53.092 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:39:53.092 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:39:53.092 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:39:53.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:39:53.094 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:39:53.094 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:39:53.094 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:39:53.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:39:53.099 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:39:53.577 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:39:53.620 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:39:53.623 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:39:53.625 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:39:53.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:39:53.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:39:53.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:39:53.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:39:53.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:39:53.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:39:53.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:39:53.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:39:53.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:39:54.049 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:39:54.097 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:54.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:54.098 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:54.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:54.518 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:39:54.986 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:39:55.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:55.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:55.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:55.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:55.457 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:39:55.928 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:39:56.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:56.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:56.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:56.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:56.401 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:39:56.874 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:39:57.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:57.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:57.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:57.101 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:57.342 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:39:57.813 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:39:58.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:39:58.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:39:58.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:39:58.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:39:58.283 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:39:58.756 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:39:59.224 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:39:59.695 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:40:00.167 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:40:00.637 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:40:01.108 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:40:01.579 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:40:02.050 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:40:02.396 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:02.396 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:02.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:02.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:02.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:02.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:02.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:02.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:02.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:02.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:02.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:02.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:02.404 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:40:02.404 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:02.404 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:02.404 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:02.404 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:02.404 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:02.404 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:07.407 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:07.407 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:07.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:07.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:07.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:07.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:07.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:07.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:07.416 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:07.417 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:07.417 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:40:07.420 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:40:07.420 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:40:07.420 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:07.420 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:07.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:07.421 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:40:07.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:07.421 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:40:07.421 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:07.422 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:40:07.422 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:40:07.423 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:07.423 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:07.423 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:07.423 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:40:07.423 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:07.423 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:40:07.423 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:07.425 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:40:07.425 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:40:07.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:07.425 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:07.425 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:07.425 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:40:07.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:07.425 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:40:07.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:40:07.428 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:40:07.428 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:40:07.428 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:07.433 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:40:07.911 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:40:07.951 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:07.953 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:40:07.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:07.956 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:40:07.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:07.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:07.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:07.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:07.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:07.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:07.960 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:07.960 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:08.384 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:40:08.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:08.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:08.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:08.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:08.857 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:40:09.330 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:40:09.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:09.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:09.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:09.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:09.802 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:40:10.273 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:40:10.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:10.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:10.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:10.433 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:10.743 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:40:11.214 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:40:11.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:11.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:11.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:11.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:11.685 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:40:12.156 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:40:12.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:12.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:12.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:12.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:12.627 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:40:13.097 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:40:13.568 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:40:14.039 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:40:14.510 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:40:14.980 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:40:15.451 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:40:15.922 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:40:16.393 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:40:16.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:16.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:16.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:16.740 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:16.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:16.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:16.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:16.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:16.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:16.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:16.744 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:16.744 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:16.744 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:40:16.745 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2016 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:16.745 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2016 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:16.745 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2016 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:16.745 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2016 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:16.745 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2016 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:16.745 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2016 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:21.745 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:21.745 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:21.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:21.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:21.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:21.746 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:21.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:21.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:21.749 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:21.749 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:21.749 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:40:21.750 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:40:21.750 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:40:21.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:21.750 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:21.750 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:21.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:40:21.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:21.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:40:21.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:21.751 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:40:21.751 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:40:21.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:21.751 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:21.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:21.751 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:40:21.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:21.751 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:40:21.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:21.752 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:40:21.752 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:40:21.752 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:21.752 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:21.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:21.753 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:40:21.753 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:21.753 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:40:21.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:21.754 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:40:21.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:40:21.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:40:21.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:40:21.754 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:40:21.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:40:21.755 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:40:21.755 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:40:21.755 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:21.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:21.759 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:40:22.238 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:40:22.280 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:22.282 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:40:22.284 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:40:22.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:22.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:22.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:22.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:22.710 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:40:22.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:22.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:22.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:22.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:23.184 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:40:23.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:23.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:23.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:23.290 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:23.290 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:23.656 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:40:23.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:23.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:23.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:23.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:24.128 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:40:24.595 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:40:24.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:24.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:24.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:24.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:25.065 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:40:25.534 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:40:25.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:25.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:25.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:25.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:26.002 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:40:26.473 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:40:26.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:26.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:26.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:26.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:26.944 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:40:27.414 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:40:27.885 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:40:28.356 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:40:28.827 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:40:29.297 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:40:29.768 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:40:30.239 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:40:30.709 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:40:31.180 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:40:31.651 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:40:32.121 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:40:32.593 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:40:33.065 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:40:33.536 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:40:34.007 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:40:34.480 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:40:34.952 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:40:35.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:35.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:35.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:35.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:35.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:35.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:35.081 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:35.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:35.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:35.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:35.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:35.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:35.082 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:40:35.083 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2886 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:35.083 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2886 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:35.083 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2886 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:35.083 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2886 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:35.083 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2886 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:35.083 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2886 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:35.083 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2886 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:40.084 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:40.084 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:40.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:40.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:40.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:40.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:40.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:40.095 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:40.096 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:40.096 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:40.096 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:40:40.101 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:40:40.101 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:40:40.101 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:40.101 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:40.101 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:40:40.101 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:40.102 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:40.102 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:40:40.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:40.107 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:40:40.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:40:40.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:40.107 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:40.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:40.108 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:40:40.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:40.108 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:40:40.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:40.111 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:40:40.111 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:40:40.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:40.111 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:40.111 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:40.111 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:40:40.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:40.111 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:40:40.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:40:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:40:40.116 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:40:40.116 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:40:40.116 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:40.121 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:40:40.599 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:40:40.649 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:40.652 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:40:40.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:40.654 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:40:40.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:40.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:40.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:40.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:40.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:40.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:40.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:40.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:41.071 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:40:41.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:41.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:41.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:41.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:41.543 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:40:41.690 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:42.016 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:40:42.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:42.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:42.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:42.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:42.215 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:42.489 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:40:42.737 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:42.961 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:40:43.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:43.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:43.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:43.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:43.435 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:40:43.907 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:40:44.123 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:44.123 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:44.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:44.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:44.379 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:40:44.752 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:44.850 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:40:45.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:45.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:45.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:45.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:45.286 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:45.324 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:40:45.796 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:40:45.809 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:46.268 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:40:46.326 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:46.739 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:40:47.212 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:40:47.685 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:40:48.157 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:40:48.332 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:48.631 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:40:49.103 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:40:49.574 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:40:50.046 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:40:50.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:50.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:50.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:50.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:50.380 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:40:55.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:55.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:55.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:55.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:55.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:55.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:55.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:55.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:55.398 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:55.398 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:40:55.398 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:40:55.403 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:40:55.404 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:40:55.404 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:55.404 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:55.405 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:55.405 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:40:55.406 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:40:55.406 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:40:55.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:55.408 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:40:55.409 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:40:55.409 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:55.409 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:55.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:55.410 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:40:55.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:40:55.411 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:40:55.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:55.413 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:40:55.413 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:40:55.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:55.413 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:40:55.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:55.413 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:40:55.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:40:55.413 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:40:55.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:55.417 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:40:55.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:40:55.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:40:55.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:40:55.417 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:40:55.418 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:40:55.418 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.418 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:40:55.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:55.423 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:40:55.902 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:40:55.951 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:40:55.954 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:40:55.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:55.956 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:40:55.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:55.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:55.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:55.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:55.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:55.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:55.984 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:55.984 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:55.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:56.002 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.002 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.002 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:56.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.094 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:56.094 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:56.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:56.144 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.145 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:56.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.346 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:56.346 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:56.373 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:40:56.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:56.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:56.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:56.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:56.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:56.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:56.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:56.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:56.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.845 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:40:56.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:56.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.865 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:56.865 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:56.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:56.897 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.897 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:56.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:56.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:56.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:56.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:56.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:56.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:56.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:56.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:56.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:56.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:56.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:56.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:56.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:56.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.011 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.011 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.012 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.012 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.012 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.013 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:57.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.070 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.070 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.070 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.070 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.078 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.078 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.105 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.105 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:40:57.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.202 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.202 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.202 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.258 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.258 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.262 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.314 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:40:57.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.385 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=425 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:57.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.404 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.404 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.404 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:57.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:57.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:57.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:57.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.638 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.659 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.659 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.659 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.662 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.662 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.662 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.662 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.696 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:40:57.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:57.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:57.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:57.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:57.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:57.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:57.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:57.918 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:57.918 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:57.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:57.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:58.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:58.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:58.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:58.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.169 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.169 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:58.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.171 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:58.171 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:58.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:58.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.250 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:40:58.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.407 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:58.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:58.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:58.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:58.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:58.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:58.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:58.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:58.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:40:58.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.439 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.439 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.439 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:40:58.439 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:40:58.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:40:58.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:40:58.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:40:58.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:40:58.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:40:58.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:40:58.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:40:58.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:40:58.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:40:58.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:40:58.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:40:58.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:40:58.690 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:40:58.690 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:40:58.690 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:40:58.690 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:40:58.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:40:58.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:40:58.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=710 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:58.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=710 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:58.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=710 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:58.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=710 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:58.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=710 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:40:58.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=710 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:03.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:03.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:03.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:03.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:03.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:03.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:03.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:03.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:03.706 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:03.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:03.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:41:03.707 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:41:03.707 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:41:03.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:03.707 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:03.707 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:03.707 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:41:03.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:03.707 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:41:03.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:03.708 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:41:03.708 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:41:03.708 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:03.708 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:03.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:03.709 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:41:03.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:03.709 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:41:03.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:03.712 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:41:03.712 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:41:03.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:03.712 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:03.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:03.712 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:41:03.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:03.712 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:41:03.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:03.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:41:03.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:41:03.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:41:03.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:41:03.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:41:03.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:41:03.717 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:41:03.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:03.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:03.722 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:41:04.199 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:41:04.240 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:41:04.241 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:41:04.241 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:41:04.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:41:04.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:41:04.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:41:04.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:41:04.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:41:04.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:41:04.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:41:04.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:41:04.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:41:04.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 01:41:04.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:41:04.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:41:04.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:41:04.303 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:41:04.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:41:04.672 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:41:04.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:04.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:04.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:04.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:05.143 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:41:05.617 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:41:05.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:05.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:05.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:05.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:06.089 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:41:06.361 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:41:06.362 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:41:06.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:06.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:06.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:06.366 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:06.368 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:06.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:06.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:06.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:06.368 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:06.368 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:06.368 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:41:06.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=572 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:11.374 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:11.374 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:11.374 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:11.374 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:11.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:11.374 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:11.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:11.384 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:11.384 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:11.384 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:11.384 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:41:11.389 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:41:11.389 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:41:11.389 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:11.389 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:11.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:11.389 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:41:11.390 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:11.390 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:41:11.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:11.393 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:41:11.394 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:41:11.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:11.394 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:11.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:11.394 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:41:11.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:11.394 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:41:11.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:11.397 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:41:11.398 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:41:11.398 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:11.398 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:11.398 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:11.398 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:41:11.398 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:11.398 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:41:11.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:11.403 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:41:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:41:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:41:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:41:11.403 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:41:11.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:41:11.404 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:41:11.404 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:41:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:11.404 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:41:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:11.406 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:11.406 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:11.406 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:16.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:16.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:16.412 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:16.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:16.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:16.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:16.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:16.421 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:16.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:16.421 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:41:16.424 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:41:16.425 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:41:16.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:16.425 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:16.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:16.425 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:41:16.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:16.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:41:16.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:16.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:41:16.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:41:16.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:16.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:16.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:16.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:41:16.428 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:16.428 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:41:16.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:16.429 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:41:16.429 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:41:16.429 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:16.429 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:16.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:16.430 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:41:16.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:16.430 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:41:16.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.432 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:41:16.432 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:41:16.432 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:41:16.433 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:16.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:16.437 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:41:16.915 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:41:16.956 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:41:16.957 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:41:16.959 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:41:16.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:41:17.387 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:41:17.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:17.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:17.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:17.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:17.861 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:41:18.333 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:41:18.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:18.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:18.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:18.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:18.805 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:41:19.281 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:41:19.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:19.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:19.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:19.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:19.754 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:41:20.228 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:41:20.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:20.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:20.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:20.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:20.700 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:41:21.171 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:41:21.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:21.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:21.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:21.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:21.645 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:41:22.117 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:41:22.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:22.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:22.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:22.475 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:22.475 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:22.475 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:41:22.475 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:22.475 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:22.475 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:22.475 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:22.475 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:22.475 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:22.475 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:22.475 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:22.475 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:27.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:27.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:27.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:27.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:27.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:27.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:27.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:27.506 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:27.506 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:27.507 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:27.507 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:41:27.514 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:41:27.514 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:41:27.514 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:27.514 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:27.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:27.515 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:41:27.515 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:27.515 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:41:27.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:27.520 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:41:27.521 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:41:27.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:27.521 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:27.522 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:27.522 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:41:27.523 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:27.523 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:41:27.523 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:27.526 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:41:27.526 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:41:27.526 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:27.526 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:27.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:27.526 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:41:27.527 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:27.527 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:41:27.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:27.532 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:41:27.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:41:27.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:41:27.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:41:27.532 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.533 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:41:27.533 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:41:27.533 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:41:27.534 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:27.538 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:41:28.016 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:41:28.061 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:41:28.063 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:41:28.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:41:28.065 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:41:28.488 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:41:28.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:28.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:28.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:28.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:28.964 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:41:29.436 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:41:29.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:29.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:29.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:29.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:29.911 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:41:30.382 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:41:30.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:30.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:30.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:30.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:30.857 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:41:31.329 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:41:31.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:31.543 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:31.797 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:41:32.266 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:41:32.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:32.559 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:32.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:32.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:32.740 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:41:33.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:33.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:33.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:33.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:33.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:33.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:33.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:33.079 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:41:33.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:33.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:33.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:33.079 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1198 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:33.079 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:33.079 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:33.079 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:33.079 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:33.079 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:33.079 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:38.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:38.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:38.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:38.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:38.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:38.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:38.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:38.092 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:38.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:38.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:38.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:41:38.098 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:41:38.098 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:41:38.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:38.099 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:38.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:38.100 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:41:38.100 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:38.100 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:41:38.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:38.102 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:41:38.102 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:41:38.103 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:38.103 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:38.103 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:38.103 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:41:38.104 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:38.104 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:41:38.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:38.105 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:41:38.105 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:41:38.105 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:38.105 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:38.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:38.106 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:41:38.106 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:38.106 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:41:38.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:38.109 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:41:38.109 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:41:38.109 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:41:38.110 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:41:38.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:38.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:38.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:38.111 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:38.111 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:38.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.119 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:43.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:43.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:43.139 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:43.139 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:43.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:43.144 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:43.146 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:43.146 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:43.147 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:41:43.147 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:41:43.154 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:41:43.155 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:41:43.156 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:43.156 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:43.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:43.157 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:41:43.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:41:43.158 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:41:43.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:43.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:41:43.161 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:41:43.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:43.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:43.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:43.163 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:41:43.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:41:43.163 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:41:43.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:43.165 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:41:43.165 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:41:43.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:43.166 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:41:43.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:43.166 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:41:43.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:41:43.166 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:41:43.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:41:43.171 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:41:43.171 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:41:43.171 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:41:43.176 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:41:43.654 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:41:43.701 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:41:43.703 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:41:43.705 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:41:43.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:41:43.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:41:43.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:41:43.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:41:44.126 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:41:44.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:44.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:44.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:44.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:44.601 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:41:44.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:41:44.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:41:44.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:41:44.711 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:41:44.711 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:41:45.074 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:41:45.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:45.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:45.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:45.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:45.545 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:41:46.018 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:41:46.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:46.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:46.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:46.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:46.490 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:41:46.962 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:41:47.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:47.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:47.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:47.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:47.433 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:41:47.905 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:41:48.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:48.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:48.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:48.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:48.378 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:41:48.850 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:41:49.322 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:41:49.793 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:41:50.264 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:41:50.734 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:41:51.206 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:41:51.676 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:41:52.147 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:41:52.617 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:41:53.088 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:41:53.559 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:41:54.030 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:41:54.503 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:41:54.976 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:41:55.448 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:41:55.922 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:41:56.394 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:41:56.866 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:41:57.340 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:41:57.812 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:41:58.284 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:41:58.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:41:58.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:41:58.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:41:58.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:41:58.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:41:58.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:41:58.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:41:58.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:41:58.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:41:58.533 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:41:58.533 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:41:58.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:41:58.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:41:58.533 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3320 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:58.533 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3320 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:58.533 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3320 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:58.533 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3320 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:58.533 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3320 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:41:58.533 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3320 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:03.536 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:42:03.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:42:03.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:03.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:03.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:03.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:03.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:03.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:03.543 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:03.544 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:03.544 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:42:03.544 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:42:03.545 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:42:03.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:03.545 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:03.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:03.545 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:42:03.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:03.545 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:42:03.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:03.546 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:42:03.546 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:42:03.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:03.546 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:03.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:03.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:42:03.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:03.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:42:03.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:03.547 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:42:03.547 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:42:03.547 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:03.547 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:03.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:03.547 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:42:03.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:03.548 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:42:03.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:03.549 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:42:03.549 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:42:03.549 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:42:03.549 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:42:03.550 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:42:03.550 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:42:03.550 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:03.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:03.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:03.555 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:42:04.030 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:42:04.070 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:04.072 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:04.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:04.074 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:42:04.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:04.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:04.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:42:04.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:04.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:04.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:04.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:42:04.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:42:04.122 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:04.126 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:04.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:04.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:04.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:04.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:04.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:04.501 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:42:04.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:04.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:04.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:04.553 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:04.974 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:42:05.444 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:42:05.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:05.555 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:05.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:05.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:05.917 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:42:06.390 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:42:06.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:06.556 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:06.556 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:06.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:06.862 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:42:07.333 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:42:07.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:07.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:07.558 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:07.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:07.804 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:42:08.278 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:42:08.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:08.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:08.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:08.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:08.750 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:42:09.223 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:42:09.694 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:42:10.167 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:42:10.639 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:42:11.111 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:42:11.582 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:42:12.055 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:42:12.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:12.145 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:12.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:12.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:12.152 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:12.152 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:12.152 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:12.152 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:12.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:12.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:12.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:12.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:12.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:42:12.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:42:12.153 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:42:12.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:12.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:12.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:12.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:12.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:12.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:12.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:17.160 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:42:17.160 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:42:17.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:17.160 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:17.160 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:17.160 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:17.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:17.169 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:17.169 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:17.170 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:17.170 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:42:17.172 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:42:17.173 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:42:17.173 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:17.173 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:17.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:17.174 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:42:17.174 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:17.174 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:42:17.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:17.175 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:42:17.175 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:42:17.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:17.175 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:17.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:17.175 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:42:17.176 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:17.176 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:42:17.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:17.178 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:42:17.178 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:42:17.178 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:17.178 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:17.178 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:17.178 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:42:17.178 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:17.178 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:42:17.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:42:17.181 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:42:17.181 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:17.186 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:42:17.663 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:42:17.708 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:17.710 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:17.712 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:42:17.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:17.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:17.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:17.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:42:17.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:17.740 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:17.740 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:17.740 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:42:17.740 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:42:17.756 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:17.759 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:17.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:17.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:17.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:17.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:17.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:18.136 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:42:18.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:18.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:18.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:18.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:18.607 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:42:19.080 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:42:19.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:19.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:19.553 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:42:20.025 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:42:20.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:20.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:20.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:20.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:20.496 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:42:20.970 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:42:21.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:21.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:21.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:21.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:21.442 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:42:21.914 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:42:22.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:22.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:22.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:22.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:22.385 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:42:22.859 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:42:23.331 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:42:23.804 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:42:24.277 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:42:24.750 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:42:25.222 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:42:25.693 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:42:25.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:25.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:25.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:25.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:25.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:25.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:25.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:25.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:25.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:25.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:42:25.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:42:25.786 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:42:25.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:25.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:25.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:25.786 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1858 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:25.786 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1858 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:25.786 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1858 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:25.786 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1858 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:25.786 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1858 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:25.786 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1858 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:30.787 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:42:30.787 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:42:30.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:30.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:30.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:30.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:30.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:30.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:30.791 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:30.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:30.791 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:42:30.791 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:42:30.792 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:42:30.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:30.792 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:30.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:30.792 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:42:30.792 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:30.792 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:42:30.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:30.793 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:42:30.794 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:42:30.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:30.794 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:30.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:30.794 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:42:30.794 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:30.794 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:42:30.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:30.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:42:30.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:42:30.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:30.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:30.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:30.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:42:30.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:30.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:42:30.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:42:30.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:42:30.799 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:42:30.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:30.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:30.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:42:31.281 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:42:31.330 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:31.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:31.334 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:31.336 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:42:31.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:31.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:31.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:42:31.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:31.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:31.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:31.367 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:42:31.367 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:42:31.375 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:31.379 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:31.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:31.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:31.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:31.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:31.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:31.752 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:42:31.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:31.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:31.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:31.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:32.225 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:42:32.697 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:42:32.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:32.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:32.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:32.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:33.168 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:42:33.641 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:42:33.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:33.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:33.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:33.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:34.114 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:42:34.587 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:42:34.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:34.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:34.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:34.806 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:35.060 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:42:35.533 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:42:35.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:35.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:35.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:35.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:36.005 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:42:36.478 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:42:36.951 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:42:37.424 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:42:37.895 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:42:38.366 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:42:38.836 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:42:39.307 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:42:39.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:39.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:39.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:39.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:39.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:39.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:39.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:42:39.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:39.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:39.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:39.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:42:39.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:42:39.444 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:39.448 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:39.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:39.456 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:39.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:39.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:39.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:39.778 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:42:40.251 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:42:40.724 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:42:41.196 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:42:41.667 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:42:42.138 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:42:42.611 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:42:43.084 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:42:43.557 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:42:44.028 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:42:44.501 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:42:44.974 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:42:45.446 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:42:45.919 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:42:46.392 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:42:46.864 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:42:47.335 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:42:47.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:47.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:47.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:47.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:47.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:47.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:47.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:47.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:47.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:47.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:42:47.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:42:47.480 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:42:47.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:47.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:47.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:47.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:47.481 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:47.481 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:47.481 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:47.481 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:47.481 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:47.481 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:42:52.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:42:52.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:42:52.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:52.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:52.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:52.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:52.489 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:42:52.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:52.490 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:52.491 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:42:52.491 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:42:52.494 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:42:52.494 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:42:52.495 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:52.495 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:52.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:42:52.496 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:42:52.496 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:42:52.496 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:42:52.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:52.497 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:42:52.497 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:42:52.498 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:52.498 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:52.498 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:42:52.498 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:42:52.498 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:42:52.498 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:42:52.498 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:52.500 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:42:52.500 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:42:52.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:52.500 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:42:52.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:42:52.500 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:42:52.501 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:42:52.501 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:42:52.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:42:52.503 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:42:52.504 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:42:52.504 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:42:52.504 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:42:52.509 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:42:52.987 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:42:53.027 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:53.028 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:53.029 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:42:53.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:53.046 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:42:53.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:42:53.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:42:53.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:53.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:53.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:53.055 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:42:53.055 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:42:53.079 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:42:53.083 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:42:53.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:42:53.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:42:53.096 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:42:53.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:53.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:42:53.459 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:42:53.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:53.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:53.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:53.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:53.930 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:42:54.401 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:42:54.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:54.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:54.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:54.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:54.872 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:42:55.342 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:42:55.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:55.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:55.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:55.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:55.816 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:42:56.289 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:42:56.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:56.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:56.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:56.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:56.761 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:42:57.235 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:42:57.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:42:57.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:42:57.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:42:57.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:42:57.707 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:42:58.178 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:42:58.652 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:42:59.124 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:42:59.596 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:43:00.067 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:43:00.538 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:43:01.009 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:43:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:01.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:01.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:01.102 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:01.120 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:01.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:01.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:43:01.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:01.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:01.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:01.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:43:01.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:43:01.144 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:01.148 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:01.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:01.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:01.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:01.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:01.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:01.481 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:43:01.954 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:43:02.427 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:43:02.898 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:43:03.368 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:43:03.839 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:43:04.312 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:43:04.785 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:43:05.258 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:43:05.729 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:43:06.202 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:43:06.674 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:43:07.147 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:43:07.620 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:43:08.093 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:43:08.565 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:43:09.036 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:43:09.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:09.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:09.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:09.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:09.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:09.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:09.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:09.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:09.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:43:09.179 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:43:09.179 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:43:09.180 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:43:09.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:43:09.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:43:09.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:43:09.180 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:43:09.180 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:43:09.181 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:43:09.181 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:43:09.181 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:43:09.181 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:43:09.181 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:43:14.185 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:43:14.186 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:43:14.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:43:14.186 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:43:14.186 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:43:14.186 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:43:14.201 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:43:14.201 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:43:14.202 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:14.202 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:43:14.202 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:43:14.205 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:43:14.205 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:43:14.205 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:43:14.205 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:14.206 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:43:14.206 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:43:14.206 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:43:14.206 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:43:14.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:14.208 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:43:14.208 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:43:14.208 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:43:14.208 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:14.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:43:14.208 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:43:14.208 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:43:14.208 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:43:14.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:14.210 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:43:14.210 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:43:14.210 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:43:14.210 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:14.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:43:14.211 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:43:14.211 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:43:14.211 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:43:14.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.213 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:43:14.214 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:43:14.214 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:43:14.214 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:14.218 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:43:14.696 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:43:14.741 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:14.743 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:14.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:14.745 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:43:14.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:14.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:14.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:43:14.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:14.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:14.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:14.772 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:43:14.772 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:43:14.788 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:14.791 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:14.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:14.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:14.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:14.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:14.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:15.166 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:43:15.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:15.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:15.217 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:15.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:15.639 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:43:16.111 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:43:16.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:16.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:16.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:16.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:16.582 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:43:17.054 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:43:17.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:17.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:17.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:17.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:17.525 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:43:17.998 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:43:18.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:18.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:18.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:18.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:18.470 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:43:18.944 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:43:19.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:19.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:19.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:19.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:19.416 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:43:19.889 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:43:20.362 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:43:20.834 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:43:21.306 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:43:21.777 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:43:22.251 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:43:22.724 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:43:22.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:22.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:22.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:22.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:22.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:22.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:22.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:43:22.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:22.823 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:22.823 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:22.823 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:43:22.823 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:43:22.862 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:22.865 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:22.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:22.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:22.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:22.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:22.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:23.195 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:43:23.667 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:43:24.140 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:43:24.612 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:43:25.085 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:43:25.558 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:43:26.031 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:43:26.503 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:43:26.974 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:43:27.447 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:43:27.919 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:43:28.392 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:43:28.865 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:43:29.338 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:43:29.810 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:43:30.284 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:43:30.756 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:43:30.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:30.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:30.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:30.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:30.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:30.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:30.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:30.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:30.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:43:30.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:43:30.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:43:30.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:43:30.893 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:43:30.893 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:43:30.893 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:43:35.899 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:43:35.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:43:35.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:43:35.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:43:35.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:43:35.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:43:35.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:43:35.907 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:43:35.907 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:35.907 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:43:35.907 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:43:35.910 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:43:35.910 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:43:35.911 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:43:35.911 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:35.911 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:43:35.912 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:43:35.912 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:43:35.912 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:43:35.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:35.913 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:43:35.914 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:43:35.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:43:35.914 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:35.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:43:35.914 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:43:35.914 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:43:35.915 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:43:35.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:35.916 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:43:35.916 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:43:35.916 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:43:35.917 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:43:35.917 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:43:35.917 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:43:35.917 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:43:35.917 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:43:35.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:43:35.920 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:43:35.920 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:43:35.920 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.920 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:43:35.925 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:43:36.402 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:43:36.443 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:36.444 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:36.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:36.444 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:43:36.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:36.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:36.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:43:36.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:36.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:36.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:36.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:43:36.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:43:36.494 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:36.498 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:36.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:36.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:36.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:36.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:36.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:36.873 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:43:36.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:36.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:36.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:36.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:37.346 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:43:37.818 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:43:37.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:37.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:37.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:37.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:38.289 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:43:38.763 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:43:38.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:38.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:38.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:38.926 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:39.236 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:43:39.709 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:43:39.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:39.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:39.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:39.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:40.182 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:43:40.654 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:43:40.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:43:40.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:43:40.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:43:40.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:43:41.127 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:43:41.600 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:43:42.072 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:43:42.543 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:43:43.017 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:43:43.489 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:43:43.962 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:43:44.433 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:43:44.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:44.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:44.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:44.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:44.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:44.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:44.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:43:44.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:44.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:44.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:44.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:43:44.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:43:44.569 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:44.573 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:44.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:44.584 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:44.584 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:44.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:44.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:44.906 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:43:45.379 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:43:45.851 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:43:46.325 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:43:46.797 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:43:47.270 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:43:47.743 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:43:48.216 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:43:48.688 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:43:49.161 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:43:49.634 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:43:50.107 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:43:50.580 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:43:51.053 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:43:51.525 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:43:51.999 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:43:52.471 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:43:52.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:52.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:52.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:52.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:52.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:43:52.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:43:52.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:43:52.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:52.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:52.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:52.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:43:52.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:43:52.656 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:43:52.659 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:43:52.668 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:43:52.675 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:43:52.675 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:43:52.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:52.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:43:52.944 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:43:53.415 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:43:53.888 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:43:54.360 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:43:54.833 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:43:55.306 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:43:55.779 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:43:56.251 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:43:56.725 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:43:57.197 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:43:57.670 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:43:58.141 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:43:58.614 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:43:59.087 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:43:59.559 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:44:00.033 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:44:00.506 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:44:00.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:00.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:00.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:00.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:00.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:00.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:00.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:44:00.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:00.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:00.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:00.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:44:00.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:44:00.740 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:00.744 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:00.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:00.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:00.757 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:00.757 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:00.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:00.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:00.978 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:44:01.449 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:44:01.922 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:44:02.394 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:44:02.867 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:44:03.340 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:44:03.813 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:44:04.285 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:44:04.759 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:44:05.231 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:44:05.704 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:44:06.177 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:44:06.650 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:44:07.122 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:44:07.596 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:44:08.068 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:44:08.541 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:44:08.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:08.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:08.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:08.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:08.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:08.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:08.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:44:08.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:44:08.778 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:44:08.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:44:08.778 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:44:08.778 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:44:08.778 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:44:08.778 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7091 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:08.778 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7091 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:08.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7091 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:08.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7091 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:08.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7091 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:08.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7091 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:13.779 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:44:13.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:44:13.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:44:13.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:44:13.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:44:13.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:44:13.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:44:13.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:44:13.791 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:13.791 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:44:13.791 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:44:13.796 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:44:13.796 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:44:13.796 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:44:13.796 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:13.797 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:44:13.797 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:44:13.797 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:44:13.797 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:44:13.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:13.799 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:44:13.799 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:44:13.799 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:44:13.799 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:13.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:44:13.800 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:44:13.800 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:44:13.800 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:44:13.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:13.803 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:44:13.803 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:44:13.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:44:13.803 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:13.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:44:13.803 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:44:13.803 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:44:13.803 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:44:13.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:13.806 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:44:13.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:44:13.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:44:13.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:44:13.806 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:44:13.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:44:13.807 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:44:13.807 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:44:13.807 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:13.812 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:44:14.289 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:44:14.333 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:14.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:14.336 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:14.337 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:44:14.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:14.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:14.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:44:14.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:14.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:14.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:14.365 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:44:14.365 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:44:14.381 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:14.384 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:14.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:14.396 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:14.396 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:14.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:14.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:14.760 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:44:14.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:14.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:14.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:14.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:15.232 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:44:15.703 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:44:15.812 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:15.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:15.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:15.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:16.174 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:44:16.647 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:44:16.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:16.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:16.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:16.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:17.120 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:44:17.592 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:44:17.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:17.814 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:17.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:17.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:18.063 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:44:18.533 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:44:18.815 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:18.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:18.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:18.816 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:19.007 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:44:19.479 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:44:19.951 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:44:20.425 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:44:20.897 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:44:21.370 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:44:21.840 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:44:22.311 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:44:22.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:22.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:22.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:22.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:22.420 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:22.420 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:22.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:44:22.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:22.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:22.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:22.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:44:22.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:44:22.447 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:22.451 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:22.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:22.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:22.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:22.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:22.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:22.781 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:44:23.253 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:44:23.726 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:44:24.198 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:44:24.671 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:44:25.141 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:44:25.614 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:44:26.087 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:44:26.559 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:44:27.030 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:44:27.504 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:44:27.976 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:44:28.449 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:44:28.922 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:44:29.395 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:44:29.866 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:44:30.339 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:44:30.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:30.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:30.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:30.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:30.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:30.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:30.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:30.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:30.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:44:30.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:44:30.482 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:44:30.482 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:44:30.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:44:30.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:44:30.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:44:30.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:30.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:30.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:30.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:30.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:30.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3603 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:44:35.485 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:44:35.485 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:44:35.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:44:35.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:44:35.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:44:35.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:44:35.493 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:44:35.494 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:44:35.494 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:35.494 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:44:35.494 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:44:35.497 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:44:35.497 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:44:35.497 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:44:35.497 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:35.497 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:44:35.497 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:44:35.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:44:35.498 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:44:35.498 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:35.500 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:44:35.500 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:44:35.500 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:44:35.500 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:35.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:44:35.501 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:44:35.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:44:35.501 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:44:35.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:35.503 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:44:35.503 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:44:35.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:44:35.504 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:44:35.504 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:44:35.504 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:44:35.504 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:44:35.504 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:44:35.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.508 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:44:35.509 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:44:35.509 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:44:35.509 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:44:35.513 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:44:35.991 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:44:36.039 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:36.042 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:36.044 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:44:36.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:36.074 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:36.074 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:36.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:44:36.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:36.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:36.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:36.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:44:36.083 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:44:36.129 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:36.133 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:36.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:36.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:36.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:36.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:36.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:36.463 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:44:36.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:36.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:36.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:36.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:36.937 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:44:37.409 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:44:37.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:37.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:37.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:37.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:37.881 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:44:38.355 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:44:38.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:38.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:38.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:38.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:38.827 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:44:39.299 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:44:39.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:39.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:39.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:39.517 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:39.772 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:44:40.245 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:44:40.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:44:40.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:44:40.518 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:44:40.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:44:40.717 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:44:41.188 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:44:41.662 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:44:42.134 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:44:42.606 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:44:43.080 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:44:43.552 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:44:44.024 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:44:44.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:44.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:44.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:44.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:44.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:44.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:44.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:44:44.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:44.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:44.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:44.174 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:44:44.174 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:44:44.207 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:44.211 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:44.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:44.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:44.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:44.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:44.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:44.495 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:44:44.966 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:44:45.437 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:44:45.908 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:44:46.381 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:44:46.854 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:44:47.326 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:44:47.797 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:44:48.270 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:44:48.742 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:44:49.215 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:44:49.688 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:44:50.161 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:44:50.633 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:44:51.104 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:44:51.577 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:44:52.050 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:44:52.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:52.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:52.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:52.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:52.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:44:52.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:44:52.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:44:52.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:52.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:52.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:52.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:44:52.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:44:52.285 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:44:52.288 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:44:52.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:44:52.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:44:52.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:44:52.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:52.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:44:52.522 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:44:52.993 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:44:53.466 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:44:53.939 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:44:54.411 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:44:54.882 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:44:55.355 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:44:55.827 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:44:56.299 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:44:56.770 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:44:57.241 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:44:57.714 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:44:58.187 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:44:58.659 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:44:59.133 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:44:59.605 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:45:00.077 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:45:00.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:00.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:00.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:00.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:00.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:00.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:00.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:45:00.317 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:00.317 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:00.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:00.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:45:00.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:45:00.357 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:00.359 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:00.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:00.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:00.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:00.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:00.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:00.548 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:45:01.019 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:45:01.492 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:45:01.964 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:45:02.436 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:45:02.910 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:45:03.382 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:45:03.854 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:45:04.325 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:45:04.796 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:45:05.269 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:45:05.742 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:45:06.214 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:45:06.685 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:45:07.159 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:45:07.631 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:45:08.103 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:45:08.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:08.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:08.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:08.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:08.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:45:08.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:45:08.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:45:08.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:45:08.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:45:08.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:45:08.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:45:08.389 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:45:08.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:45:08.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:45:08.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:45:08.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7102 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:45:08.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7102 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:45:08.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7102 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:45:08.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7102 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:45:08.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7102 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:45:08.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7102 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:45:13.393 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:45:13.393 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:45:13.393 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:45:13.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:45:13.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:45:13.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:45:13.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:45:13.399 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:45:13.399 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:45:13.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:45:13.400 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:45:13.402 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:45:13.402 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:45:13.403 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:45:13.403 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:45:13.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:45:13.403 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:45:13.404 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:45:13.404 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:45:13.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:45:13.405 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:45:13.405 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:45:13.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:45:13.405 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:45:13.405 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:45:13.405 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:45:13.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:45:13.405 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:45:13.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:45:13.407 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:45:13.407 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:45:13.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:45:13.408 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:45:13.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:45:13.408 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:45:13.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:45:13.408 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:45:13.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:45:13.410 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:45:13.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:45:13.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:45:13.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:45:13.410 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:45:13.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:45:13.411 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:45:13.411 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:45:13.411 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.411 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:45:13.416 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:45:13.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:45:13.937 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:13.939 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:13.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:13.943 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:45:13.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:13.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:13.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:45:13.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:13.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:13.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:13.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:45:13.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:45:13.986 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:13.990 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:13.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:14.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:14.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:14.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:14.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:14.365 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:45:14.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:45:14.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:45:14.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:45:14.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:45:14.837 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:45:15.309 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:45:15.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:45:15.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:45:15.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:45:15.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:45:15.780 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:45:16.251 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:45:16.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:45:16.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:45:16.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:45:16.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:45:16.725 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:45:17.197 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:45:17.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:45:17.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:45:17.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:45:17.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:45:17.669 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:45:18.140 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:45:18.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:45:18.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:45:18.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:45:18.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:45:18.613 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:45:19.086 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:45:19.558 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:45:20.029 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:45:20.500 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:45:20.972 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:45:21.441 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:45:21.914 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:45:22.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:22.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:22.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:22.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:22.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:22.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:22.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:45:22.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:22.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:22.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:22.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:45:22.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:45:22.047 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:22.051 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:22.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:22.062 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:22.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:22.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:22.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:22.387 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:45:22.859 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:45:23.330 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:45:23.803 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:45:24.276 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:45:24.748 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:45:25.219 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:45:25.684 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:45:26.155 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:45:26.626 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:45:27.100 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:45:27.572 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:45:28.044 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:45:28.518 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:45:28.990 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:45:29.462 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:45:29.933 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:45:30.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:30.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:30.068 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:30.068 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:30.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:30.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:30.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:45:30.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:30.077 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:30.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:30.077 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:45:30.077 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:45:30.116 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:30.120 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:30.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:30.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:30.130 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:30.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:30.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:30.406 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:45:30.879 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:45:31.351 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:45:31.822 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:45:32.295 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:45:32.768 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:45:33.240 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:45:33.711 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:45:34.184 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:45:34.656 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:45:35.128 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:45:35.599 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:45:36.072 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:45:36.545 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:45:37.016 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:45:37.487 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:45:37.958 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:45:38.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:38.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:38.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:38.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:38.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:38.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:38.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:45:38.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:38.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:38.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:38.157 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:45:38.157 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:45:38.192 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:38.197 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:38.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:38.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:38.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:38.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:38.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:38.432 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:45:38.904 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:45:39.376 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:45:39.847 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:45:40.321 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:45:40.793 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:45:41.265 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:45:41.736 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:45:42.209 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:45:42.682 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:45:43.154 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:45:43.625 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:45:44.098 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:45:44.571 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:45:45.043 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:45:45.514 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:45:45.987 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:45:46.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:46.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:46.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:46.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:46.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:46.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:46.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:45:46.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:46.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:46.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:46.235 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:45:46.235 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:45:46.264 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:46.269 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:46.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:46.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:46.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:46.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:46.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:46.459 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:45:46.932 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:45:47.402 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:45:47.876 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 01:45:48.348 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 01:45:48.820 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 01:45:49.292 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 01:45:49.765 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 01:45:50.237 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 01:45:50.709 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 01:45:51.181 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 01:45:51.654 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 01:45:52.126 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 01:45:52.598 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 01:45:53.069 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 01:45:53.540 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 01:45:54.013 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 01:45:54.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:54.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:54.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:54.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:54.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:45:54.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:45:54.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:45:54.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:54.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:54.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:54.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:45:54.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:45:54.337 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:45:54.341 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:45:54.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:45:54.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:45:54.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:45:54.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:54.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:45:54.486 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 01:45:54.958 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 01:45:55.431 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 01:45:55.913 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 01:45:56.385 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 01:45:56.856 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 01:45:57.327 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 01:45:57.801 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 01:45:58.273 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 01:45:58.745 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 01:45:59.219 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 01:45:59.692 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 01:46:00.164 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 01:46:00.635 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 01:46:01.108 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 01:46:01.581 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 01:46:02.052 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 01:46:02.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:02.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:02.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:02.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:02.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:02.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:02.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:46:02.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:02.378 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:02.378 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:02.378 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:46:02.378 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:46:02.425 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:46:02.429 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:46:02.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:02.440 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:02.440 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:02.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:02.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:02.523 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 01:46:02.995 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 01:46:03.465 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 01:46:03.936 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 01:46:04.407 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 01:46:04.878 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 01:46:05.351 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 01:46:05.824 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 01:46:06.295 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 01:46:06.767 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 01:46:07.237 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 01:46:07.708 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 01:46:08.179 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 01:46:08.650 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 01:46:09.120 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 01:46:09.591 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 01:46:10.065 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 01:46:10.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:10.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:10.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:10.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:10.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:10.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:10.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:46:10.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:10.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:10.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:10.482 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:46:10.482 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:46:10.531 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:46:10.533 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:46:10.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:10.537 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 01:46:10.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:10.542 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:10.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:10.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:11.008 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 01:46:11.480 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 01:46:11.950 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 01:46:12.424 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 01:46:12.896 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 01:46:13.368 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 01:46:13.839 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 01:46:14.313 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 01:46:14.785 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 01:46:15.257 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 01:46:15.731 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 01:46:16.203 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 01:46:16.675 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 01:46:17.146 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 01:46:17.619 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 01:46:18.092 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 01:46:18.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:18.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:18.549 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:18.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:18.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:18.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:18.564 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 01:46:18.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:18.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:46:18.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:46:18.565 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:46:18.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:18.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:18.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14078 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14078 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14078 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14078 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14078 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14078 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:18.565 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=14079 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:23.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:46:23.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:46:23.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:23.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:23.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:23.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:23.575 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:23.575 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:46:23.576 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:23.576 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:46:23.576 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:46:23.578 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:46:23.578 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:46:23.579 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:46:23.579 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:23.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:23.579 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:46:23.579 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:46:23.579 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:46:23.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:23.581 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:46:23.581 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:46:23.581 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:46:23.581 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:23.581 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:23.581 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:46:23.582 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:46:23.582 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:46:23.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:23.584 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:46:23.584 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:46:23.584 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:46:23.584 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:23.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:23.584 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:46:23.584 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:46:23.584 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:46:23.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:23.587 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:46:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:46:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:46:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:46:23.587 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:46:23.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:46:23.588 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:46:23.588 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:46:23.588 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.588 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:23.593 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:46:24.070 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:46:24.117 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:46:24.120 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:46:24.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:24.122 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:46:24.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:24.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:24.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:46:24.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:24.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:24.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:24.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:46:24.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:46:24.161 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:46:24.163 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:46:24.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:24.168 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:24.168 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:24.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:24.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:24.543 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:46:24.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:24.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:24.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:24.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:25.014 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:46:25.485 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:46:25.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:25.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:25.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:25.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:25.955 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:46:26.429 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:46:26.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:26.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:26.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:26.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:26.901 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:46:27.373 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:46:27.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:27.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:27.844 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:46:28.317 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:46:28.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:28.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:28.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:28.599 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:28.790 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:46:29.262 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:46:29.736 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:46:30.208 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:46:30.681 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:46:31.151 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:46:31.622 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:46:32.093 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:46:32.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:32.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:32.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:32.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:32.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:32.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:32.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:46:32.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:32.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:32.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:32.192 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:46:32.192 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:46:32.229 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:46:32.233 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:46:32.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:32.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:32.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:32.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:32.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:32.564 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:46:33.038 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:46:33.510 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:46:33.981 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:46:34.454 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:46:34.927 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:46:35.399 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:46:35.872 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:46:36.345 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:46:36.817 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:46:37.290 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:46:37.763 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:46:38.235 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:46:38.709 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:46:39.181 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:46:39.653 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:46:40.124 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:46:40.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:40.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:40.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:40.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:40.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:40.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:40.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:40.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:40.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:40.261 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:46:40.261 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:46:40.261 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:46:40.261 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:40.261 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:40.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:40.262 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3602 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:40.262 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3602 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:40.262 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3602 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:40.262 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3602 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:40.262 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3602 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:40.262 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3602 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:45.268 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:46:45.268 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:46:45.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:45.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:45.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:45.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:45.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:45.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:46:45.276 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:45.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:46:45.276 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:46:45.278 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:46:45.278 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:46:45.279 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:46:45.279 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:45.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:45.279 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:46:45.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:46:45.280 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:46:45.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:45.281 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:46:45.281 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:46:45.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:46:45.281 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:45.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:45.281 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:46:45.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:46:45.281 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:46:45.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:45.283 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:46:45.283 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:46:45.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:46:45.283 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:45.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:45.283 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:46:45.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:46:45.283 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:46:45.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:45.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:46:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:46:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:46:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:46:45.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:46:45.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:46:45.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:46:45.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:46:45.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:45.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:45.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:45.291 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:46:45.768 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:46:45.808 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:46:45.809 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:46:45.812 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:46:45.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:45.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:45.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:45.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:46:45.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:45.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:45.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:45.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:46:45.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:46:45.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:45.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:45.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:45.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:45.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:46.240 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:46:46.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:46.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:46.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:46.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:46.712 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:46:47.182 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:46:47.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:47.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:47.290 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:47.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:47.656 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:46:48.128 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:46:48.291 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:48.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:48.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:48.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:48.601 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:46:49.072 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:46:49.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:49.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:49.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:49.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:49.542 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:46:50.013 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:46:50.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:50.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:50.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:50.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:50.484 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:46:50.955 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:46:51.428 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:46:51.901 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:46:52.373 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:46:52.847 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:46:53.319 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:46:53.791 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:46:53.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:53.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:53.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:53.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:53.898 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:53.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:53.899 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:53.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:53.901 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:53.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:53.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:53.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:53.902 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:46:53.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:46:53.902 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:46:53.902 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:53.902 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:53.902 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:53.902 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:53.902 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:53.902 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:46:58.906 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:46:58.906 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:46:58.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:58.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:58.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:58.906 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:58.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:46:58.916 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:46:58.916 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:58.916 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:46:58.916 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:46:58.920 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:46:58.920 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:46:58.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:46:58.920 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:58.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:46:58.920 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:46:58.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:46:58.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:46:58.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:58.925 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:46:58.925 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:46:58.925 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:46:58.925 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:58.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:46:58.925 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:46:58.926 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:46:58.926 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:46:58.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:58.929 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:46:58.929 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:46:58.929 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:46:58.929 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:46:58.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:46:58.930 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:46:58.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:46:58.930 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:46:58.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:46:58.935 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:46:58.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:46:58.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:46:58.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:46:58.935 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:46:58.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.936 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:46:58.936 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:46:58.936 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:46:58.936 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:46:58.941 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:46:59.419 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:46:59.465 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:46:59.467 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:46:59.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:59.469 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:46:59.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:46:59.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:46:59.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:46:59.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:59.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:59.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:59.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:46:59.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:46:59.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:46:59.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:46:59.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:46:59.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:59.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:46:59.891 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:46:59.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:46:59.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:46:59.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:46:59.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:00.363 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:47:00.836 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:47:00.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:00.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:00.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:00.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:01.308 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:47:01.781 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:47:01.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:01.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:01.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:01.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:02.252 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:47:02.722 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:47:02.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:02.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:02.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:02.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:03.193 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:47:03.667 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:47:03.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:03.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:03.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:03.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:04.139 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:47:04.611 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:47:05.085 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:47:05.557 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:47:06.029 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:47:06.502 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:47:06.974 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:47:07.447 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:47:07.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:47:07.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:47:07.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:47:07.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:07.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:07.536 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:12.543 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:12.543 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:12.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:12.543 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:12.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:12.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:12.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:12.548 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:12.548 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:12.549 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:12.549 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:47:12.551 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:47:12.551 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:47:12.551 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:12.552 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:12.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:12.552 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:47:12.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:12.552 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:47:12.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:12.554 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:47:12.554 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:47:12.554 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:12.554 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:12.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:12.554 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:47:12.554 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:12.554 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:47:12.554 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:12.556 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:47:12.556 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:47:12.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:12.556 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:12.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:12.556 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:47:12.556 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:12.556 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:47:12.556 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:47:12.559 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:47:12.559 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:12.564 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:47:13.042 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:47:13.084 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:47:13.086 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:47:13.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:47:13.088 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:47:13.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:47:13.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:47:13.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:47:13.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:47:13.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:47:13.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:47:13.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:47:13.119 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:47:13.513 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:47:13.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:13.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:13.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:13.582 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:13.985 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:47:14.458 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:47:14.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:14.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:14.582 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:14.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:14.931 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:47:15.404 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:47:15.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:15.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:15.583 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:15.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:15.875 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:47:16.347 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:47:16.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:16.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:16.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:16.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:16.820 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:47:17.292 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:47:17.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:17.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:17.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:17.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:17.764 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:47:18.235 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:47:18.706 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:47:19.180 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:47:19.652 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:47:19.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:47:19.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:47:19.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:19.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:19.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:19.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:19.789 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:19.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:19.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:19.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:19.789 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:19.789 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:19.789 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:47:24.796 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:24.796 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:24.796 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:24.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:24.796 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:24.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:24.803 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:24.805 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:24.805 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:24.805 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:24.805 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:47:24.811 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:47:24.811 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:47:24.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:24.811 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:24.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:24.812 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:47:24.812 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:24.812 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:47:24.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:24.816 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:47:24.816 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:47:24.816 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:24.817 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:24.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:24.817 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:47:24.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:24.817 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:47:24.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:24.821 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:47:24.821 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:47:24.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:24.821 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:24.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:24.821 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:47:24.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:24.822 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:47:24.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:47:24.827 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:47:24.828 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:47:24.828 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:47:24.828 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:24.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:24.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:24.833 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:47:25.309 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:47:25.362 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:47:25.365 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:47:25.365 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:47:25.367 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:47:25.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:47:25.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:47:25.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:47:25.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:47:25.397 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:47:25.397 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:47:25.397 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:47:25.397 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:47:25.779 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:47:25.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:25.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:25.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:25.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:26.252 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:47:26.724 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:47:26.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:26.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:26.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:26.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:27.195 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:47:27.668 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:47:27.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:27.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:27.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:27.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:28.141 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:47:28.612 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:47:28.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:28.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:28.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:28.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:29.084 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:47:29.557 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:47:29.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:29.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:29.836 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:29.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:30.029 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:47:30.052 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:30.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:30.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:30.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:30.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:30.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:30.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:30.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:30.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:30.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:30.053 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:47:30.053 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:47:30.053 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:47:30.053 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:47:30.053 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:47:30.053 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:47:30.507 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:47:30.987 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:47:31.465 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:47:31.945 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:47:32.423 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:47:32.904 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:47:33.384 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:47:33.862 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:47:34.341 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:47:34.821 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:47:35.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:47:35.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:47:35.058 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:47:35.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:35.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:35.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:35.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:35.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:35.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:35.064 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:35.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:35.064 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:35.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:35.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:47:35.066 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:47:35.066 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:47:35.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:35.066 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:35.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:35.066 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:47:35.066 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:35.066 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:47:35.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:35.068 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:47:35.068 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:47:35.068 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:35.068 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:35.068 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:35.068 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:47:35.069 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:35.069 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:47:35.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:35.070 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:47:35.070 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:47:35.071 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:35.071 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:35.071 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:35.071 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:47:35.071 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:35.071 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:47:35.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:35.074 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:35.075 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:35.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:35.075 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:35.075 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:47:35.076 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:47:35.076 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:47:35.076 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:35.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:35.076 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:35.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.083 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:47:40.083 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:47:40.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:40.084 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:40.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:40.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:40.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:40.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:40.093 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:40.093 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:47:40.093 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:47:40.098 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:47:40.098 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:47:40.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:40.099 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:40.099 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:47:40.099 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:47:40.099 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:47:40.099 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:47:40.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:40.103 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:47:40.103 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:47:40.104 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:40.104 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:40.104 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:47:40.104 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:47:40.104 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:47:40.104 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:47:40.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:40.108 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:47:40.108 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:47:40.108 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:40.108 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:47:40.108 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:47:40.108 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:47:40.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:47:40.109 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:47:40.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:47:40.113 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:47:40.114 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:47:40.114 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:47:40.114 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:47:40.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:47:40.119 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:47:40.596 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:47:40.643 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:47:40.644 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:47:40.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:47:40.647 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:47:40.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:47:40.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:47:40.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:47:40.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:47:40.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:47:40.680 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:47:40.680 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:47:40.680 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:47:41.068 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:47:41.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:41.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:41.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:41.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:41.539 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:47:42.010 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:47:42.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:42.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:42.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:42.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:42.481 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:47:42.955 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:47:43.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:43.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:43.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:43.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:43.427 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:47:43.899 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:47:44.122 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:44.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:44.123 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:44.123 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:44.370 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:47:44.843 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:47:45.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:45.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:47:45.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:47:45.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:47:45.316 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:47:45.788 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:47:46.259 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:47:46.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:46.732 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:47:47.205 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:47:47.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:47.677 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:47:48.148 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:47:48.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:48.621 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:47:49.093 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:47:49.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:49.565 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:47:50.036 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:47:50.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:50.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:50.511 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:47:50.983 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:47:51.458 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:47:51.930 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:47:52.405 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:47:52.877 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:47:53.353 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:47:53.825 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:47:54.300 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:47:54.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:47:54.772 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:47:55.243 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:47:55.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:55.717 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:47:56.189 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:47:56.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:56.661 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:47:57.132 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:47:57.346 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:57.606 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:47:58.078 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:47:58.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:58.550 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:47:59.021 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:47:59.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:47:59.492 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:47:59.965 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:48:00.438 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:48:00.909 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:48:01.380 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:48:01.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:01.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:01.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:01.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:01.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:01.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:01.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:01.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:01.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:01.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:01.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:48:01.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:48:01.513 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:48:06.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:48:06.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:48:06.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:06.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:06.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:06.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:06.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:06.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:48:06.524 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:06.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:48:06.524 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:48:06.526 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:48:06.526 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:48:06.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:48:06.527 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:06.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:06.527 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:48:06.528 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:48:06.528 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:48:06.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:06.529 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:48:06.529 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:48:06.529 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:48:06.529 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:06.529 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:06.529 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:48:06.529 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:48:06.529 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:48:06.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:06.531 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:48:06.531 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:48:06.531 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:48:06.531 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:06.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:06.531 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:48:06.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:48:06.532 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:48:06.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.534 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:48:06.534 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:48:06.534 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:48:06.535 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:06.539 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:48:07.017 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:48:07.063 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:48:07.065 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:48:07.066 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:48:07.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:07.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:07.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:07.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:48:07.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:07.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:07.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:07.090 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:48:07.090 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:48:07.109 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:48:07.113 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:48:07.119 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 01:48:07.123 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:07.123 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:07.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:07.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:07.489 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:48:07.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:07.537 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:07.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:07.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:07.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 01:48:07.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:07.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:07.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:07.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:07.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:07.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:07.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:07.936 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:07.937 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:07.937 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:07.937 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:07.937 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:48:07.937 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:48:07.937 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:48:07.937 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:07.937 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:07.937 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:07.937 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:07.937 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:07.937 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:12.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:48:12.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:48:12.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:12.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:12.942 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:12.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:12.951 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:12.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:48:12.952 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:12.953 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:48:12.953 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:48:12.957 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:48:12.958 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:48:12.958 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:48:12.958 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:12.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:12.959 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:48:12.959 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:48:12.959 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:48:12.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:12.961 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:48:12.961 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:48:12.961 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:48:12.961 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:12.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:12.962 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:48:12.962 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:48:12.962 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:48:12.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:12.964 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:48:12.964 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:48:12.964 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:48:12.964 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:12.964 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:12.965 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:48:12.965 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:48:12.965 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:48:12.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:48:12.968 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:48:12.968 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:48:12.968 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.968 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.969 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:12.973 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:48:13.451 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:48:13.495 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:48:13.497 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:48:13.498 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:48:13.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:13.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:13.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:13.523 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:48:13.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:13.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:13.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:13.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:48:13.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:48:13.543 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:48:13.547 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:48:13.552 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 01:48:13.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:13.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:13.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:13.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:13.923 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:48:13.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:13.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:13.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:13.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:14.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 01:48:14.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:14.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:14.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:14.369 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:14.369 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:14.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:14.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:14.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:14.373 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:14.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:14.373 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:14.373 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:48:14.374 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:48:14.374 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:48:14.374 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:14.374 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:14.374 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:14.374 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:14.374 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:14.375 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=303 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:48:19.374 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:48:19.374 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:48:19.374 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:19.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:19.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:19.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:19.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:48:19.385 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:48:19.385 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:19.386 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:48:19.386 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:48:19.391 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:48:19.391 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:48:19.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:48:19.391 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:19.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:48:19.392 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:48:19.392 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:48:19.392 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:48:19.392 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:19.396 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:48:19.396 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:48:19.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:48:19.397 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:19.397 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:48:19.397 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:48:19.397 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:48:19.397 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:48:19.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:19.401 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:48:19.401 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:48:19.401 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:48:19.401 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:48:19.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:48:19.402 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:48:19.402 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:48:19.402 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:48:19.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:19.407 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:48:19.407 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:48:19.407 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:48:19.407 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:48:19.407 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.408 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:48:19.408 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:48:19.408 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:48:19.408 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:48:19.413 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:48:19.891 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:48:19.941 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:48:19.942 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:48:19.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:19.944 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:48:19.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:19.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:19.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:48:19.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:19.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:19.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:19.972 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:48:19.972 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:48:19.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:19.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:19.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:19.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:19.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:20.364 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:48:20.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:20.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:20.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:20.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:20.835 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:48:21.308 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:48:21.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:21.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:21.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:21.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:21.781 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:48:22.253 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:48:22.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:22.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:22.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:22.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:22.727 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:48:23.199 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:48:23.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:23.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:23.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:23.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:23.672 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:48:24.146 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:48:24.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:48:24.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:48:24.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:48:24.420 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:48:24.618 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:48:25.090 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:48:25.564 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:48:26.036 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:48:26.509 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:48:26.980 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:48:27.453 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:48:27.926 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:48:28.398 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:48:28.872 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:48:29.344 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:48:29.817 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:48:30.290 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:48:30.763 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:48:31.235 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:48:31.709 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:48:32.181 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:48:32.654 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:48:33.127 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:48:33.600 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:48:34.072 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:48:34.543 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:48:35.017 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:48:35.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:35.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:35.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:35.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:35.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:35.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:35.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:48:35.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:35.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:35.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:35.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:48:35.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:48:35.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:35.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:35.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:35.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:35.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:35.489 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:48:35.962 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:48:36.433 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:48:36.906 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:48:37.379 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:48:37.851 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:48:38.322 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:48:38.793 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:48:39.266 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:48:39.739 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:48:40.211 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:48:40.685 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:48:41.157 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:48:41.630 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:48:42.103 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:48:42.576 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:48:43.048 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:48:43.519 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:48:43.990 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:48:44.463 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:48:44.936 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:48:45.409 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:48:45.882 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:48:46.354 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:48:46.827 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:48:47.298 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:48:47.771 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:48:48.244 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:48:48.716 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:48:49.187 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:48:49.658 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:48:50.131 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:48:50.604 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:48:50.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:50.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:50.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:50.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:50.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:48:50.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:48:50.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:48:50.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:50.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:50.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:50.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:48:50.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:48:50.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:48:50.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:48:50.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:48:50.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:50.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:48:51.076 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:48:51.550 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:48:52.022 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:48:52.495 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:48:52.968 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:48:53.441 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:48:53.913 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 01:48:54.384 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 01:48:54.858 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 01:48:55.330 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 01:48:55.803 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 01:48:56.276 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 01:48:56.749 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 01:48:57.221 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 01:48:57.695 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 01:48:58.167 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 01:48:58.640 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 01:48:59.111 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 01:48:59.581 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 01:49:00.055 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 01:49:00.528 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 01:49:01.000 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 01:49:01.473 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 01:49:01.946 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 01:49:02.419 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 01:49:02.892 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 01:49:03.364 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 01:49:03.837 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 01:49:04.310 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 01:49:04.783 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 01:49:05.255 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 01:49:05.726 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 01:49:06.199 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 01:49:06.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:06.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:06.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:49:06.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:49:06.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:49:06.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:49:06.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:49:06.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:06.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:49:06.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:49:06.281 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:49:06.281 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:49:06.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:06.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:06.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:49:06.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:49:06.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:06.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:06.671 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 01:49:07.144 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 01:49:07.617 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 01:49:08.090 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 01:49:08.562 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 01:49:09.036 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 01:49:09.509 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 01:49:09.982 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 01:49:10.455 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 01:49:10.928 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 01:49:11.401 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 01:49:11.874 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 01:49:12.346 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 01:49:12.817 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 01:49:13.291 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 01:49:13.763 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 01:49:14.234 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 01:49:14.705 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 01:49:15.179 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 01:49:15.651 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 01:49:16.124 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 01:49:16.597 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 01:49:17.070 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 01:49:17.542 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 01:49:18.015 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 01:49:18.488 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 01:49:18.961 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 01:49:19.434 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 01:49:19.907 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 01:49:20.379 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 01:49:20.850 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 01:49:21.323 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 01:49:21.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:21.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:21.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:49:21.745 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:49:21.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:21.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:21.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:21.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:21.758 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:21.758 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:49:21.758 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:49:21.758 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:49:21.758 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:21.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:21.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:21.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:49:21.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:49:21.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:49:21.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:49:21.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:49:21.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:49:21.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:49:26.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:49:26.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:49:26.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:26.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:26.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:26.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:26.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:26.766 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:49:26.766 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:26.766 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:49:26.766 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:49:26.767 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:49:26.767 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:49:26.767 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:49:26.768 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:26.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:26.768 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:49:26.768 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:49:26.768 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:49:26.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:26.768 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:49:26.769 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:49:26.769 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:49:26.769 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:26.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:26.769 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:49:26.769 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:49:26.769 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:49:26.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:26.770 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:49:26.770 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:49:26.770 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:49:26.770 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:26.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:26.770 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:49:26.770 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:49:26.770 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:49:26.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:49:26.772 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:49:26.772 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:49:26.772 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.772 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:26.773 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:26.774 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:26.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:26.774 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:26.774 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:26.774 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:49:26.774 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:49:26.774 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:49:31.782 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:49:31.782 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:49:31.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:31.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:31.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:31.782 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:31.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:31.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:49:31.785 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:31.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:49:31.785 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:49:31.786 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:49:31.786 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:49:31.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:49:31.786 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:31.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:31.786 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:49:31.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:49:31.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:49:31.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:31.787 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:49:31.787 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:49:31.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:49:31.787 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:31.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:31.787 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:49:31.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:49:31.787 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:49:31.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:31.788 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:49:31.788 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:49:31.788 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:49:31.788 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:31.788 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:31.788 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:49:31.788 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:49:31.788 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:49:31.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:49:31.791 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:49:31.791 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:49:31.791 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:31.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:31.795 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:49:32.273 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:49:32.310 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:49:32.311 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:49:32.312 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:49:32.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:32.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:49:32.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:49:32.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:49:32.334 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:49:32.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:32.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:49:32.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:49:32.336 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:49:32.336 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:49:32.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:32.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:49:32.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:49:32.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:32.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:32.746 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:49:32.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:32.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:32.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:32.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:33.217 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:49:33.690 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:49:33.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:33.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:33.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:33.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:34.163 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:49:34.635 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:49:34.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:34.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:34.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:34.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:35.106 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:49:35.577 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:49:35.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:35.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:35.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:35.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:36.048 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:49:36.521 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:49:36.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:36.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:36.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:36.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:36.994 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:49:37.465 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:49:37.938 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:49:38.411 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:49:38.883 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:49:39.357 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:49:39.829 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:49:40.316 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:49:40.788 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:49:41.258 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:49:41.730 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:49:42.200 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:49:42.674 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:49:42.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:42.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:42.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:49:42.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:49:42.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:42.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:42.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:42.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:42.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:42.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:42.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:42.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:42.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:49:42.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:49:42.771 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:49:47.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:49:47.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:49:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:47.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:47.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:47.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:49:47.783 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:47.783 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:49:47.784 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:49:47.784 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:49:47.785 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:49:47.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:49:47.785 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:47.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:47.785 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:49:47.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:49:47.785 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:49:47.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:47.786 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:49:47.786 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:49:47.786 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:49:47.786 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:47.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:47.786 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:49:47.786 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:49:47.786 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:49:47.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:47.787 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:49:47.787 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:49:47.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:49:47.787 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:49:47.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:49:47.787 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:49:47.787 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:49:47.787 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:49:47.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:47.789 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:49:47.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:49:47.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:49:47.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:49:47.789 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:49:47.790 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:49:47.790 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:49:47.790 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:49:47.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:49:47.794 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:49:48.272 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:49:48.314 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:49:48.316 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:49:48.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:48.318 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:49:48.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:49:48.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:49:48.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:49:48.361 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:49:48.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:48.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:49:48.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:49:48.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:49:48.367 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:49:48.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:48.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:49:48.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:49:48.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:48.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:48.743 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:49:48.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:48.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:48.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:48.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:49.215 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:49:49.688 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:49:49.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:49.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:49.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:49.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:50.160 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:49:50.633 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:49:50.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:50.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:50.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:50.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:51.106 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:49:51.579 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:49:51.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:51.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:51.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:51.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:52.052 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:49:52.524 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:49:52.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:52.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:52.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:52.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:52.998 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:49:53.470 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:49:53.943 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:49:54.416 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:49:54.889 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:49:55.361 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:49:55.832 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:49:56.306 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:49:56.778 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:49:57.251 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:49:57.721 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:49:58.192 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:49:58.666 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:49:59.139 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:49:59.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:49:59.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:49:59.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:49:59.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:49:59.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:49:59.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:49:59.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:49:59.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:49:59.245 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:49:59.245 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:49:59.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:49:59.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:49:59.246 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:49:59.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:49:59.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:04.251 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:50:04.251 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:50:04.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:04.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:04.251 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:04.251 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:04.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:04.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:50:04.263 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:04.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:50:04.264 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:50:04.265 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:50:04.266 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:50:04.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:50:04.266 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:04.266 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:04.266 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:50:04.266 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:50:04.266 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:50:04.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:04.267 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:50:04.267 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:50:04.267 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:50:04.267 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:04.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:04.268 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:50:04.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:50:04.268 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:50:04.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:04.269 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:50:04.269 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:50:04.269 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:50:04.269 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:04.269 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:04.269 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:50:04.269 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:50:04.269 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:50:04.269 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:50:04.271 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:50:04.271 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:50:04.271 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.271 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:04.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:04.276 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:50:04.754 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:50:04.793 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:50:04.795 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:04.797 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:50:04.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:04.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:50:04.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:50:04.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:50:04.831 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:04.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:04.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:50:04.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:50:04.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:50:04.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:50:04.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:04.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:50:04.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:50:04.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:04.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:05.226 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:50:05.274 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:05.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:05.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:05.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:05.698 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:50:05.712 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:06.171 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:50:06.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:06.276 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:06.276 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:06.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:06.644 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:50:07.116 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:50:07.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:07.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:07.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:07.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:07.590 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:50:08.062 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:50:08.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:08.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:08.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:08.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:08.535 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:50:09.008 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:50:09.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:09.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:09.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:09.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:09.481 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:50:09.953 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:50:10.424 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:50:10.898 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:50:11.370 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:50:11.844 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:50:12.316 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:50:12.789 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:50:13.262 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:50:13.735 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:50:14.207 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:50:14.678 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:50:15.152 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:50:15.624 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:50:16.096 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:50:16.567 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:50:17.041 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:50:17.513 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:50:17.985 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:50:18.456 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:50:18.929 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:50:19.402 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:50:19.875 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:50:20.348 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:50:20.821 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:50:21.293 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:50:21.764 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:50:22.238 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:50:22.711 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:50:23.182 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:50:23.655 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:50:24.127 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:50:24.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:24.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:24.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:50:24.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:50:24.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:24.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:24.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:24.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:24.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:24.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:24.457 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:24.457 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:24.457 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:50:24.457 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:50:24.457 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:50:24.458 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4357 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:50:24.458 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4357 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:50:24.458 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4357 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:50:24.458 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4357 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:50:24.458 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4357 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:50:24.458 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4357 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:50:29.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:50:29.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:50:29.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:29.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:29.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:29.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:29.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:29.469 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:50:29.469 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:29.470 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:50:29.470 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:50:29.474 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:50:29.474 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:50:29.474 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:50:29.474 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:29.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:29.474 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:50:29.475 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:50:29.475 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:50:29.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:29.479 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:50:29.479 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:50:29.479 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:50:29.479 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:29.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:29.479 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:50:29.480 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:50:29.480 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:50:29.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:29.483 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:50:29.483 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:50:29.483 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:50:29.483 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:29.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:29.484 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:50:29.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:50:29.484 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:50:29.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:50:29.489 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:50:29.489 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:50:29.489 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:29.493 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:50:29.973 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:50:30.012 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:50:30.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:30.013 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:30.014 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:50:30.040 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:50:30.040 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:50:30.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:50:30.044 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:30.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:30.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:50:30.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:50:30.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:50:30.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:50:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:30.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:50:30.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:50:30.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:30.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:30.443 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:50:30.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:30.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:30.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:30.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:30.916 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:50:30.932 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:31.388 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:50:31.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:31.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:31.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:31.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:31.862 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:50:31.892 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:32.334 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:50:32.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:32.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:32.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:32.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:32.807 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:50:32.858 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:33.280 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:50:33.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:33.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:33.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:33.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:33.753 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:50:33.823 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:34.227 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:50:34.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:34.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:34.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:34.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:34.699 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:50:34.789 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:35.171 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:50:35.641 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:50:35.744 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:36.113 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:50:36.586 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:50:36.711 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:37.059 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:50:37.532 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:50:37.677 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:38.004 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:50:38.478 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:50:38.637 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:38.950 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:50:39.422 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:50:39.603 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:39.894 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:50:40.367 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:50:40.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:40.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:40.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:50:40.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:50:40.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:40.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:40.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:40.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:40.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:40.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:40.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:50:40.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:50:40.468 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:50:40.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:40.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:45.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:50:45.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:50:45.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:45.474 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:45.474 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:45.474 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:45.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:50:45.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:50:45.484 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:45.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:50:45.485 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:50:45.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:50:45.491 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:50:45.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:50:45.491 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:45.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:50:45.492 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:50:45.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:50:45.492 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:50:45.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:45.495 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:50:45.496 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:50:45.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:50:45.496 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:45.497 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:50:45.497 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:50:45.497 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:50:45.497 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:50:45.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:45.500 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:50:45.500 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:50:45.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:50:45.500 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:50:45.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:50:45.500 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:50:45.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:50:45.500 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:50:45.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:45.504 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:50:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:50:45.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:50:45.505 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:50:45.505 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.505 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:50:45.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:50:45.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:50:45.510 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:50:45.989 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:50:46.031 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:50:46.033 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:46.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:46.035 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:50:46.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:50:46.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:50:46.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:50:46.064 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:50:46.065 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:46.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:46.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:50:46.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:50:46.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:50:46.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:50:46.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:50:46.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:50:46.085 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:46.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:50:46.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:46.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:50:46.460 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:50:46.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:46.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:46.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:46.508 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:46.932 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:50:46.948 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:50:47.405 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:50:47.508 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:47.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:47.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:47.509 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:47.878 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:50:48.350 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:50:48.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:48.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:48.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:48.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:48.823 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:50:49.294 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:50:49.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:49.510 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:49.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:49.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:49.765 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:50:50.238 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:50:50.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:50:50.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:50:50.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:50:50.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:50:50.711 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:50:51.183 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:50:51.656 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:50:52.129 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:50:52.601 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:50:53.072 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:50:53.546 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:50:54.018 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:50:54.491 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:50:54.964 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:50:55.437 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:50:55.909 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:50:56.383 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:50:56.580 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:50:56.855 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:50:57.328 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:50:57.801 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:50:58.274 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:50:58.746 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:50:59.217 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:50:59.688 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:51:00.161 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:51:00.634 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:51:01.106 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:51:01.580 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:51:02.052 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:51:02.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:02.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:02.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:02.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:02.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:02.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:02.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:02.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:02.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:02.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:02.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:02.389 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:51:02.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:02.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:02.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:02.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:02.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:02.389 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:02.390 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:02.390 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:02.390 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:07.392 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:07.392 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:07.392 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:07.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:07.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:07.392 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:07.399 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:07.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:07.400 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:07.400 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:07.400 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:51:07.405 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:51:07.405 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:51:07.406 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:07.406 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:07.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:07.407 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:51:07.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:07.407 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:51:07.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:07.411 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:51:07.411 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:51:07.411 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:07.411 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:07.412 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:07.412 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:51:07.412 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:07.412 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:51:07.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:07.416 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:51:07.416 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:51:07.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:07.416 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:07.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:07.416 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:51:07.416 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:07.416 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:51:07.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.421 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:51:07.422 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:51:07.422 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:07.427 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:51:07.905 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:51:07.950 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:51:07.951 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:51:07.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:07.953 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:51:07.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:07.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:07.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:07.990 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:51:07.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:07.993 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:07.993 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:07.993 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:07.993 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:07.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:08.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:08.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:08.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:08.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:08.377 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:51:08.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:08.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:08.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:08.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:08.849 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:51:08.863 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:51:09.322 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:51:09.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:09.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:09.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:09.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:09.795 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:51:10.267 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:51:10.426 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:10.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:10.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:10.427 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:10.740 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:51:11.213 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:51:11.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:11.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:11.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:11.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:11.686 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:51:12.159 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:51:12.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:12.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:12.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:12.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:12.632 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:51:13.103 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:51:13.576 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:51:14.049 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:51:14.521 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:51:14.994 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:51:15.467 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:51:15.940 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:51:16.413 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:51:16.886 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:51:17.358 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:51:17.829 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:51:18.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:18.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:18.007 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:18.008 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:18.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:18.017 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:18.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:18.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:18.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:18.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:18.022 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:18.022 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:18.022 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:18.022 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:18.022 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:51:18.023 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2288 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:18.023 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2288 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:18.023 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2288 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:18.023 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2288 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:18.023 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2288 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:18.023 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2288 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:23.024 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:23.024 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:23.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:23.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:23.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:23.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:23.031 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:23.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:23.032 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:23.032 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:23.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:51:23.035 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:51:23.035 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:51:23.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:23.035 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:23.036 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:23.036 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:51:23.036 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:23.036 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:51:23.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:23.039 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:51:23.039 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:51:23.039 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:23.040 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:23.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:23.040 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:51:23.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:23.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:51:23.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:23.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:51:23.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:51:23.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:23.044 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:23.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:23.044 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:51:23.044 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:23.044 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:51:23.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:23.049 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:51:23.049 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:51:23.049 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:51:23.049 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:51:23.049 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:51:23.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:51:23.050 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.051 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:23.056 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:51:23.534 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:51:23.587 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:51:23.588 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:51:23.589 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:51:23.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:23.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:23.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:23.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:23.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:23.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:23.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:23.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:23.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:23.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:23.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:23.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:23.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:23.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.004 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:51:24.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:24.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:24.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:24.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:24.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:24.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:24.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:24.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:24.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:24.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:24.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:24.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:24.054 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:24.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:24.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:24.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:24.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:24.476 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:51:24.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:24.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.739 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:24.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:24.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:24.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:24.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:24.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:24.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:24.758 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:24.758 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:24.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:24.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:24.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:24.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:24.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:24.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:24.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:24.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:24.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:24.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:24.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:24.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:24.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:24.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:24.945 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:24.946 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:24.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:24.948 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:51:25.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:25.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:25.057 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:25.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:25.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:25.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:25.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:25.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:25.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:25.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:25.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:25.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:25.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:25.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:25.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:25.349 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:51:25.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:25.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:25.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:25.349 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=497 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:25.349 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=497 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:25.349 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=497 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:25.349 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=497 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:25.349 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=497 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:25.349 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=497 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:30.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:30.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:30.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:30.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:30.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:30.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:30.364 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:30.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:30.366 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:30.366 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:30.366 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:51:30.369 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:51:30.369 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:51:30.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:30.369 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:30.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:30.370 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:51:30.370 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:30.370 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:51:30.370 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:30.371 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:51:30.371 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:51:30.371 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:30.371 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:30.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:30.372 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:51:30.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:30.372 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:51:30.372 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:30.373 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:51:30.373 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:51:30.373 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:30.373 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:30.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:30.374 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:51:30.374 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:30.374 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:51:30.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.376 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:51:30.376 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:51:30.376 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:30.381 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:51:30.860 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:51:30.897 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:51:30.897 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:51:30.898 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:51:30.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:30.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:30.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:30.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:30.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:30.930 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:30.930 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:30.930 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:30.930 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:30.951 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:51:30.956 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 01:51:30.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:30.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:30.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:30.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:30.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:31.331 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:51:31.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:31.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:31.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:31.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:31.803 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:51:31.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:31.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:31.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:31.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:31.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:31.831 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:31.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:31.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:31.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:31.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:31.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:31.835 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:51:31.835 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:31.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:31.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:31.835 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=315 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:31.835 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=315 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:31.835 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=315 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:31.836 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=315 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:31.836 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=315 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:31.836 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=315 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:36.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:36.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:36.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:36.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:36.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:36.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:36.844 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:36.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:36.845 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:36.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:36.845 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:51:36.848 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:51:36.848 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:51:36.848 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:36.849 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:36.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:36.849 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:51:36.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:36.849 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:51:36.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:36.851 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:51:36.851 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:51:36.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:36.851 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:36.851 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:36.851 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:51:36.851 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:36.851 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:51:36.851 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:36.853 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:51:36.853 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:51:36.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:36.853 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:36.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:36.853 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:51:36.853 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:36.853 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:51:36.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:51:36.856 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:51:36.856 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.856 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:36.861 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:51:37.338 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:51:37.379 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:51:37.380 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:51:37.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:37.382 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:51:37.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:37.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:37.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:37.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:37.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:37.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:37.409 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:37.409 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:37.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:37.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:37.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:37.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:37.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:37.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:37.809 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:51:37.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:37.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:37.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:37.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:38.282 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:51:38.754 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:51:38.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:38.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:38.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:38.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:39.225 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:51:39.699 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:51:39.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:39.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:39.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:39.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:40.171 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:51:40.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:40.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:40.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:40.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:40.586 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:40.586 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:40.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:40.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:40.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:40.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:40.588 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:40.588 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:40.643 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:51:40.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:40.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:40.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:40.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:40.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:40.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:40.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:40.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:40.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:40.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:41.115 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:51:41.588 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:51:41.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:41.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:41.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:41.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:42.060 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:51:42.533 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:51:43.006 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:51:43.479 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:51:43.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:43.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:43.816 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:43.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:43.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:43.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:43.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:43.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:43.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:43.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:43.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:43.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:43.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:43.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:43.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:43.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:43.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:43.951 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:51:44.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:44.422 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:51:44.892 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:51:45.365 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:51:45.838 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:51:46.310 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:51:46.781 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:51:47.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:47.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:47.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:47.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:47.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:47.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:47.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:47.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:47.195 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:47.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:47.195 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:47.195 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:47.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:47.254 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:51:47.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:47.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:47.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:47.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:47.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:47.727 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:51:48.199 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:51:48.670 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:51:49.141 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:51:49.615 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:51:50.087 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:51:50.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:50.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:50.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:50.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:50.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:50.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:50.425 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:50.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:50.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:50.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:50.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:50.432 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:50.432 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:50.432 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:50.432 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:51:50.432 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:50.432 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:50.432 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:50.433 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:50.433 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:50.433 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:51:55.432 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:51:55.433 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:51:55.433 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:55.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:55.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:55.433 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:55.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:51:55.436 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:55.436 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:55.436 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:51:55.436 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:51:55.437 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:51:55.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:51:55.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:55.437 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:55.437 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:51:55.437 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:51:55.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:55.438 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:51:55.438 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:51:55.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:55.440 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:51:55.440 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:51:55.440 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:55.440 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:51:55.440 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:51:55.440 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:51:55.440 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:51:55.440 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:51:55.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:55.441 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:51:55.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:51:55.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:51:55.442 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:51:55.442 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:51:55.447 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:51:55.925 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:51:55.965 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:51:55.967 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:51:55.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:51:55.969 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:51:55.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:51:55.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:51:55.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:51:55.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:51:55.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:51:55.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:51:55.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:51:55.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:51:56.397 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:51:56.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:56.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:56.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:56.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:56.868 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:51:57.341 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:51:57.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:57.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:57.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:57.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:57.814 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:51:58.286 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:51:58.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:58.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:58.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:58.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:58.759 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:51:59.232 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:51:59.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:51:59.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:51:59.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:51:59.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:51:59.703 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:52:00.174 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:52:00.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:00.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:00.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:00.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:00.647 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:52:01.120 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:52:01.592 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:52:02.063 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:52:02.536 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:52:03.008 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:52:03.480 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:52:03.952 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:52:04.423 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:52:04.897 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:52:05.369 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:52:05.840 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:52:06.313 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:52:06.785 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:52:07.258 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:52:07.731 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:52:08.203 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:52:08.675 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:52:09.146 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:52:09.620 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:52:09.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:52:09.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:52:09.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:09.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:09.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:09.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:09.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:52:09.906 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:52:09.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:52:09.906 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:52:09.906 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:52:09.906 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:52:09.906 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:52:14.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:52:14.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:52:14.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:52:14.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:52:14.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:52:14.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:52:14.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:52:14.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:52:14.920 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:14.921 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:52:14.921 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:52:14.921 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:52:14.922 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:52:14.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:52:14.922 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:14.922 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:52:14.922 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:52:14.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:52:14.922 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:52:14.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:14.923 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:52:14.923 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:52:14.923 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:52:14.923 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:14.923 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:52:14.923 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:52:14.923 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:52:14.923 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:52:14.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:14.925 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:52:14.925 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:52:14.925 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:52:14.925 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:14.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:52:14.925 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:52:14.925 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:52:14.925 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:52:14.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:52:14.927 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:52:14.927 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:14.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:14.928 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:14.932 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:52:15.410 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:52:15.451 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:52:15.454 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:52:15.456 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:52:15.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:52:15.480 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:52:15.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:52:15.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:52:15.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:52:15.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:52:15.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:52:15.485 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:52:15.485 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:52:15.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:52:15.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:52:15.515 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:52:15.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:52:15.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:52:15.882 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:52:15.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:15.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:15.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:15.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:16.353 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:52:16.827 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:52:16.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:16.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:16.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:16.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:17.299 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:52:17.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:52:17.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:52:17.516 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:52:17.516 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:52:17.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:52:17.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:52:17.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:52:17.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:52:17.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:52:17.772 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:52:17.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:17.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:17.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:17.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:18.245 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:52:18.717 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:52:18.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:18.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:18.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:18.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:19.189 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:52:19.663 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:52:19.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:19.935 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:19.935 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:19.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:20.135 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:52:20.607 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:52:21.078 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:52:21.552 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:52:22.024 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:52:22.496 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:52:22.967 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:52:23.440 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:52:23.913 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:52:24.385 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:52:24.858 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:52:25.331 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:52:25.803 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:52:26.274 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:52:26.745 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:52:27.218 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:52:27.690 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:52:28.162 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:52:28.636 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:52:29.108 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:52:29.580 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:52:30.051 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:52:30.524 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:52:30.997 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:52:31.469 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:52:31.940 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:52:32.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:52:32.225 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:52:32.225 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:52:32.239 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:32.239 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:32.239 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:32.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:32.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:52:32.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:52:32.240 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:52:32.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:52:32.240 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:52:32.240 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:52:32.240 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:52:37.246 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:52:37.246 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:52:37.246 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:52:37.246 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:52:37.246 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:52:37.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:52:37.254 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:52:37.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:52:37.255 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:37.255 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:52:37.255 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:52:37.258 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:52:37.259 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:52:37.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:52:37.259 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:37.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:52:37.259 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:52:37.259 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:52:37.259 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:52:37.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:37.263 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:52:37.263 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:52:37.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:52:37.263 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:37.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:52:37.263 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:52:37.263 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:52:37.263 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:52:37.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:37.267 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:52:37.267 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:52:37.267 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:52:37.267 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:52:37.267 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:52:37.267 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:52:37.267 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:52:37.267 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:52:37.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:37.272 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:52:37.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:52:37.272 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:52:37.272 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:52:37.272 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:52:37.272 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:52:37.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:52:37.273 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:52:37.273 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.275 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:52:37.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:52:37.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:52:37.278 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:52:37.756 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:52:37.802 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:52:37.804 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:52:37.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:52:37.806 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:52:37.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:52:37.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:52:37.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:52:37.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:52:37.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:52:37.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:52:37.812 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:52:37.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:52:38.228 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:52:38.276 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:38.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:38.277 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:38.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:38.699 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:52:39.170 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:52:39.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:39.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:39.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:39.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:39.643 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:52:40.116 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:52:40.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:40.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:40.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:40.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:40.588 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:52:41.062 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:52:41.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:41.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:41.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:41.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:41.534 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:52:42.006 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:52:42.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:42.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:42.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:42.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:42.479 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:52:42.952 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:52:43.424 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:52:43.895 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:52:44.365 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:52:44.839 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:52:45.311 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:52:45.783 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:52:46.254 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:52:46.728 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:52:47.200 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:52:47.672 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:52:48.143 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:52:48.617 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:52:49.089 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:52:49.561 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:52:50.032 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:52:50.505 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:52:50.978 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:52:51.450 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:52:51.921 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:52:52.394 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:52:52.867 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:52:53.339 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:52:53.810 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:52:54.283 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:52:54.756 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:52:55.228 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:52:55.699 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:52:56.172 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:52:56.645 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:52:57.117 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:52:57.590 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:52:58.063 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:52:58.535 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:52:59.006 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:52:59.292 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:52:59.292 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:52:59.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:52:59.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:52:59.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:52:59.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:52:59.299 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:52:59.299 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:52:59.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:52:59.299 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:52:59.299 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:52:59.299 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:52:59.299 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:52:59.300 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4758 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:04.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:53:04.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:53:04.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:53:04.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:53:04.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:53:04.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:53:04.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:53:04.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:53:04.313 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:04.313 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:53:04.313 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:53:04.316 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:53:04.317 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:53:04.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:53:04.317 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:04.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:53:04.318 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:53:04.318 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:53:04.318 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:53:04.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:04.320 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:53:04.320 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:53:04.321 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:53:04.321 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:04.321 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:53:04.321 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:53:04.322 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:53:04.322 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:53:04.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:04.323 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:53:04.323 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:53:04.323 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:53:04.323 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:04.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:53:04.323 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:53:04.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:53:04.324 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:53:04.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:53:04.327 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:53:04.327 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:53:04.327 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:53:04.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:04.332 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:53:04.810 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:53:04.853 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:53:04.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:53:04.856 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:53:04.858 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:53:04.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:53:04.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:53:04.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:53:04.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:53:04.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:53:04.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:53:04.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:53:04.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:53:05.283 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:53:05.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:05.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:05.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:05.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:05.754 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:53:06.227 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:53:06.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:06.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:06.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:06.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:06.700 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:53:07.172 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:53:07.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:07.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:07.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:07.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:07.643 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:53:08.116 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:53:08.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:08.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:08.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:08.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:08.589 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:53:09.061 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:53:09.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:09.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:09.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:09.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:09.532 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:53:10.005 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:53:10.478 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:53:10.950 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:53:11.421 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:53:11.894 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:53:12.367 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:53:12.839 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:53:13.310 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:53:13.783 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:53:14.256 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:53:14.728 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:53:15.201 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:53:15.674 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:53:16.146 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:53:16.617 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:53:17.090 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:53:17.562 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:53:18.034 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:53:18.506 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:53:18.979 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:53:19.451 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:53:19.923 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:53:20.397 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:53:20.869 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:53:21.341 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:53:21.812 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:53:22.285 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:53:22.758 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:53:23.230 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:53:23.701 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:53:24.174 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:53:24.647 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:53:25.119 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:53:25.590 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:53:26.063 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:53:26.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:53:26.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:53:26.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:26.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:26.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:26.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:26.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:53:26.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:53:26.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:53:26.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:53:26.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:53:26.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:53:26.351 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:53:26.351 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:26.351 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:26.351 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:26.351 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:26.351 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:26.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:26.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:53:31.356 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:53:31.356 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:53:31.356 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:53:31.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:53:31.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:53:31.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:53:31.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:53:31.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:53:31.364 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:31.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:53:31.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:53:31.368 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:53:31.368 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:53:31.369 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:53:31.369 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:31.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:53:31.370 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:53:31.370 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:53:31.370 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:53:31.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:31.372 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:53:31.373 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:53:31.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:53:31.373 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:31.373 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:53:31.374 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:53:31.374 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:53:31.374 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:53:31.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:31.376 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:53:31.376 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:53:31.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:53:31.376 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:53:31.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:53:31.376 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:53:31.376 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:53:31.376 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:53:31.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:31.380 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:53:31.381 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:53:31.381 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:53:31.381 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:53:31.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:53:31.385 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:53:31.863 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:53:31.907 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:53:31.909 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:53:31.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:53:31.911 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:53:31.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:53:31.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:53:31.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:53:31.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:53:31.914 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:53:31.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:53:31.914 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:53:31.914 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:53:32.335 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:53:32.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:32.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:32.383 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:32.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:32.806 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:53:33.280 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:53:33.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:33.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:33.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:33.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:33.752 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:53:34.224 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:53:34.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:34.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:34.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:34.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:34.695 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:53:35.168 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:53:35.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:35.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:35.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:35.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:35.641 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:53:36.113 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:53:36.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:53:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:53:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:53:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:53:36.584 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:53:37.057 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:53:37.529 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:53:38.001 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:53:38.472 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:53:38.946 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:53:39.418 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:53:39.890 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:53:40.361 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:53:40.834 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:53:41.307 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:53:41.779 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:53:42.250 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:53:42.723 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:53:43.196 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:53:43.668 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:53:44.139 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:53:44.612 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:53:45.085 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:53:45.557 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:53:46.028 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:53:46.501 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:53:46.973 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:53:47.445 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:53:47.917 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:53:48.390 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:53:48.862 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:53:49.335 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:53:49.808 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:53:50.281 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:53:50.753 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:53:51.224 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:53:51.695 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:53:52.168 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:53:52.640 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:53:53.112 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:53:53.583 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:53:54.056 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:53:54.528 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:53:55.000 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:53:55.471 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:53:55.945 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:53:56.417 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:53:56.889 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:53:57.363 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:53:57.835 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:53:58.307 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:53:58.778 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:53:59.251 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:53:59.723 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:54:00.195 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:54:00.666 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:54:01.140 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:54:01.612 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:54:02.084 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:54:02.555 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:54:03.029 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:54:03.501 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:54:03.973 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:54:04.447 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:54:04.920 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:54:05.392 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:54:05.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:54:05.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:54:05.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:05.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:05.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:05.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:05.409 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:05.409 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:05.409 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:05.409 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:54:05.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:05.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:05.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:05.410 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:05.410 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:05.410 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:05.410 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:05.410 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:05.410 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:05.410 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:10.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:10.414 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:10.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:10.414 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:10.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:10.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:10.422 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:10.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:10.424 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:10.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:10.424 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:54:10.430 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:54:10.430 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:54:10.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:10.430 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:10.431 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:10.431 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:54:10.431 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:10.431 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:54:10.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:10.435 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:54:10.436 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:54:10.436 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:10.436 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:10.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:10.436 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:54:10.436 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:10.436 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:54:10.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:10.440 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:54:10.440 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:54:10.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:10.441 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:10.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:10.441 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:54:10.441 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:10.441 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:54:10.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:54:10.447 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:54:10.448 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:54:10.448 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:54:10.448 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.448 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.449 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:10.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:10.453 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:54:10.930 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:54:10.981 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:54:10.983 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:54:10.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:54:10.985 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:54:10.988 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:54:10.988 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:54:10.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:54:10.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:54:10.990 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:54:10.990 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:54:10.990 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:54:10.990 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:54:11.401 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:54:11.451 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:11.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:11.452 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:11.452 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:11.873 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:54:12.345 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:54:12.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:12.453 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:12.453 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:12.453 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:12.816 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:54:13.290 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:54:13.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:13.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:13.762 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:54:14.234 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:54:14.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:14.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:14.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:14.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:14.705 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:54:15.178 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:54:15.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:15.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:15.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:15.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:15.650 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:54:16.122 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:54:16.593 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:54:17.064 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:54:17.537 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:54:18.010 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:54:18.482 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:54:18.953 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:54:19.427 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:54:19.899 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:54:20.371 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:54:20.845 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:54:21.317 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:54:21.789 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:54:22.260 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:54:22.733 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:54:23.206 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:54:23.678 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:54:24.149 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:54:24.622 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:54:25.095 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:54:25.567 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:54:26.038 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:54:26.511 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:54:26.983 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:54:27.455 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:54:27.927 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:54:28.400 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:54:28.872 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:54:29.344 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:54:29.815 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:54:30.289 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:54:30.761 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:54:31.233 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:54:31.704 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:54:32.178 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:54:32.650 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:54:33.122 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:54:33.593 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:54:34.067 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:54:34.539 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:54:35.011 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:54:35.485 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:54:35.957 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:54:36.429 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:54:36.900 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:54:37.373 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:54:37.846 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:54:38.318 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:54:38.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:54:38.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:54:38.471 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:38.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:38.471 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:38.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:38.472 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:38.472 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:38.472 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:38.472 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:38.472 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:38.472 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:38.472 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:54:43.478 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:43.478 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:43.478 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:43.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:43.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:43.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:43.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:43.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:43.482 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:43.482 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:43.482 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:54:43.483 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:54:43.483 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:54:43.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:43.483 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:43.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:43.483 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:54:43.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:43.483 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:54:43.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:43.484 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:54:43.484 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:54:43.484 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:43.484 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:43.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:43.484 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:54:43.484 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:43.484 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:54:43.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:43.485 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:54:43.485 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:54:43.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:43.485 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:43.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:43.485 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:54:43.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:43.485 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:54:43.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:54:43.488 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:54:43.488 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:54:43.488 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:43.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:43.492 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:54:43.970 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:54:44.009 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:54:44.010 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:54:44.012 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:54:44.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:54:44.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:44.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:44.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:44.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:44.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:44.031 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:44.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:44.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:44.031 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:44.031 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:44.031 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:54:44.031 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:44.032 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:44.032 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:44.032 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:44.032 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:44.032 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:44.032 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:49.032 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:49.032 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:49.032 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:49.032 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:49.032 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:49.032 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:49.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:49.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:49.040 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:49.041 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:49.041 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:54:49.044 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:54:49.044 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:54:49.045 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:49.045 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:49.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:49.045 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:54:49.046 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:49.046 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:54:49.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:49.047 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:54:49.048 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:54:49.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:49.048 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:49.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:49.048 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:54:49.048 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:49.048 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:54:49.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:49.050 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:54:49.050 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:54:49.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:49.051 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:49.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:49.051 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:54:49.051 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:49.051 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:54:49.051 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.054 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:54:49.054 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:54:49.054 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:54:49.054 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:49.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:49.059 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:54:49.537 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:54:49.579 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:54:49.581 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:54:49.581 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:54:49.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:54:49.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:49.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:49.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:49.587 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:49.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:49.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:49.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:49.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:49.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:49.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:49.589 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:54:49.590 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:49.590 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:49.590 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:49.590 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:49.590 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:49.590 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:49.590 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:54.594 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:54.594 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:54.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:54.594 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:54.594 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:54.594 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:54.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:54.603 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:54.604 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:54.604 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:54:54.604 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:54:54.607 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:54:54.607 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:54:54.608 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:54.608 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:54.608 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:54.609 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:54:54.609 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:54:54.609 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:54:54.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:54.610 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:54:54.611 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:54:54.611 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:54.611 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:54.611 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:54.611 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:54:54.611 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:54:54.611 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:54:54.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:54.613 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:54:54.613 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:54:54.613 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:54.613 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:54:54.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:54.614 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:54:54.614 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:54:54.614 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:54:54.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:54:54.617 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:54:54.617 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:54:54.617 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:54:54.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:54:54.622 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:54:55.100 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:54:55.139 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:54:55.140 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:54:55.141 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:54:55.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:54:55.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:54:55.151 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:54:55.151 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:54:55.151 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:54:55.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:54:55.153 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:54:55.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:54:55.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:54:55.153 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:54:55.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:54:55.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:54:55.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:55.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:55.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:54:55.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:00.157 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:00.157 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:00.157 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:00.157 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:00.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:00.157 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:00.160 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:00.160 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:00.161 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:00.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:00.161 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:55:00.161 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:55:00.162 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:55:00.162 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:00.162 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:00.162 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:00.162 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:55:00.162 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:00.162 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:55:00.162 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:00.163 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:55:00.163 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:55:00.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:00.163 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:00.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:00.163 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:55:00.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:00.163 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:55:00.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:00.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:55:00.164 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:55:00.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:00.164 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:00.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:00.164 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:55:00.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:00.164 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:55:00.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.166 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:55:00.167 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:55:00.167 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:55:00.167 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:00.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:00.171 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:55:00.650 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:55:00.691 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:55:00.694 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:55:00.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:55:00.697 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:55:00.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:00.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:00.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:55:00.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:55:00.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:55:00.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:55:00.704 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:55:00.704 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:55:01.123 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:55:01.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:01.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:01.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:01.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:01.596 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:55:02.068 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:55:02.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:02.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:02.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:02.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:02.540 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:55:03.011 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:55:03.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:03.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:03.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:03.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:03.485 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:55:03.957 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:55:04.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:04.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:04.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:04.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:04.429 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:55:04.903 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:55:05.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:05.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:05.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:05.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:05.375 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:55:05.848 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:55:06.321 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:55:06.793 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:55:07.265 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:55:07.736 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:55:08.210 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:55:08.682 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:55:08.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:08.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:08.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:08.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:08.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:08.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:08.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:08.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:08.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:08.756 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:55:08.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:08.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:08.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:08.756 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:08.756 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:08.756 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:08.756 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:08.756 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:08.756 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:13.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:13.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:13.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:13.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:13.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:13.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:13.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:13.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:13.769 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:13.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:13.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:55:13.772 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:55:13.773 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:55:13.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:13.773 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:13.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:13.774 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:55:13.774 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:13.774 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:55:13.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:13.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:55:13.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:55:13.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:13.775 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:13.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:13.776 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:55:13.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:13.776 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:55:13.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:13.778 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:55:13.778 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:55:13.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:13.778 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:13.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:13.778 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:55:13.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:13.778 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:55:13.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:55:13.781 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:55:13.781 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:55:13.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:13.786 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:55:14.264 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:55:14.306 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:55:14.308 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:55:14.311 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:55:14.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:55:14.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:14.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:14.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:55:14.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:55:14.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:55:14.317 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:55:14.317 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:55:14.317 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:55:14.736 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:55:14.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:14.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:14.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:14.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:15.207 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:55:15.681 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:55:15.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:15.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:15.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:15.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:16.153 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:55:16.626 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:55:16.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:16.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:16.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:16.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:17.099 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:55:17.571 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:55:17.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:17.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:17.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:17.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:18.043 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:55:18.514 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:55:18.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:18.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:18.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:18.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:18.988 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:55:19.460 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:55:19.932 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:55:20.403 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:55:20.877 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:55:21.349 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:55:21.821 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:55:22.292 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:55:22.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:22.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:22.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:22.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:22.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:22.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:22.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:22.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:22.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:22.365 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:55:22.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:22.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:22.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:22.365 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:22.365 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:22.365 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:22.365 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:22.365 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:22.365 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:27.371 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:27.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:27.371 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:27.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:27.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:27.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:27.377 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:27.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:27.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:27.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:27.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:55:27.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:55:27.383 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:55:27.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:27.383 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:27.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:27.384 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:55:27.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:27.384 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:55:27.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:27.386 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:55:27.386 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:55:27.387 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:27.387 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:27.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:27.388 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:55:27.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:27.388 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:55:27.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:27.389 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:55:27.390 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:55:27.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:27.390 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:27.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:27.390 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:55:27.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:27.390 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:55:27.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:27.394 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:55:27.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:55:27.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:55:27.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:55:27.394 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:55:27.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:55:27.395 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:55:27.395 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:55:27.395 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:27.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:27.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:27.400 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:55:27.878 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:55:27.928 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:55:27.931 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:55:27.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:55:27.934 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:55:27.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:27.937 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:27.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:55:27.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:55:27.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:55:27.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:55:27.937 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:55:27.937 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:55:28.349 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:55:28.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:28.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:28.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:28.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:28.821 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:55:29.292 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:55:29.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:29.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:29.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:29.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:29.765 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:55:30.238 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:55:30.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:30.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:30.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:30.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:30.709 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:55:31.181 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:55:31.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:31.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:31.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:31.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:31.654 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:55:32.126 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:55:32.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:32.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:32.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:32.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:32.598 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:55:33.069 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:55:33.543 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:55:34.015 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:55:34.487 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:55:34.958 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:55:35.432 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:55:35.903 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:55:35.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:35.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:35.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:35.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:35.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:35.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:35.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:35.983 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:35.983 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:35.983 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:55:35.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:35.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:35.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:35.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:35.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:35.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:35.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:35.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:35.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:55:40.988 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:40.988 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:40.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:41.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:41.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:41.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:41.010 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:41.010 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:41.010 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:41.010 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:41.010 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:55:41.011 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:55:41.011 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:55:41.011 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:41.011 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:41.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:41.011 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:55:41.011 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:41.011 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:55:41.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:41.012 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:55:41.012 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:55:41.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:41.012 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:41.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:41.012 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:55:41.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:41.012 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:55:41.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:41.013 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:55:41.013 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:55:41.014 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:41.014 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:41.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:41.014 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:55:41.014 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:41.014 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:55:41.015 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.017 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:55:41.018 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:55:41.018 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:55:41.018 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:41.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:41.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:41.022 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:55:41.500 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:55:41.546 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:55:41.549 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:55:41.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:55:41.552 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:55:41.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:41.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:41.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:55:41.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:55:41.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:55:41.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:55:41.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:55:41.557 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:55:41.972 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:55:42.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:42.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:42.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:42.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:42.444 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:55:42.917 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:55:43.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:43.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:43.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:43.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:43.390 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:55:43.862 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:55:44.024 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:44.024 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:44.024 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:44.024 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:44.333 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:55:44.806 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:55:45.025 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:45.025 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:45.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:45.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:45.278 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:55:45.751 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:55:46.026 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:46.027 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:46.027 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:46.027 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:46.224 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:55:46.696 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:55:47.168 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:55:47.639 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:55:48.113 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:55:48.585 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:55:49.057 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:55:49.528 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:55:49.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:49.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:49.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:49.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:49.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:49.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:49.597 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:49.597 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:49.597 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:49.597 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:49.597 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:55:49.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:49.597 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:54.605 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:55:54.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:55:54.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:54.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:54.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:54.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:54.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:55:54.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:54.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:54.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:55:54.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:55:54.618 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:55:54.618 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:55:54.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:54.619 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:54.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:55:54.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:55:54.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:55:54.620 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:55:54.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:54.622 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:55:54.622 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:55:54.622 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:54.622 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:54.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:55:54.623 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:55:54.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:55:54.623 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:55:54.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:54.625 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:55:54.625 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:55:54.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:54.625 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:55:54.625 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:55:54.625 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:55:54.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:55:54.625 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:55:54.625 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:55:54.630 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:55:54.630 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:55:54.630 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:55:54.634 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:55:55.114 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:55:55.152 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:55:55.153 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:55:55.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:55:55.154 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:55:55.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:55:55.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:55:55.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:55:55.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:55:55.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:55:55.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:55:55.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:55:55.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:55:55.585 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:55:55.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:55.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:55.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:55.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:56.057 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:55:56.530 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:55:56.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:56.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:56.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:56.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:57.003 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:55:57.475 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:55:57.634 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:57.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:57.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:57.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:57.946 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:55:58.419 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:55:58.636 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:58.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:58.636 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:58.636 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:58.892 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:55:59.364 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:55:59.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:55:59.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:55:59.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:55:59.638 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:55:59.835 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:56:00.308 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:56:00.780 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:56:01.252 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:56:01.723 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:56:02.196 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:56:02.668 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:56:03.140 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:56:03.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:56:03.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:03.215 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:56:03.215 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:56:03.216 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:56:08.223 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:56:08.223 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:56:08.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:08.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:08.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:08.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:08.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:08.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:56:08.236 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:08.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:56:08.236 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:56:08.239 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:56:08.239 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:56:08.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:56:08.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:08.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:08.240 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:56:08.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:56:08.240 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:56:08.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:08.242 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:56:08.242 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:56:08.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:56:08.242 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:08.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:08.242 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:56:08.242 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:56:08.242 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:56:08.242 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:08.245 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:56:08.245 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:56:08.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:56:08.245 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:08.245 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:08.245 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:56:08.245 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:56:08.245 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:56:08.245 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:56:08.248 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:56:08.248 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:56:08.248 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:08.248 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:08.253 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:56:08.730 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:56:08.777 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:56:08.780 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:56:08.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:56:08.784 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:56:08.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:56:08.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:56:08.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:56:08.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:56:08.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:56:08.789 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:56:08.789 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:56:08.789 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:56:09.202 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:56:09.251 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:09.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:09.252 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:09.252 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:09.673 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:56:10.147 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:56:10.253 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:10.253 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:10.253 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:10.253 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:10.619 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:56:11.092 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:56:11.254 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:11.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:11.255 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:11.255 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:11.565 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:56:12.037 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:56:12.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:12.509 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:56:12.980 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:56:13.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:13.257 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:13.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:13.257 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:13.454 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:56:13.926 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:56:14.398 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:56:14.871 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:56:15.344 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:56:15.816 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:56:16.287 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:56:16.760 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:56:17.232 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:56:17.704 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:56:18.175 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:56:18.649 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:56:19.121 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:56:19.593 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:56:20.064 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:56:20.538 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:56:21.010 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:56:21.482 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:56:21.956 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:56:22.428 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:56:22.900 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:56:23.371 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:56:23.844 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:56:24.317 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:56:24.789 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:56:24.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:56:24.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:56:24.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:24.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:24.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:24.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:24.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:24.835 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:24.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:24.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:56:24.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:56:24.835 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:56:24.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:24.835 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3582 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:24.835 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3582 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:29.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:56:29.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:56:29.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:29.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:29.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:29.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:29.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:29.853 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:56:29.853 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:29.853 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:56:29.853 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:56:29.856 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:56:29.857 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:56:29.857 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:56:29.857 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:29.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:29.857 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:56:29.857 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:56:29.858 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:56:29.858 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:29.859 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:56:29.859 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:56:29.859 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:56:29.859 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:29.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:29.860 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:56:29.860 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:56:29.860 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:56:29.860 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:29.862 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:56:29.862 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:56:29.862 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:56:29.862 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:29.862 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:29.862 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:56:29.863 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:56:29.863 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:56:29.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.866 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:56:29.866 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:56:29.866 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:56:29.866 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:29.871 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:56:30.348 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:56:30.397 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:56:30.399 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:56:30.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:56:30.401 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:56:30.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:56:30.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:56:30.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:56:30.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:56:30.409 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:56:30.409 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:56:30.409 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:56:30.409 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:56:30.821 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:56:30.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:30.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:30.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:30.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:31.292 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:56:31.763 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:56:31.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:31.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:31.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:31.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:32.236 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:56:32.708 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:56:32.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:32.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:32.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:32.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:33.180 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:56:33.651 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:56:33.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:33.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:33.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:33.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:34.125 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:56:34.597 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:56:34.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:34.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:34.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:34.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:35.069 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:56:35.540 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:56:36.011 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:56:36.484 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:56:36.957 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:56:37.429 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:56:37.900 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:56:38.373 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:56:38.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:56:38.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:56:38.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:38.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:38.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:38.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:38.466 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:38.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:38.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:38.466 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:38.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:56:38.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:56:38.467 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:56:38.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:38.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:38.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:38.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:38.468 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:38.468 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:38.468 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:56:43.469 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:56:43.469 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:56:43.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:43.469 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:43.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:43.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:43.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:56:43.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:56:43.484 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:43.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:56:43.485 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:56:43.491 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:56:43.491 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:56:43.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:56:43.492 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:43.493 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:56:43.493 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:56:43.494 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:56:43.494 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:56:43.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:43.497 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:56:43.498 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:56:43.498 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:56:43.498 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:43.499 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:56:43.499 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:56:43.500 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:56:43.500 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:56:43.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:43.502 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:56:43.502 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:56:43.503 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:56:43.503 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:56:43.503 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:56:43.503 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:56:43.503 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:56:43.503 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:56:43.503 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:43.506 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:56:43.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:56:43.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:56:43.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:56:43.506 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:56:43.507 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:56:43.507 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:56:43.507 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.507 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:56:43.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:56:43.512 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:56:43.990 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:56:44.038 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:56:44.041 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:56:44.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:56:44.044 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:56:44.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:56:44.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:56:44.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:56:44.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:56:44.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:56:44.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:56:44.055 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:56:44.055 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:56:44.462 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:56:44.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:44.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:44.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:44.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:44.933 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:56:45.407 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:56:45.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:45.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:45.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:45.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:45.879 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:56:46.351 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:56:46.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:46.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:46.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:46.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:46.825 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:56:47.298 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:56:47.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:47.514 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:47.514 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:47.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:47.770 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:56:48.243 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:56:48.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:56:48.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:56:48.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:56:48.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:56:48.715 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:56:49.188 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:56:49.661 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:56:50.133 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:56:50.605 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:56:51.076 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:56:51.549 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:56:52.022 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:56:52.494 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:56:52.965 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:56:53.438 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:56:53.910 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:56:54.382 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:56:54.853 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:56:55.327 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:56:55.799 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:56:56.271 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:56:56.742 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:56:57.215 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:56:57.688 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:56:58.160 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:56:58.633 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:56:59.106 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:56:59.578 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:57:00.049 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:57:00.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:00.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:00.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:00.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:00.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:00.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:00.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:00.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:00.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:00.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:00.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:00.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:00.113 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:57:00.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3586 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:00.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3586 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:00.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3586 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:00.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3586 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:00.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3586 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:00.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3586 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:05.117 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:05.117 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:05.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:05.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:05.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:05.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:05.125 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:05.126 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:05.126 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:05.126 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:05.126 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:57:05.131 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:57:05.132 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:57:05.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:05.132 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:05.132 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:05.132 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:57:05.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:05.132 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:57:05.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:05.136 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:57:05.136 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:57:05.136 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:05.136 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:05.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:05.136 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:57:05.136 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:05.137 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:57:05.137 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:05.139 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:57:05.140 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:57:05.140 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:05.140 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:05.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:05.140 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:57:05.140 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:05.140 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:57:05.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.144 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:57:05.144 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:57:05.144 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:57:05.145 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:05.149 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:57:05.627 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:57:05.668 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:57:05.669 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:57:05.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:57:05.672 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:57:05.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:05.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:05.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:05.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:05.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:05.704 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:05.704 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:05.707 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:05.707 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:05.707 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:05.707 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:57:05.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:05.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:05.708 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:05.708 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:05.708 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:05.708 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:05.708 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:05.708 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:05.708 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:10.711 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:10.711 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:10.711 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:10.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:10.711 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:10.711 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:10.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:10.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:10.717 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:10.717 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:10.717 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:57:10.719 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:57:10.720 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:57:10.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:10.720 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:10.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:10.721 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:57:10.721 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:10.721 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:57:10.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:10.722 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:57:10.722 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:57:10.722 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:10.722 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:10.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:10.723 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:57:10.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:10.723 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:57:10.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:10.725 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:57:10.725 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:57:10.725 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:10.725 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:10.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:10.725 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:57:10.725 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:10.725 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:57:10.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.728 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:57:10.728 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:57:10.728 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:57:10.729 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:10.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:10.733 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:57:11.211 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:57:11.254 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:57:11.256 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:57:11.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:57:11.258 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:57:11.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:11.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:11.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:11.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:11.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:11.309 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:11.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:11.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:11.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:11.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:11.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:11.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:11.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:11.314 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:57:11.314 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:11.314 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:11.314 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:11.314 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:11.314 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:11.315 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:11.315 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:11.315 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=126 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:16.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:16.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:16.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:16.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:16.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:16.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:16.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:16.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:16.325 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:16.326 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:16.326 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:57:16.329 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:57:16.330 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:57:16.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:16.330 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:16.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:16.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:57:16.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:16.331 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:57:16.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:16.334 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:57:16.334 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:57:16.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:16.335 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:16.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:16.335 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:57:16.335 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:16.335 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:57:16.336 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:16.339 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:57:16.339 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:57:16.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:16.339 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:16.339 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:16.339 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:57:16.339 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:16.339 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:57:16.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:16.344 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:57:16.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:57:16.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.345 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:57:16.346 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:57:16.346 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:57:16.346 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:16.350 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:57:16.828 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:57:16.876 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:57:16.878 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:57:16.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:57:16.880 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:57:16.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:16.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:16.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:16.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:16.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:16.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:16.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:16.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:16.928 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:16.928 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:16.928 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:57:16.928 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:16.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:16.928 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:16.928 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:16.928 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:16.928 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:16.929 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:16.929 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:16.929 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:21.932 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:21.932 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:21.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:21.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:21.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:21.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:21.939 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:21.940 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:21.940 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:21.941 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:21.941 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:57:21.943 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:57:21.943 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:57:21.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:21.944 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:21.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:21.944 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:57:21.945 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:21.945 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:57:21.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:21.946 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:57:21.946 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:57:21.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:21.946 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:21.946 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:21.946 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:57:21.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:21.946 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:57:21.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:21.948 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:57:21.948 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:57:21.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:21.948 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:21.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:21.948 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:57:21.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:21.948 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:57:21.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:21.950 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:57:21.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:57:21.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:57:21.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:57:21.950 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:57:21.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:57:21.951 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:57:21.951 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:57:21.951 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:21.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:21.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:21.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:21.956 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:57:22.435 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:57:22.477 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:57:22.479 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:57:22.481 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:57:22.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:57:22.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:22.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:22.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:22.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:22.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:22.534 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:22.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:22.536 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:22.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:22.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:22.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:22.536 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:22.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:22.536 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:57:27.545 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:27.545 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:27.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:27.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:27.546 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:27.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:27.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:27.558 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:27.558 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:27.558 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:27.558 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:57:27.560 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:57:27.560 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:57:27.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:27.560 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:27.560 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:27.561 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:57:27.561 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:27.561 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:57:27.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:27.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:57:27.562 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:57:27.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:27.562 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:27.562 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:27.562 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:57:27.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:27.562 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:57:27.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:27.563 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:57:27.563 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:57:27.563 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:27.563 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:27.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:27.563 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:57:27.563 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:27.563 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:57:27.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:57:27.565 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:57:27.565 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:57:27.565 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:57:27.565 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:27.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:27.570 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:57:28.048 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:57:28.091 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:57:28.093 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:57:28.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:57:28.095 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:57:28.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:28.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:28.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:28.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:28.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:28.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:28.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:28.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:28.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:28.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:28.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:28.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:28.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:28.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:28.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:28.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:57:28.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:33.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:33.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:33.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:33.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:33.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:33.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:33.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:33.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:33.181 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:33.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:33.182 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:57:33.185 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:57:33.186 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:57:33.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:33.186 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:33.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:33.186 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:57:33.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:33.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:57:33.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:33.190 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:57:33.191 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:57:33.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:33.191 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:33.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:33.192 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:57:33.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:33.193 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:57:33.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:33.194 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:57:33.194 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:57:33.194 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:33.195 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:33.195 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:33.195 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:57:33.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:33.195 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:57:33.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:33.199 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:57:33.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:57:33.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:57:33.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:57:33.199 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:57:33.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.200 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:57:33.200 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:57:33.200 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:57:33.200 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:33.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:33.205 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:57:33.683 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:57:33.729 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:57:33.731 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:57:33.734 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:57:33.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:57:33.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:33.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:33.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:33.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:33.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:33.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:33.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:33.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:33.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:33.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:33.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:33.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:33.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:33.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:33.794 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:57:33.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:33.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:33.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:57:38.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:57:38.800 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:57:38.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:38.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:38.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:38.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:38.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:57:38.808 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:38.808 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:38.808 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:57:38.808 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:57:38.811 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:57:38.811 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:57:38.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:38.811 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:38.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:57:38.812 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:57:38.812 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:57:38.812 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:57:38.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:38.814 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:57:38.814 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:57:38.814 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:38.814 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:38.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:57:38.815 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:57:38.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:57:38.815 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:57:38.815 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:38.817 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:57:38.817 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:57:38.817 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:38.817 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:57:38.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:57:38.817 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:57:38.817 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:57:38.817 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:57:38.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:38.820 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:57:38.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:57:38.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:57:38.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:57:38.820 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:57:38.821 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:57:38.821 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:57:38.821 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:57:38.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:57:38.826 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:57:39.304 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:57:39.349 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:57:39.351 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:57:39.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:57:39.353 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:57:39.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:57:39.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:57:39.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:57:39.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:57:39.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:57:39.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:57:39.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:57:39.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:57:39.776 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:57:39.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:39.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:39.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:39.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:40.247 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:57:40.718 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:57:40.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:40.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:40.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:40.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:41.191 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:57:41.664 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:57:41.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:41.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:41.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:41.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:42.136 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:57:42.609 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:57:42.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:42.827 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:42.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:42.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:43.082 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:57:43.554 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:57:43.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:57:43.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:57:43.829 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:57:43.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:57:44.028 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:57:44.500 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:57:44.972 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:57:45.443 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:57:45.916 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:57:46.389 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:57:46.861 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:57:47.332 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:57:47.806 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 01:57:48.278 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 01:57:48.750 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 01:57:49.221 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 01:57:49.694 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 01:57:50.167 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 01:57:50.639 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 01:57:51.110 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 01:57:51.583 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 01:57:52.056 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 01:57:52.528 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 01:57:53.001 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 01:57:53.474 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 01:57:53.946 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 01:57:54.417 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 01:57:54.890 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 01:57:55.362 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 01:57:55.835 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 01:57:56.308 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 01:57:56.781 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 01:57:57.253 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 01:57:57.724 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 01:57:58.197 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 01:57:58.669 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 01:57:59.141 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 01:57:59.615 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 01:58:00.087 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 01:58:00.559 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 01:58:01.030 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 01:58:01.504 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 01:58:01.976 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 01:58:02.448 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 01:58:02.922 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 01:58:03.394 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 01:58:03.866 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 01:58:04.337 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 01:58:04.810 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 01:58:05.283 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 01:58:05.755 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 01:58:06.229 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 01:58:06.701 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 01:58:07.173 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 01:58:07.644 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 01:58:08.115 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 01:58:08.588 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 01:58:09.061 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 01:58:09.533 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 01:58:10.006 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 01:58:10.479 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 01:58:10.951 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 01:58:11.422 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 01:58:11.896 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 01:58:12.368 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 01:58:12.840 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 01:58:12.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:58:12.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:58:12.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:12.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:12.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:12.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:12.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:12.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:12.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:12.854 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:58:12.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:12.854 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:12.854 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:12.854 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7349 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:12.854 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7349 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:12.854 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7349 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:12.855 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7349 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:12.855 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7349 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:12.855 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7349 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:17.855 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:17.856 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:17.856 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:17.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:17.856 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:17.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:17.863 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:17.864 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:17.864 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:17.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:17.865 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:58:17.868 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:58:17.869 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:58:17.869 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:17.869 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:17.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:17.870 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:58:17.870 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:17.870 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:58:17.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:17.872 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:58:17.872 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:58:17.873 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:17.873 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:17.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:17.873 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:58:17.873 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:17.873 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:58:17.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:17.875 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:58:17.875 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:58:17.875 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:17.875 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:17.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:17.876 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:58:17.876 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:17.876 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:58:17.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.879 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:58:17.879 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:58:17.879 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:58:17.880 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:17.884 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:58:18.363 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:58:18.410 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:58:18.412 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:58:18.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:58:18.414 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:58:18.835 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:58:18.883 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:18.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:18.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:18.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:19.310 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:58:19.782 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:58:19.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:19.885 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:19.885 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:19.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:20.257 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:58:20.729 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:58:20.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:20.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:20.887 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:20.887 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:21.203 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:58:21.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:58:21.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:21.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:21.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:21.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:21.434 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:21.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:21.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:21.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:21.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:21.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:21.434 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:58:26.437 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:26.438 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:26.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:26.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:26.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:26.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:26.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:26.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:26.444 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:26.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:26.444 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:58:26.445 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:58:26.445 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:58:26.445 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:26.445 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:26.445 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:26.446 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:58:26.446 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:26.446 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:58:26.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:26.447 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:58:26.447 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:58:26.447 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:26.447 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:26.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:26.447 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:58:26.447 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:26.447 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:58:26.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:26.449 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:58:26.450 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:58:26.450 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:26.450 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:26.450 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:26.450 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:58:26.450 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:26.450 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:58:26.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:26.453 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:58:26.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:58:26.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:58:26.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:58:26.453 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:58:26.454 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:58:26.454 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:58:26.454 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:26.459 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:58:26.937 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:58:26.982 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:58:26.984 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:58:26.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:58:26.986 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:58:27.409 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:58:27.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:27.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:27.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:27.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:27.884 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:58:28.355 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:58:28.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:28.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:28.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:28.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:28.830 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:58:29.302 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:58:29.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:29.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:29.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:29.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:29.778 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:58:30.249 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:58:30.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:30.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:30.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:30.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:30.725 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:58:31.197 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:58:31.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:31.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:31.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:31.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:31.671 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:58:32.143 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:58:32.618 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:58:33.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:33.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:33.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:33.001 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:33.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:33.003 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:33.003 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:33.003 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:58:33.003 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:33.003 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:33.003 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:33.003 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:33.003 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:33.003 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:33.003 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:33.003 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:33.003 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:33.003 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:38.008 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:38.008 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:38.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:38.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:38.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:38.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:38.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:38.024 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:38.024 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:38.024 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:38.025 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:58:38.027 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:58:38.027 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:58:38.027 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:38.027 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:38.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:38.028 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:58:38.028 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:38.028 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:58:38.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:38.029 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:58:38.029 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:58:38.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:38.029 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:38.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:38.029 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:58:38.029 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:38.029 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:58:38.030 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:38.030 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:58:38.030 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:58:38.031 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:38.031 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:38.031 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:38.031 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:58:38.031 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:38.031 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:58:38.031 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:38.032 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:58:38.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:58:38.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:58:38.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:58:38.032 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:58:38.033 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:58:38.033 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:58:38.033 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:38.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:38.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:38.038 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:58:38.517 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:58:38.559 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:58:38.561 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:58:38.563 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:58:38.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:58:38.988 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:58:39.034 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:39.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:39.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:39.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:39.462 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:58:39.935 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:58:40.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:40.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:40.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:40.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:40.406 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:58:40.881 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:58:41.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:41.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:41.038 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:41.038 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:41.353 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:58:41.824 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:58:42.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:42.039 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:42.040 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:42.040 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:42.298 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:58:42.771 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:58:43.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:43.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:43.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:43.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:43.243 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:58:43.717 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:58:44.189 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:58:44.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:44.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:44.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:44.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:44.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:44.577 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:44.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:44.577 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:58:44.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:44.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:44.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:44.577 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:44.577 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:44.577 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:44.577 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:44.577 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:44.577 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1412 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:58:49.584 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:49.584 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:49.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:49.584 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:49.584 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:49.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:49.591 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:49.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:49.592 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:49.593 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:58:49.593 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:58:49.595 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:58:49.596 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:58:49.596 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:49.597 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:49.597 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:49.597 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:58:49.598 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:58:49.598 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:58:49.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:49.601 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:58:49.602 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:58:49.602 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:49.602 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:49.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:49.602 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:58:49.602 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:58:49.602 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:58:49.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:49.606 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:58:49.606 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:58:49.607 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:49.607 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:58:49.607 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:49.607 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:58:49.607 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:58:49.607 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:58:49.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:49.611 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:58:49.611 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:58:49.611 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:58:49.611 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:58:49.611 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:58:49.612 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:58:49.612 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:58:49.612 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.612 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.613 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:58:49.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:58:49.617 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:58:50.096 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:58:50.139 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:58:50.141 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:58:50.143 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:58:50.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:58:50.568 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:58:50.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:50.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:50.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:50.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:51.043 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:58:51.517 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:58:51.616 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:51.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:51.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:51.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:51.990 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:58:52.462 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:58:52.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:52.618 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:52.618 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:52.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:52.937 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:58:53.409 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:58:53.619 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:53.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:53.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:53.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:53.884 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:58:54.356 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:58:54.621 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:54.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:54.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:54.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:54.832 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:58:55.304 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:58:55.779 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:58:56.158 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:58:56.158 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:58:56.158 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:01.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:01.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:01.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:01.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:01.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:01.166 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:01.174 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:01.175 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:01.176 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:01.176 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:01.176 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:01.180 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:01.181 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:01.181 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:01.181 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:01.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:01.182 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:01.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:01.182 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:01.183 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:01.184 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:01.184 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:01.185 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:01.185 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:01.185 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:01.185 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:01.186 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:01.186 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:01.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:01.187 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:01.187 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:01.187 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:01.187 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:01.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:01.188 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:01.188 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:01.188 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:01.188 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:01.191 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:01.191 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:01.191 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.191 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:01.196 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:01.674 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:01.719 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:01.722 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:01.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:01.724 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:02.146 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:59:02.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:02.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:02.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:02.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:02.621 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:59:03.093 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:59:03.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:03.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:03.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:03.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:03.568 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:59:04.039 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:59:04.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:04.198 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:04.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:04.198 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:04.515 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:59:04.987 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:59:05.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:05.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:05.200 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:05.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:05.462 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:59:05.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:05.934 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 01:59:06.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:06.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:06.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:06.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:06.408 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 01:59:06.880 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 01:59:07.352 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 01:59:07.826 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 01:59:08.298 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 01:59:08.770 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 01:59:09.244 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 01:59:09.716 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 01:59:09.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:09.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:09.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:09.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:09.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:09.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:09.752 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:09.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:09.752 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:09.752 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:09.752 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:14.759 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:14.759 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:14.759 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:14.759 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:14.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:14.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:14.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:14.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:14.770 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:14.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:14.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:14.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:14.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:14.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:14.777 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:14.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:14.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:14.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:14.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:14.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:14.781 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:14.781 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:14.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:14.781 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:14.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:14.782 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:14.782 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:14.782 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:14.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:14.785 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:14.785 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:14.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:14.785 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:14.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:14.785 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:14.786 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:14.786 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:14.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:14.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:14.790 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:14.790 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:14.790 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:14.795 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:15.273 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:15.318 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:15.321 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:15.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:15.323 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:15.745 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:59:15.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:15.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:15.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:15.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:16.219 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:59:16.691 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:59:16.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:16.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:16.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:16.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:17.163 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:59:17.638 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:59:17.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:17.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:17.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:17.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:18.110 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:59:18.581 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:59:18.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:18.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:18.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:18.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:19.057 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:59:19.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:19.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:19.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:19.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:19.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:19.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:19.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:19.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:19.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:19.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:19.341 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:24.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:24.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:24.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:24.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:24.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:24.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:24.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:24.355 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:24.356 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:24.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:24.356 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:24.358 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:24.359 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:24.359 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:24.359 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:24.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:24.359 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:24.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:24.360 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:24.360 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:24.362 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:24.362 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:24.362 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:24.362 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:24.363 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:24.363 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:24.363 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:24.363 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:24.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:24.364 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:24.365 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:24.365 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:24.365 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:24.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:24.365 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:24.365 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:24.365 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:24.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:24.367 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:24.367 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:24.367 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:24.368 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:24.368 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:24.368 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.368 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:24.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:24.373 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:24.851 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:24.898 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:24.899 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:24.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:24.901 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:24.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:24.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:24.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:24.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:24.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:24.911 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:24.911 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:24.911 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:24.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:24.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:24.912 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:24.912 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:24.912 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:24.912 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:24.912 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:24.912 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:24.912 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:24.912 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:29.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:29.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:29.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:29.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:29.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:29.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:29.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:29.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:29.927 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:29.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:29.927 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:29.928 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:29.928 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:29.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:29.929 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:29.929 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:29.929 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:29.929 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:29.929 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:29.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:29.931 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:29.931 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:29.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:29.931 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:29.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:29.931 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:29.931 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:29.931 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:29.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:29.933 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:29.933 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:29.933 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:29.933 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:29.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:29.933 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:29.933 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:29.933 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:29.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:29.935 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:29.935 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:29.935 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:29.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:29.940 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:30.418 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:30.459 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:30.461 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:30.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:30.464 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:30.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:30.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:30.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:30.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:30.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:30.514 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:30.514 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:30.514 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:30.514 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:30.514 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:30.514 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:30.514 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:35.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:35.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:35.521 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:35.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:35.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:35.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:35.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:35.530 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:35.530 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:35.530 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:35.530 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:35.533 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:35.533 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:35.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:35.534 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:35.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:35.534 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:35.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:35.535 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:35.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:35.536 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:35.536 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:35.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:35.536 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:35.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:35.536 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:35.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:35.536 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:35.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:35.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:35.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:35.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:35.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:35.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:35.538 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:35.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:35.539 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:35.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.541 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:35.541 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:35.542 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:35.542 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:35.546 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:36.024 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:36.066 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:36.068 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:36.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:36.071 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:36.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:36.081 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:36.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:36.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:36.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:36.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:36.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:36.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:36.085 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:36.085 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:36.085 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:36.085 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:36.085 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:36.085 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:36.085 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:36.085 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:36.085 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 01:59:41.089 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:41.089 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:41.089 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:41.089 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:41.089 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:41.089 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:41.097 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:41.098 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:41.098 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:41.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:41.099 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:41.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:41.104 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:41.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:41.104 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:41.104 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:41.104 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:41.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:41.104 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:41.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:41.108 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:41.108 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:41.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:41.108 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:41.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:41.108 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:41.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:41.108 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:41.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:41.111 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:41.111 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:41.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:41.111 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:41.111 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:41.112 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:41.112 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:41.112 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:41.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:41.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:41.116 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:41.116 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:41.116 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:41.117 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:41.121 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:41.598 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:41.646 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:41.649 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:41.650 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:41.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:41.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:59:41.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:59:41.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:59:41.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:59:41.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:59:41.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:59:41.656 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:59:41.656 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:59:42.070 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:59:42.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:42.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:42.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:42.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:42.541 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:59:43.015 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:59:43.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:43.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:43.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:43.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:43.487 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:59:43.959 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:59:44.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:44.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:44.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:44.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:44.430 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:59:44.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:59:44.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:59:44.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:59:44.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:59:44.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:59:44.760 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:59:44.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:44.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:44.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:44.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:44.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:44.769 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:44.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:44.769 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:44.769 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:44.769 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:44.769 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:44.769 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:49.775 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:49.775 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:49.775 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:49.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:49.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:49.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:49.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:49.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:49.781 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:49.781 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:49.781 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:49.784 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:49.784 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:49.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:49.785 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:49.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:49.785 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:49.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:49.786 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:49.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:49.787 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:49.787 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:49.787 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:49.787 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:49.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:49.788 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:49.788 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:49.788 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:49.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:49.790 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:49.790 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:49.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:49.790 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:49.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:49.790 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:49.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:49.790 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:49.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:49.793 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:49.793 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:49.793 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.793 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:49.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:49.798 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:50.277 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:50.322 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:50.324 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:50.326 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:50.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:50.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:59:50.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:59:50.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:59:50.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:59:50.336 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:59:50.336 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:59:50.336 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:59:50.336 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 01:59:50.749 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 01:59:50.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:50.796 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:50.796 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:50.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:51.220 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 01:59:51.691 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 01:59:51.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:51.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:51.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:51.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:52.165 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 01:59:52.636 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 01:59:52.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:52.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:52.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:52.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:53.108 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 01:59:53.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:59:53.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:59:53.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:59:53.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:59:53.579 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 01:59:53.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:53.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:53.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:53.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:54.053 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 01:59:54.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:59:54.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:59:54.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:54.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:54.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:54.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:54.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:54.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:54.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:54.070 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:54.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:54.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:54.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:54.070 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 01:59:59.076 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 01:59:59.076 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 01:59:59.076 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:59.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:59.076 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:59.076 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:59.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 01:59:59.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:59.085 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:59.085 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 01:59:59.085 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 01:59:59.089 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 01:59:59.089 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 01:59:59.090 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:59.090 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:59.090 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 01:59:59.090 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 01:59:59.091 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 01:59:59.091 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 01:59:59.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 01:59:59.092 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 01:59:59.093 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 01:59:59.093 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:59.093 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:59.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 01:59:59.093 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 01:59:59.093 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 01:59:59.093 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 01:59:59.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 01:59:59.095 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 01:59:59.096 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 01:59:59.096 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:59.096 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 01:59:59.096 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 01:59:59.096 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 01:59:59.096 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 01:59:59.096 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 01:59:59.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 01:59:59.100 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 01:59:59.100 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 01:59:59.100 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 01:59:59.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 01:59:59.104 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 01:59:59.582 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 01:59:59.631 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 01:59:59.634 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 01:59:59.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 01:59:59.636 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 01:59:59.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 01:59:59.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 01:59:59.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 01:59:59.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 01:59:59.647 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 01:59:59.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 01:59:59.647 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 01:59:59.647 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:00:00.054 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:00:00.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:00.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:00.103 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:00.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:00.525 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:00:00.999 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:00:01.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:01.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:01.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:01.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:01.471 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:00:01.943 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:00:02.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:02.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:02.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:02.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:02.414 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:00:02.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:02.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:02.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:02.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:02.887 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:00:03.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:03.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:03.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:03.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:03.360 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:00:03.832 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:00:04.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:04.109 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:04.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:04.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:04.305 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:00:04.778 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:00:05.250 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:00:05.721 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:00:06.194 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:00:06.667 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:00:07.139 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:00:07.610 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:00:07.700 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:07.700 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:07.701 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:07.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:07.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:07.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:07.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:07.721 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:07.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:07.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:07.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:07.721 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:07.721 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:07.721 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:00:07.721 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:07.721 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:07.721 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:07.721 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:07.721 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:07.721 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:12.725 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:12.725 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:12.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:12.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:12.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:12.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:12.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:12.732 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:12.732 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:12.733 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:12.733 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:00:12.735 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:00:12.735 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:00:12.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:12.736 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:12.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:12.736 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:00:12.737 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:12.737 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:00:12.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:12.738 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:00:12.738 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:00:12.738 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:12.738 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:12.738 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:12.738 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:00:12.738 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:12.738 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:00:12.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:12.740 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:00:12.740 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:00:12.740 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:12.740 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:12.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:12.740 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:00:12.740 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:12.740 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:00:12.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:00:12.743 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:00:12.743 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:00:12.743 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:12.748 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:00:13.225 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:00:13.272 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:00:13.274 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:00:13.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:13.275 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:00:13.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:13.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:13.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:00:13.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:13.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:13.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:13.283 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:00:13.283 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:00:13.696 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:00:13.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:13.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:13.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:13.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:14.168 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:00:14.640 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:00:14.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:14.746 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:14.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:14.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:15.111 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:00:15.584 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:00:15.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:15.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:15.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:15.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:16.057 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:00:16.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:16.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:16.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:16.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:16.529 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:00:16.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:16.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:16.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:16.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:17.003 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:00:17.475 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:00:17.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:17.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:17.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:17.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:17.947 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:00:18.418 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:00:18.891 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:00:19.364 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:00:19.836 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:00:20.307 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:00:20.780 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:00:21.253 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:00:21.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:21.345 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:21.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:21.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:21.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:21.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:21.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:21.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:21.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:21.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:21.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:21.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:21.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:21.365 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:00:21.366 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:21.366 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:21.366 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:21.366 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:21.366 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:21.366 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:26.370 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:26.370 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:26.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:26.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:26.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:26.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:26.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:26.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:26.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:26.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:26.380 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:00:26.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:00:26.383 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:00:26.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:26.383 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:26.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:26.384 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:00:26.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:26.384 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:00:26.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:26.385 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:00:26.385 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:00:26.385 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:26.385 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:26.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:26.386 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:00:26.386 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:26.386 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:00:26.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:26.387 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:00:26.388 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:00:26.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:26.388 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:26.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:26.388 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:00:26.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:26.388 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:00:26.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:00:26.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:00:26.391 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:00:26.391 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:00:26.391 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:26.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:26.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:26.395 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:00:26.872 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:00:26.917 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:00:26.919 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:00:26.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:26.921 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:00:26.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:26.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:26.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:00:26.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:26.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:26.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:26.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:00:26.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:00:27.343 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:00:27.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:27.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:27.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:27.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:27.815 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:00:28.286 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:00:28.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:28.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:28.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:28.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:28.757 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:00:29.227 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:00:29.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:29.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:29.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:29.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:29.698 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:00:29.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:29.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:29.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:29.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:30.169 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:00:30.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:30.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:30.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:30.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:30.640 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:00:31.111 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:00:31.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:31.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:31.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:31.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:31.581 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:00:32.052 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:00:32.526 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:00:32.998 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:00:33.470 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:00:33.941 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:00:34.415 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:00:34.887 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:00:34.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:34.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:34.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:35.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:35.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:35.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:35.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:35.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:35.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:35.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:35.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:35.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:35.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:35.004 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:00:35.004 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1863 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:35.004 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1863 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:35.004 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1863 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:35.004 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1863 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:35.004 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1863 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:40.009 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:40.009 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:40.009 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:40.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:40.009 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:40.009 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:40.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:40.016 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:40.017 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:40.017 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:40.017 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:00:40.021 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:00:40.022 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:00:40.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:40.022 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:40.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:40.022 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:00:40.023 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:40.023 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:00:40.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:40.026 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:00:40.026 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:00:40.027 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:40.027 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:40.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:40.028 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:00:40.028 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:40.028 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:00:40.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:40.029 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:00:40.030 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:00:40.030 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:40.030 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:40.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:40.030 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:00:40.030 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:40.030 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:00:40.030 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:00:40.034 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:00:40.035 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:00:40.035 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:00:40.035 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.035 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.036 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:40.040 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:00:40.518 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:00:40.560 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:00:40.562 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:00:40.564 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:00:40.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:40.571 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:40.571 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:40.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:00:40.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:40.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:40.573 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:40.573 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:00:40.574 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:00:40.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:40.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:40.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:40.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:40.990 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:00:41.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:41.037 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:41.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:41.462 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:00:41.935 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:00:42.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:42.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:42.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:42.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:42.408 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:00:42.880 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:00:43.038 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:43.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:43.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:43.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:43.351 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:00:43.824 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:00:44.039 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:44.049 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:44.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:44.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:44.296 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:00:44.768 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:00:45.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:45.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:45.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:45.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:45.239 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:00:45.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:45.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:45.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:45.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:45.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:45.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:45.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:45.626 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:45.626 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:45.626 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:00:45.626 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:45.626 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:45.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:45.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1208 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:45.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1208 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:45.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1208 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:45.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1208 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:45.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1208 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:45.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1208 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:45.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1208 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:50.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:50.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:50.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:50.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:50.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:50.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:50.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:50.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:50.642 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:50.642 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:00:50.642 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:00:50.648 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:00:50.648 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:00:50.648 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:50.648 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:50.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:50.649 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:00:50.649 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:00:50.649 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:00:50.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:50.653 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:00:50.653 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:00:50.653 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:50.653 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:50.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:50.654 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:00:50.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:00:50.654 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:00:50.654 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:50.657 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:00:50.657 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:00:50.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:50.657 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:00:50.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:50.658 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:00:50.658 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:00:50.658 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:00:50.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:50.663 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:00:50.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:00:50.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:00:50.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:00:50.663 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:00:50.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.664 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:00:50.664 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:00:50.664 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:00:50.664 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:00:50.669 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:00:51.147 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:00:51.202 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:00:51.205 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:00:51.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:51.208 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:00:51.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:51.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:51.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:00:51.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:51.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:51.215 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:51.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:00:51.216 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:00:51.620 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:00:51.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:51.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:51.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:51.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:52.091 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:00:52.563 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:00:52.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:52.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:52.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:52.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:53.036 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:00:53.508 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:00:53.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:53.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:53.673 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:53.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:53.979 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:00:54.262 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:00:54.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:00:54.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:54.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:00:54.453 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:00:54.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:54.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:54.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:54.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:54.925 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:00:55.397 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:00:55.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:55.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:55.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:55.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:55.868 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:00:56.341 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:00:56.814 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:00:56.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:00:56.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:00:56.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:00:56.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:00:56.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:00:56.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:00:56.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:00:56.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:00:56.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:00:56.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:00:56.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:00:56.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:00:56.876 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:00:56.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:00:56.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1341 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:56.877 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1341 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:56.877 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1341 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:56.877 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1341 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:56.877 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1341 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:56.877 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1341 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:00:56.877 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1341 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:01.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:01.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:01.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:01.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:01.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:01.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:01.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:01.889 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:01.890 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:01.890 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:01.890 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:01:01.895 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:01:01.896 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:01:01.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:01.896 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:01.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:01.896 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:01:01.897 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:01.897 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:01:01.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:01.900 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:01:01.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:01:01.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:01.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:01.901 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:01.901 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:01:01.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:01.901 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:01:01.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:01.905 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:01:01.905 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:01:01.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:01.905 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:01.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:01.905 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:01:01.905 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:01.905 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:01:01.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:01:01.910 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:01:01.910 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:01:01.910 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:01.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:01.915 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:01:02.393 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:01:02.435 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:01:02.438 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:01:02.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:02.440 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:01:02.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:02.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:02.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:01:02.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:01:02.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:01:02.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:01:02.450 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:01:02.450 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:01:02.865 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:01:02.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:02.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:02.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:02.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:03.336 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:01:03.810 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:01:03.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:03.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:03.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:03.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:04.282 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:01:04.754 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:01:04.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:04.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:04.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:04.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:05.225 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:01:05.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:05.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:05.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:05.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:05.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:05.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:05.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:05.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:05.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:05.546 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:05.546 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:05.546 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:01:05.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:05.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:10.554 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:10.554 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:10.554 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:10.554 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:10.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:10.554 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:10.563 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:10.564 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:10.564 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:10.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:10.565 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:01:10.568 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:01:10.569 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:01:10.569 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:10.569 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:10.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:10.570 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:01:10.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:10.571 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:01:10.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:10.573 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:01:10.573 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:01:10.573 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:10.574 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:10.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:10.574 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:01:10.575 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:10.575 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:01:10.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:10.577 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:01:10.577 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:01:10.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:10.577 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:10.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:10.577 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:01:10.578 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:10.578 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:01:10.578 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:10.582 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:01:10.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:01:10.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:01:10.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:01:10.582 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:01:10.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.583 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:01:10.583 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:01:10.583 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:01:10.583 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.584 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:10.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:10.588 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:01:11.067 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:01:11.118 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:01:11.120 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:01:11.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:11.124 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:01:11.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:11.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:11.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:01:11.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:01:11.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:01:11.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:01:11.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:01:11.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:01:11.539 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:01:11.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:11.587 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:11.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:11.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:12.010 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:01:12.484 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:01:12.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:12.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:12.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:12.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:12.956 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:01:13.428 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:01:13.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:13.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:13.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:13.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:13.899 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:01:14.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:14.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:14.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:14.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:14.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:14.220 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:14.220 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:14.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:14.223 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:14.223 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:14.223 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:14.223 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:01:14.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:14.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:14.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:14.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:14.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:14.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:14.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:14.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:19.227 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:19.227 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:19.227 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:19.227 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:19.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:19.227 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:19.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:19.230 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:19.230 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:19.230 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:19.230 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:01:19.231 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:01:19.231 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:01:19.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:19.232 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:19.232 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:19.232 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:01:19.232 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:19.232 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:01:19.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:19.233 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:01:19.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:01:19.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:19.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:19.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:19.233 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:01:19.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:19.233 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:01:19.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:19.234 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:01:19.234 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:01:19.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:19.234 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:19.234 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:19.234 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:01:19.234 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:19.234 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:01:19.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.236 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:01:19.236 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:01:19.236 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:01:19.236 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:19.241 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:01:19.720 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:01:19.762 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:01:19.764 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:01:19.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:19.767 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:01:19.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:19.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:19.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:01:19.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:01:19.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:01:19.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:01:19.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:01:19.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:01:20.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:20.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:20.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:20.042 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:20.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:20.042 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:20.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:20.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:20.043 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:20.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:20.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:20.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:20.043 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:01:20.043 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:20.043 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:20.043 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:20.043 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:20.043 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:20.043 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:20.043 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:25.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:25.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:25.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:25.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:25.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:25.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:25.058 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:25.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:25.059 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:25.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:25.060 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:01:25.062 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:01:25.062 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:01:25.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:25.063 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:25.063 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:25.064 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:01:25.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:25.064 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:01:25.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:25.065 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:01:25.065 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:01:25.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:25.066 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:25.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:25.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:01:25.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:25.066 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:01:25.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:25.068 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:01:25.068 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:01:25.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:25.068 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:25.068 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:25.068 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:01:25.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:25.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:01:25.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:01:25.071 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:01:25.071 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:25.076 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:01:25.554 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:01:25.600 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:01:25.603 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:01:25.604 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:25.605 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:01:25.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:25.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:25.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:01:25.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:01:25.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:01:25.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:01:25.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:01:25.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:01:25.824 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:25.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:25.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:25.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:25.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:25.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:25.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:25.833 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:25.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:25.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:25.833 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:25.833 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:25.833 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:01:25.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:25.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:25.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:25.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:25.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:25.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:30.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:30.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:30.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:30.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:30.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:30.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:30.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:30.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:30.845 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:30.845 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:30.845 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:01:30.848 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:01:30.849 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:01:30.849 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:30.849 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:30.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:30.850 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:01:30.851 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:30.851 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:01:30.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:30.852 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:01:30.853 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:01:30.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:30.853 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:30.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:30.853 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:01:30.854 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:30.854 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:01:30.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:30.855 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:01:30.856 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:01:30.856 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:30.856 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:30.856 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:30.856 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:01:30.856 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:30.856 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:01:30.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:01:30.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:01:30.860 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:01:30.860 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:01:30.860 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:30.865 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:01:31.341 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:01:31.387 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:01:31.390 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:01:31.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:31.392 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:01:31.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:31.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:31.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:01:31.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:01:31.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:01:31.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:01:31.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:01:31.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:01:31.813 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:01:31.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:31.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:31.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:31.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:32.284 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:01:32.757 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:01:32.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:32.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:32.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:32.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:33.230 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:01:33.702 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:01:33.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:33.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:33.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:33.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:34.173 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:01:34.646 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:01:34.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:34.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:34.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:34.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:35.119 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:01:35.590 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:01:35.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:35.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:35.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:35.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:36.062 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:01:36.535 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:01:37.008 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:01:37.480 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:01:37.951 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:01:38.421 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:01:38.895 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:01:39.367 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:01:39.839 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:01:40.187 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:40.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:40.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:40.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:40.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:40.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:40.194 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:40.194 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:40.194 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:40.194 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:01:40.194 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:40.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:40.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:40.194 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:40.194 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:40.194 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:40.194 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:40.194 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:40.194 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:40.194 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:45.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:45.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:45.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:45.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:45.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:45.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:45.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:45.216 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:45.216 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:45.217 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:45.217 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:01:45.219 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:01:45.219 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:01:45.219 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:45.219 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:45.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:45.220 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:01:45.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:45.220 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:01:45.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:45.221 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:01:45.221 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:01:45.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:45.221 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:45.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:45.221 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:01:45.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:45.221 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:01:45.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:45.223 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:01:45.223 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:01:45.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:45.223 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:45.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:45.223 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:01:45.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:45.223 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:01:45.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:01:45.225 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:01:45.225 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:01:45.225 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:45.225 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:45.230 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:01:45.708 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:01:45.753 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:01:45.755 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:01:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:01:45.757 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:01:45.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:45.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:45.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:01:45.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:01:45.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:01:45.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:01:45.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:01:45.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:01:46.179 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:01:46.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:46.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:46.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:46.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:46.651 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:01:47.122 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:01:47.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:47.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:47.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:47.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:47.595 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:01:48.068 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:01:48.230 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:48.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:48.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:48.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:48.540 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:01:49.011 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:01:49.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:49.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:49.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:49.232 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:49.484 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:01:49.957 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:01:50.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:50.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:50.233 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:50.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:50.429 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:01:50.900 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:01:51.373 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:01:51.846 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:01:52.318 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:01:52.791 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:01:53.264 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:01:53.736 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:01:54.207 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:01:54.564 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:01:54.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:01:54.570 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:54.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:54.570 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:54.570 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:54.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:54.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:54.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:54.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:54.572 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:54.572 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:54.572 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:01:54.572 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:54.572 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:54.572 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:54.572 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:54.572 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:01:59.576 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:01:59.577 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:01:59.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:59.577 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:59.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:59.577 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:59.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:01:59.591 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:59.591 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:59.591 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:01:59.592 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:01:59.593 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:01:59.594 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:01:59.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:59.594 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:59.594 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:01:59.594 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:01:59.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:01:59.595 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:01:59.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:01:59.596 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:01:59.596 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:01:59.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:59.596 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:59.596 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:01:59.596 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:01:59.596 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:01:59.596 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:01:59.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:01:59.597 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:01:59.597 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:01:59.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:59.598 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:01:59.598 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:01:59.598 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:01:59.598 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:01:59.598 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:01:59.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:01:59.599 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:01:59.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:01:59.600 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:01:59.600 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:01:59.600 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:01:59.605 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:02:00.081 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:02:00.125 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:02:00.128 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:02:00.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:00.130 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:00.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:02:00.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:02:00.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:02:00.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:02:00.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:02:00.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:02:00.140 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:02:00.140 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:02:00.553 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:02:00.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:00.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:00.603 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:00.603 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:01.025 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:02:01.498 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:02:01.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:01.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:01.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:01.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:01.969 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:02:02.434 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:02:02.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:02.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:02.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:02.605 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:02.899 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:02:03.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:02:03.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:02:03.179 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:02:03.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:02:03.225 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.267 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.304 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.345 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.363 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:02:03.378 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.415 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.456 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.498 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.535 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.576 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:03.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:03.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:03.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:03.618 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.655 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:03.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:02:03.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:02:03.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:03.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:03.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:03.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:03.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:03.698 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:03.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:03.698 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:03.698 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:03.698 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:02:03.698 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:03.698 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:08.709 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:08.709 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:08.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:08.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:08.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:08.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:08.721 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:08.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:08.722 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:08.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:08.722 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:02:08.724 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:02:08.725 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:02:08.725 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:08.725 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:08.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:08.725 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:02:08.725 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:08.725 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:02:08.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:08.728 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:02:08.728 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:02:08.728 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:08.728 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:08.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:08.729 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:02:08.729 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:08.729 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:02:08.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:08.732 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:02:08.732 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:02:08.732 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:08.732 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:08.732 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:08.732 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:02:08.732 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:08.732 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:02:08.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.735 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:02:08.735 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:02:08.735 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:02:08.736 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:08.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:08.740 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:02:09.212 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:02:09.264 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:02:09.266 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:02:09.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:09.269 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:09.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:09.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:09.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:09.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:09.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:09.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:09.477 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:09.477 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:09.478 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:02:09.478 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:09.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:14.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:14.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:14.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:14.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:14.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:14.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:14.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:14.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:14.483 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:14.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:14.483 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:02:14.485 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:02:14.485 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:02:14.485 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:14.485 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:14.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:14.485 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:02:14.485 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:14.485 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:02:14.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:14.487 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:02:14.487 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:02:14.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:14.487 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:14.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:14.487 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:02:14.487 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:14.487 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:02:14.487 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:14.488 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:02:14.488 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:02:14.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:14.489 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:14.489 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:14.489 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:02:14.489 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:14.489 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:02:14.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:14.491 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:02:14.491 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:02:14.491 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:02:14.491 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:02:14.491 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:02:14.492 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:02:14.492 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:02:14.492 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.492 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:14.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:14.493 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:14.497 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:02:14.961 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:02:15.004 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:02:15.004 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:02:15.005 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:15.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:15.424 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:02:15.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:15.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:15.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:15.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:15.890 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:02:16.354 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:02:16.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:16.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:16.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:16.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:16.816 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:02:17.278 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:02:17.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:17.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:17.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:17.495 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:17.742 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:02:18.205 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:02:18.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:18.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:18.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:18.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:18.672 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:02:19.137 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:02:19.497 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:19.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:19.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:19.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:19.600 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:02:20.062 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:02:20.524 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:02:20.986 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:02:21.449 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:02:21.911 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:02:22.373 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:02:22.835 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:02:23.297 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:02:23.758 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:02:24.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:24.023 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:24.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:24.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:24.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:24.024 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:24.024 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:24.024 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:24.024 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:24.024 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:24.024 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:24.024 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:02:29.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:29.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:29.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:29.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:29.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:29.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:29.033 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:29.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:29.033 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:29.033 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:29.033 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:02:29.035 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:02:29.035 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:02:29.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:29.035 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:29.035 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:29.035 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:02:29.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:29.035 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:02:29.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:29.037 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:02:29.037 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:02:29.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:29.037 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:29.037 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:29.037 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:02:29.037 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:29.037 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:02:29.037 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:29.039 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:02:29.039 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:02:29.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:29.039 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:29.039 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:29.039 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:02:29.039 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:29.039 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:02:29.039 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:02:29.042 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:02:29.042 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:02:29.042 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:29.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:29.047 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:02:29.512 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:02:29.554 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:02:29.554 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:02:29.554 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:29.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:29.975 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:02:30.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:30.045 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:30.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:30.045 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:30.443 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:02:30.909 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:02:31.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:31.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:31.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:31.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:31.374 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:02:31.839 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:02:32.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:32.304 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:02:32.767 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:02:33.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:33.047 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:33.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:33.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:33.233 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:02:33.696 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:02:34.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:34.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:34.048 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:34.048 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:34.162 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:02:34.629 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:02:35.094 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:02:35.560 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:02:36.025 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:02:36.491 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:02:36.956 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:02:37.421 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:02:37.888 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:02:38.351 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:02:38.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:38.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:38.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:38.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:38.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:38.568 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:38.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:38.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:38.568 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:02:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:38.568 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2089 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:38.568 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2089 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:38.568 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2089 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:38.568 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2089 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:38.568 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2089 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:38.568 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2089 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:43.574 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:43.574 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:43.574 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:43.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:43.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:43.574 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:43.583 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:43.585 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:43.585 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:43.586 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:43.586 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:02:43.591 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:02:43.592 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:02:43.593 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:43.593 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:43.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:43.594 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:02:43.594 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:43.595 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:02:43.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:43.597 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:02:43.598 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:02:43.598 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:43.598 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:43.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:43.599 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:02:43.600 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:43.600 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:02:43.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:43.602 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:02:43.603 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:02:43.603 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:43.603 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:43.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:43.603 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:02:43.603 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:43.604 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:02:43.604 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:43.607 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.608 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:02:43.608 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:02:43.608 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:02:43.609 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:43.613 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:02:44.092 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:02:44.136 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:02:44.138 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:02:44.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:44.139 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:44.564 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:02:44.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:44.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:44.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:44.613 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:45.039 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:02:45.511 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:02:45.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:45.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:45.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:45.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:45.986 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:02:46.458 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:02:46.615 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:46.615 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:46.616 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:46.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:46.934 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:02:47.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:47.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:47.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:47.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:47.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:47.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:47.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:47.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:47.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:47.171 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:47.171 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:47.171 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:02:52.176 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:52.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:52.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:52.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:52.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:52.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:52.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:52.186 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:52.187 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:52.187 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:52.187 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:02:52.192 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:02:52.192 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:02:52.192 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:52.192 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:52.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:52.192 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:02:52.193 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:52.193 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:02:52.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:52.197 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:02:52.197 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:02:52.198 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:52.198 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:52.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:52.198 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:02:52.198 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:52.198 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:02:52.198 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:52.201 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:02:52.201 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:02:52.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:52.201 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:52.201 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:52.201 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:02:52.201 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:52.201 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:02:52.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:52.204 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:02:52.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:02:52.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:02:52.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:02:52.204 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:02:52.205 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:02:52.205 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:02:52.205 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:52.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:52.210 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:02:52.688 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:02:52.735 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:02:52.737 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:02:52.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:52.740 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:52.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:02:52.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:02:52.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:02:52.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:02:52.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:02:52.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:02:52.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:02:52.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:02:52.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:52.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:02:52.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:02:52.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:02:52.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:02:53.160 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:02:53.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:53.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:02:53.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:02:53.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:02:53.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:53.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:53.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:53.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:53.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:53.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:53.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:53.183 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:02:53.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:53.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:53.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:53.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:53.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:53.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:53.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:53.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:53.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:58.186 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:58.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:58.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:58.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:58.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:58.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:58.197 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:58.198 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:58.199 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:58.199 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:02:58.199 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:02:58.202 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:02:58.202 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:02:58.202 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:58.203 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:58.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:58.203 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:02:58.204 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:02:58.204 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:02:58.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:58.205 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:02:58.205 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:02:58.205 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:58.205 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:58.205 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:58.205 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:02:58.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:02:58.206 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:02:58.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:58.207 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:02:58.208 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:02:58.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:58.208 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:02:58.208 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:58.208 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:02:58.208 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:02:58.208 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:02:58.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:58.210 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:02:58.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:02:58.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:02:58.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:02:58.210 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:02:58.211 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:02:58.211 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:02:58.211 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:02:58.216 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:02:58.694 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:02:58.733 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:02:58.736 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:02:58.736 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:02:58.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:02:58.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:02:58.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:02:58.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:02:58.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:02:58.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:02:58.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:02:58.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:02:58.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:02:58.753 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:02:58.753 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:02:58.753 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:02:58.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:58.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:58.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:58.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:02:58.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:03.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:03.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:03.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:03.757 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:03.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:03.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:03.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:03.768 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:03.768 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:03.769 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:03.769 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:03:03.775 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:03:03.775 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:03:03.775 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:03.775 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:03.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:03.776 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:03:03.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:03.776 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:03:03.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:03.780 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:03:03.781 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:03:03.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:03.781 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:03.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:03.781 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:03:03.781 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:03.781 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:03:03.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:03.784 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:03:03.785 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:03:03.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:03.785 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:03.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:03.785 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:03:03.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:03.785 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:03:03.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.789 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:03:03.790 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:03:03.790 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:03:03.790 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.790 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:03.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:03.794 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:03:04.273 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:03:04.315 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:03:04.318 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:03:04.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:03:04.320 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:03:04.745 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:03:04.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:04.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:04.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:04.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:05.218 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:03:05.691 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:03:05.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:05.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:05.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:05.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:06.163 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:03:06.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:06.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:06.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:06.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:06.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:06.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:06.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:06.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:06.344 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:06.344 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:06.344 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:03:06.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=551 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:06.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=551 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:06.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=551 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:06.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=551 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:06.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=551 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:06.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=551 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:11.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:11.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:11.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:11.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:11.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:11.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:11.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:11.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:11.356 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:11.356 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:11.356 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:03:11.358 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:03:11.359 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:03:11.359 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:11.359 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:11.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:11.359 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:03:11.359 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:11.359 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:03:11.359 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:11.362 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:03:11.362 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:03:11.362 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:11.362 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:11.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:11.362 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:03:11.363 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:11.363 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:03:11.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:11.366 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:03:11.366 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:03:11.366 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:11.366 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:11.366 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:11.366 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:03:11.366 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:11.366 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:03:11.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:11.371 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:03:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:03:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:03:11.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:03:11.371 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.372 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:03:11.372 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:03:11.372 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:03:11.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:11.377 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:03:11.856 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:03:11.906 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:03:11.909 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:03:11.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:03:11.911 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:03:11.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:11.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:11.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:03:11.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:03:11.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:03:11.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:03:11.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:03:11.917 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:03:12.328 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:03:12.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:12.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:12.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:12.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:12.799 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:03:13.270 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:03:13.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:13.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:13.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:13.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:13.743 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:03:14.216 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:03:14.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:14.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:14.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:14.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:14.688 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:03:14.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:14.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:14.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:14.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:14.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:14.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:14.712 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:14.712 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:14.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:14.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:14.712 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:14.712 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:14.712 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:03:19.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:19.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:19.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:19.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:19.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:19.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:19.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:19.736 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:19.736 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:19.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:19.737 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:03:19.742 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:03:19.742 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:03:19.742 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:19.742 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:19.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:19.743 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:03:19.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:19.744 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:03:19.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:19.745 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:03:19.746 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:03:19.746 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:19.746 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:19.746 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:19.747 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:03:19.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:19.747 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:03:19.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:19.749 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:03:19.749 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:03:19.750 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:19.750 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:19.750 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:19.750 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:03:19.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:19.751 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:03:19.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:03:19.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:03:19.755 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:03:19.755 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:03:19.755 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:19.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:19.760 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:03:20.239 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:03:20.284 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:03:20.285 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:03:20.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:03:20.286 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:03:20.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:20.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:20.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:03:20.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:03:20.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:03:20.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:03:20.288 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:03:20.288 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:03:20.710 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:03:20.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:20.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:20.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:20.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:21.182 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:03:21.653 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:03:21.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:21.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:21.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:21.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:22.126 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:03:22.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:22.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:22.381 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:22.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:22.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:22.382 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:22.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:22.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:22.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:22.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:22.383 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:22.383 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:22.383 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:03:27.389 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:27.389 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:27.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:27.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:27.389 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:27.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:27.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:27.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:27.397 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:27.397 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:27.397 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:03:27.401 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:03:27.401 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:03:27.401 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:27.402 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:27.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:27.402 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:03:27.403 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:27.403 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:03:27.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:27.405 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:03:27.405 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:03:27.405 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:27.405 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:27.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:27.406 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:03:27.406 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:27.406 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:03:27.406 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:27.408 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:03:27.408 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:03:27.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:27.408 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:27.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:27.408 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:03:27.408 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:27.408 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:03:27.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:27.411 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:03:27.412 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:03:27.412 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:03:27.412 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:27.417 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:03:27.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:03:27.935 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:03:27.936 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:03:27.937 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:03:27.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:03:27.943 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:27.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:27.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:03:27.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:03:27.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:03:27.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:03:27.945 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:03:27.945 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:03:28.367 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:03:28.414 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:28.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:28.415 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:28.415 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:28.840 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:03:29.313 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:03:29.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:29.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:29.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:29.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:29.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:03:30.256 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:03:30.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:30.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:30.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:30.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:30.729 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:03:30.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:30.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:30.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:30.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:30.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:30.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:30.754 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:30.754 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:30.754 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:30.754 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:03:30.754 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:30.754 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:30.754 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:30.754 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=722 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:30.754 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=722 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:30.754 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=722 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:30.754 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=722 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:30.754 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=722 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:30.755 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=722 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:35.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:35.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:35.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:35.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:35.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:35.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:35.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:35.768 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:35.768 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:35.768 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:35.768 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:03:35.771 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:03:35.771 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:03:35.772 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:35.772 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:35.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:35.772 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:03:35.773 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:35.773 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:03:35.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:35.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:03:35.775 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:03:35.775 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:35.775 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:35.775 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:35.776 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:03:35.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:35.776 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:03:35.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:35.777 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:03:35.777 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:03:35.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:35.778 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:35.778 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:35.778 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:03:35.778 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:35.778 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:03:35.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:35.780 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:03:35.781 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:03:35.781 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:03:35.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:35.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:35.786 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:03:36.264 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:03:36.310 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:03:36.313 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:03:36.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:03:36.315 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:03:36.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:36.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:36.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:03:36.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:03:36.326 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:03:36.326 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:03:36.326 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:03:36.326 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:03:36.736 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:03:36.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:36.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:36.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:36.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:37.208 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:03:37.681 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:03:37.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:37.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:37.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:37.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:38.153 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:03:38.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:38.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:38.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:38.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:38.417 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:38.417 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:38.419 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:38.419 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:38.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:38.419 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:38.419 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:38.419 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:38.419 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:03:38.419 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:43.424 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:43.424 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:43.424 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:43.424 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:43.424 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:43.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:43.432 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:43.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:43.433 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:43.433 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:43.433 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:03:43.437 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:03:43.437 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:03:43.437 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:43.437 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:43.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:43.438 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:03:43.438 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:43.438 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:03:43.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:43.442 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:03:43.442 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:03:43.442 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:43.442 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:43.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:43.443 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:03:43.443 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:43.443 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:03:43.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:43.446 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:03:43.447 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:03:43.447 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:43.447 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:43.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:43.447 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:03:43.447 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:43.447 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:03:43.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:43.452 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:03:43.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:03:43.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:03:43.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:03:43.452 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.453 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:03:43.453 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:03:43.453 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:03:43.454 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:43.458 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:03:43.936 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:03:43.987 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:03:43.989 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:03:43.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:03:43.990 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:03:43.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:43.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:43.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:03:43.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:03:43.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:03:43.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:03:43.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:03:43.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:03:44.408 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:03:44.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:44.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:44.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:44.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:44.880 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:03:45.353 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:03:45.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:45.459 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:45.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:45.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:45.825 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:03:46.297 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:03:46.460 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:46.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:46.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:46.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:46.768 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:03:47.241 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:03:47.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:47.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:47.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:47.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:47.714 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:03:47.733 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:47.733 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:47.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:47.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:47.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:47.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:47.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:47.743 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:47.743 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:47.743 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:03:47.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:47.743 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:47.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:47.744 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:47.744 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:47.744 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:47.744 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:47.744 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:47.744 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:52.749 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:52.749 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:52.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:52.749 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:52.749 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:52.749 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:52.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:52.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:52.758 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:52.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:03:52.758 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:03:52.761 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:03:52.761 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:03:52.762 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:52.762 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:52.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:52.763 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:03:52.763 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:03:52.763 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:03:52.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:52.764 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:03:52.764 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:03:52.764 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:52.764 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:52.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:52.765 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:03:52.765 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:03:52.765 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:03:52.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:52.767 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:03:52.767 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:03:52.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:52.767 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:03:52.767 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:52.767 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:03:52.767 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:03:52.767 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:03:52.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:03:52.770 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:03:52.770 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:03:52.770 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:03:52.775 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:03:53.253 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:03:53.298 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:03:53.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:03:53.302 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:03:53.306 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:03:53.314 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:53.314 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:53.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:03:53.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:03:53.315 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:03:53.315 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:03:53.316 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:03:53.316 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:03:53.725 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:03:53.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:53.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:53.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:53.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:54.196 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:03:54.669 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:03:54.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:54.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:54.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:54.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:55.142 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:03:55.614 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:03:55.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:55.774 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:55.774 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:55.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:56.085 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:03:56.559 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:03:56.775 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:56.776 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:56.776 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:56.776 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:57.031 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:03:57.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:03:57.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:03:57.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:03:57.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:03:57.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:03:57.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:03:57.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:03:57.290 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:03:57.290 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:03:57.290 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:03:57.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:03:57.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:03:57.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:03:57.290 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=976 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:57.290 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=976 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:57.290 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=976 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:57.290 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=976 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:57.290 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=976 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:03:57.290 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=976 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:02.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:02.297 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:02.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:02.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:02.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:02.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:02.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:02.306 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:02.306 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:02.306 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:02.306 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:02.312 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:02.313 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:02.313 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:02.314 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:02.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:02.314 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:02.315 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:02.315 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:02.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:02.318 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:02.318 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:02.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:02.319 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:02.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:02.319 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:02.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:02.319 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:02.319 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:02.322 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:02.323 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:02.323 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:02.323 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:02.323 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:02.323 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:02.323 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:02.323 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:02.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:02.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:02.328 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:02.328 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:02.328 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:02.333 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:02.808 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:02.855 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:02.857 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:02.859 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:02.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:03.280 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:04:03.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:03.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:03.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:03.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:03.754 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:04:04.226 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:04:04.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:04.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:04.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:04.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:04.698 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:04:04.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:04.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:04.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:04.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:04.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:04.874 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:04.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:04.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:04.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:04.875 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:04.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:09.882 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:09.882 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:09.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:09.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:09.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:09.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:09.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:09.889 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:09.889 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:09.889 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:09.889 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:09.892 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:09.892 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:09.893 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:09.893 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:09.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:09.893 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:09.894 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:09.894 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:09.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:09.895 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:09.895 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:09.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:09.895 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:09.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:09.896 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:09.896 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:09.896 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:09.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:09.898 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:09.898 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:09.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:09.898 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:09.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:09.898 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:09.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:09.898 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:09.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.901 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:09.901 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:09.901 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:09.902 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:09.906 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:10.384 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:10.430 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:10.432 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:10.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:10.434 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:10.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:04:10.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:04:10.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:04:10.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:10.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:10.856 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:04:10.905 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:10.905 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:10.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:10.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:11.332 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:04:11.803 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:04:11.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:11.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:11.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:11.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:12.279 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:04:12.751 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:04:12.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:12.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:12.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:12.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:13.225 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:04:13.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:13.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:13.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:13.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:13.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:13.496 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:13.496 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:13.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:13.496 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:13.496 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:13.496 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:13.496 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=774 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=774 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=774 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=774 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:13.496 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:18.499 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:18.499 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:18.500 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:18.500 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:18.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:18.500 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:18.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:18.503 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:18.503 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:18.503 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:18.503 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:18.504 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:18.504 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:18.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:18.504 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:18.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:18.504 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:18.504 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:18.504 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:18.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:18.505 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:18.505 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:18.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:18.505 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:18.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:18.505 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:18.505 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:18.505 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:18.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:18.506 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:18.506 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:18.506 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:18.506 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:18.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:18.507 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:18.507 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:18.507 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:18.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:18.508 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:18.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:18.508 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:18.508 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:18.508 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:18.508 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:18.508 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:18.509 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:18.509 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:18.509 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.509 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:18.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:18.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:18.513 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:18.992 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:19.029 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:19.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:19.032 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:19.034 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:19.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:04:19.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:04:19.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:04:19.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:19.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:19.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:19.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:19.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:19.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:19.063 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:19.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:19.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:19.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:19.065 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:19.065 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:19.065 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:19.065 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:24.071 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:24.071 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:24.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:24.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:24.071 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:24.071 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:24.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:24.078 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:24.078 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:24.078 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:24.078 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:24.082 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:24.082 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:24.082 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:24.082 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:24.083 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:24.083 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:24.083 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:24.083 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:24.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:24.085 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:24.085 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:24.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:24.086 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:24.086 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:24.086 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:24.086 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:24.086 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:24.086 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:24.088 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:24.088 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:24.088 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:24.088 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:24.088 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:24.088 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:24.088 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:24.088 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:24.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:24.093 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:24.093 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:24.093 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.093 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.098 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:24.575 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:24.629 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:24.631 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:24.634 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:24.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:24.658 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:04:24.658 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:04:24.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:04:24.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:24.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:25.047 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:04:25.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:25.097 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:25.097 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:25.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:25.523 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:04:25.994 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:04:26.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:26.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:26.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:26.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:26.470 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:04:26.942 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:04:27.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:27.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:27.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:27.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:27.417 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:04:27.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:27.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:27.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:27.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:27.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:27.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:27.691 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:27.691 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:27.691 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:27.691 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:27.691 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:27.691 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:27.691 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:32.703 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:32.703 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:32.703 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:32.703 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:32.703 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:32.703 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:32.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:32.710 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:32.710 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:32.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:32.711 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:32.713 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:32.713 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:32.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:32.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:32.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:32.715 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:32.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:32.715 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:32.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:32.716 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:32.717 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:32.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:32.717 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:32.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:32.717 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:32.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:32.717 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:32.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:32.719 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:32.719 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:32.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:32.719 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:32.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:32.720 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:32.720 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:32.720 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:32.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:32.723 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:32.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:32.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:32.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:32.723 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:32.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:32.724 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:32.724 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:32.724 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:32.725 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:32.729 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:33.207 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:33.248 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:33.249 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:33.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:33.251 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:33.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:04:33.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:04:33.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:04:33.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:33.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:33.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:33.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:33.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:33.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:33.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:33.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:33.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:33.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:33.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:33.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:33.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:33.293 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:33.293 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:33.293 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:33.294 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:33.294 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:33.294 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:33.294 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:33.294 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:38.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:38.297 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:38.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:38.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:38.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:38.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:38.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:38.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:38.304 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:38.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:38.305 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:38.308 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:38.308 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:38.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:38.309 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:38.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:38.310 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:38.310 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:38.310 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:38.311 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:38.312 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:38.312 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:38.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:38.313 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:38.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:38.313 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:38.314 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:38.314 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:38.314 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:38.315 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:38.315 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:38.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:38.315 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:38.315 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:38.315 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:38.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:38.315 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:38.316 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:38.318 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:38.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:38.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:38.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:38.318 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:38.319 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:38.319 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:38.319 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:38.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:38.324 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:38.802 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:38.841 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:38.842 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:38.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:38.843 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:38.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:38.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:38.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:38.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:38.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:38.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:38.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:38.850 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:38.850 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:38.850 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:38.850 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:38.850 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:43.857 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:43.857 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:43.857 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:43.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:43.857 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:43.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:43.864 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:43.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:43.865 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:43.865 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:43.865 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:43.867 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:43.867 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:43.868 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:43.868 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:43.868 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:43.868 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:43.869 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:43.869 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:43.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:43.870 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:43.870 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:43.870 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:43.870 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:43.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:43.870 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:43.870 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:43.870 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:43.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:43.872 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:43.872 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:43.872 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:43.872 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:43.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:43.872 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:43.872 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:43.872 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:43.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:43.874 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:43.874 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:43.874 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:43.874 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:43.874 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:43.875 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:43.875 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:43.875 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:43.880 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:44.358 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:44.395 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:44.396 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:44.397 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:44.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:44.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:44.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:44.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:44.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:44.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:44.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:44.410 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:44.410 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:44.410 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:44.411 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:44.411 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:44.411 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:44.411 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:44.411 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:44.411 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:44.411 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:44.411 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:49.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:49.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:49.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:49.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:49.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:49.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:49.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:49.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:49.424 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:49.424 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:49.424 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:49.428 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:49.428 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:49.429 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:49.429 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:49.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:49.430 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:49.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:49.430 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:49.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:49.432 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:49.432 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:49.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:49.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:49.433 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:49.433 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:49.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:49.433 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:49.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:49.435 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:49.435 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:49.435 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:49.435 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:49.435 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:49.436 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:49.436 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:49.436 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:49.436 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.439 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:49.439 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:49.439 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:49.439 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:49.444 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:49.921 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:49.961 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:49.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:49.964 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:49.965 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:49.976 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:49.977 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:49.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:49.977 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:49.979 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:49.979 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:49.979 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:49.979 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:49.979 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:49.979 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:49.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:49.979 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:49.979 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:49.979 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:49.979 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:49.979 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:49.979 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:54.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:54.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:54.983 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:54.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:54.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:54.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:54.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:54.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:54.988 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:54.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:04:54.988 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:04:54.991 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:04:54.991 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:04:54.991 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:54.991 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:54.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:54.992 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:04:54.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:04:54.992 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:04:54.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:54.993 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:04:54.993 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:04:54.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:54.994 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:54.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:54.994 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:04:54.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:04:54.994 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:04:54.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:54.996 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:04:54.996 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:04:54.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:54.996 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:04:54.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:54.996 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:04:54.997 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:04:54.997 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:04:54.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:04:54.999 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:04:54.999 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:04:54.999 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:04:54.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:04:55.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:04:55.004 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:04:55.482 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:04:55.520 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:04:55.521 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:04:55.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:04:55.522 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:04:55.527 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:04:55.527 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:04:55.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:04:55.527 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:04:55.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:04:55.529 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:04:55.529 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:04:55.529 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:04:55.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:04:55.529 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:04:55.529 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:04:55.529 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:55.529 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:55.529 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:55.529 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:55.529 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:55.529 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:04:55.529 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=114 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:00.535 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:00.535 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:00.535 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:00.535 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:00.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:00.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:00.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:00.544 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:00.545 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:00.545 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:00.545 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:00.548 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:00.548 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:00.549 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:00.549 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:00.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:00.550 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:00.550 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:00.550 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:00.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:00.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:00.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:00.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:00.552 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:00.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:00.552 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:00.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:00.552 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:00.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:00.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:00.555 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:00.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:00.555 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:00.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:00.555 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:00.555 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:00.555 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:00.555 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:00.559 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:00.559 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:00.559 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:00.560 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:00.563 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:01.042 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:01.084 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:01.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:01.086 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:01.086 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:01.513 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:05:01.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:01.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:01.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:01.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:01.984 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:05:02.460 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:05:02.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:02.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:02.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:02.564 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:02.932 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:05:03.407 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:05:03.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:03.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:03.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:03.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:03.879 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:05:04.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:04.104 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:04.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:05:04.105 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:05:04.105 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:05:04.105 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:05:04.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:05:04.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:05:04.354 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:05:04.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:04.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:04.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:04.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:04.826 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:05:05.297 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:05:05.568 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:05.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:05.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:05.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:05.770 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:05:06.243 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:05:06.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:06.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:06.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:06.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:06.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:06.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:06.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:06.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:06.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:06.376 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:06.376 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:06.376 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:06.376 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:06.376 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:11.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:11.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:11.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:11.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:11.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:11.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:11.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:11.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:11.396 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:11.396 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:11.396 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:11.398 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:11.399 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:11.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:11.399 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:11.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:11.399 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:11.399 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:11.399 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:11.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:11.401 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:11.401 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:11.401 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:11.401 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:11.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:11.401 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:11.401 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:11.401 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:11.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:11.402 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:11.402 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:11.402 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:11.402 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:11.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:11.402 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:11.403 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:11.403 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:11.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:11.404 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:11.404 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:11.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:11.405 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:11.405 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:11.405 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:11.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:11.409 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:11.887 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:11.930 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:11.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:11.932 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:11.934 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:11.955 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:11.955 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:11.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:05:11.974 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:11.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:11.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:11.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:11.978 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:11.978 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:11.978 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:11.978 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:11.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:11.978 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:11.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:11.978 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:11.978 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:11.978 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:11.978 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:11.978 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:11.978 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:16.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:16.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:16.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:16.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:16.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:16.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:16.985 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:16.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:16.986 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:16.986 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:16.986 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:16.988 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:16.989 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:16.989 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:16.989 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:16.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:16.990 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:16.990 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:16.990 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:16.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:16.991 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:16.991 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:16.991 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:16.991 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:16.991 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:16.991 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:16.992 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:16.992 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:16.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:16.993 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:16.994 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:16.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:16.994 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:16.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:16.994 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:16.994 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:16.994 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:16.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:16.997 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:16.997 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:16.997 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:16.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:17.002 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:17.479 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:17.521 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:17.523 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:17.524 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:17.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:17.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:17.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:17.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:05:17.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:17.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:17.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:17.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:17.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:17.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:17.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:17.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:17.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:17.565 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:17.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:17.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:17.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:17.566 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:17.566 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:17.566 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:17.566 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:17.566 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:17.566 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:22.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:22.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:22.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:22.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:22.569 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:22.569 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:22.575 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:22.576 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:22.576 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:22.576 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:22.577 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:22.581 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:22.581 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:22.581 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:22.581 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:22.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:22.581 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:22.581 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:22.581 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:22.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:22.584 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:22.585 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:22.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:22.585 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:22.585 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:22.585 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:22.585 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:22.585 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:22.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:22.587 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:22.588 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:22.588 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:22.588 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:22.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:22.588 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:22.588 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:22.588 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:22.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:22.591 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:22.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:22.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:22.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:22.591 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:22.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:22.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:22.592 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:22.592 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:22.592 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.592 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:22.597 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:23.075 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:23.121 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:23.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:23.122 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:23.123 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:23.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:23.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:23.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:05:23.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:23.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:23.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:23.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:23.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:23.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:23.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:23.170 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:23.170 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:23.170 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:23.170 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:23.170 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:23.170 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:23.170 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:23.170 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:23.170 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:23.170 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:23.170 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:23.170 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:23.170 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:23.170 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.172 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:28.172 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:28.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:28.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:28.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:28.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:28.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:28.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:28.181 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:28.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:28.182 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:28.186 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:28.186 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:28.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:28.186 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:28.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:28.187 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:28.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:28.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:28.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:28.191 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:28.191 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:28.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:28.191 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:28.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:28.192 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:28.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:28.192 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:28.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:28.195 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:28.195 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:28.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:28.196 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:28.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:28.196 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:28.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:28.196 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:28.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:28.201 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:28.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:28.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:28.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:28.201 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.202 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:28.202 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:28.202 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:28.203 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.204 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:28.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.207 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:28.686 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:28.736 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:28.739 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:28.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.741 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:28.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:28.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:28.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:05:28.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:28.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:28.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:28.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:28.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:28.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:28.798 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:28.798 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:28.798 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:28.798 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:28.798 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:28.798 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:28.798 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:28.798 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:33.802 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:33.802 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:33.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:33.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:33.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:33.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:33.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:33.810 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:33.810 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:33.811 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:33.811 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:33.814 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:33.814 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:33.815 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:33.815 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:33.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:33.816 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:33.816 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:33.816 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:33.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:33.818 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:33.819 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:33.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:33.819 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:33.819 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:33.819 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:33.819 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:33.820 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:33.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:33.822 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:33.822 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:33.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:33.822 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:33.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:33.822 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:33.823 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:33.823 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:33.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:33.828 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:33.828 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:33.828 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:33.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:33.832 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:34.310 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:34.360 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:34.362 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:34.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:34.365 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:34.367 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 02:05:34.367 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 200
2026-03-01 02:05:34.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 02:05:34.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:34.784 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:05:34.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:34.996 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:34.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:34.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:34.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:35.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:35.260 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:05:35.732 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:05:35.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:36.004 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 02:05:36.004 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 0
2026-03-01 02:05:36.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 02:05:36.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:36.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:36.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:36.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:36.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:36.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:36.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:36.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:36.011 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:36.011 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:36.011 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:36.011 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:36.011 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:36.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:36.012 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:41.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:41.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:41.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:41.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:41.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:41.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:41.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:41.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:41.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:41.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:41.026 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:41.030 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:41.030 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:41.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:41.030 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:41.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:41.030 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:41.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:41.031 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:41.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:41.033 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:41.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:41.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:41.033 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:41.033 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:41.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:41.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:41.033 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:41.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:41.036 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:41.036 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:41.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:41.036 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:41.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:41.036 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:41.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:41.036 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:41.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:41.040 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:41.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:41.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:41.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:41.040 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:41.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:41.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:41.041 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:41.041 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.046 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:41.524 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:41.591 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:41.592 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:41.594 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:41.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:41.596 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 02:05:41.596 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 200
2026-03-01 02:05:41.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 02:05:41.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:41.998 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:05:42.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:42.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:42.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:42.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:42.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:42.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:42.472 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:05:42.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:42.832 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:42.946 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:05:43.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.233 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 02:05:43.234 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 0
2026-03-01 02:05:43.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 02:05:43.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:43.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:43.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:43.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:43.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:43.243 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:43.244 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:43.244 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:43.244 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:48.252 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:48.252 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:48.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:48.252 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:48.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:48.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:48.258 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:48.259 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:48.259 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:48.260 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:48.260 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:48.264 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:48.264 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:48.264 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:48.264 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:48.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:48.265 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:48.265 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:48.265 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:48.266 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:48.267 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:48.267 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:48.267 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:48.267 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:48.267 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:48.267 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:48.268 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:48.268 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:48.268 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:48.270 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:48.270 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:48.270 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:48.270 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:48.270 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:48.270 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:48.270 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:48.270 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:48.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:48.274 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:48.274 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:48.274 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:48.274 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.275 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:48.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:48.278 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:48.757 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:48.795 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:48.796 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:48.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:48.798 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:48.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:48.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:48.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:05:48.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:48.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:48.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:48.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:48.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:48.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:48.844 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:48.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:48.844 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:48.844 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:48.844 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:48.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:48.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:53.850 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:53.850 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:53.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:53.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:53.850 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:53.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:53.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:53.861 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:53.861 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:53.862 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:53.862 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:53.868 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:53.868 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:53.869 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:53.869 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:53.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:53.870 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:53.871 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:53.871 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:53.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:53.873 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:53.873 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:53.874 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:53.874 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:53.874 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:53.875 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:53.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:53.875 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:53.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:53.877 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:53.878 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:53.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:53.878 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:53.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:53.878 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:53.878 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:53.878 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:53.878 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:53.885 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:53.885 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:53.885 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:53.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:53.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:53.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:53.890 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:54.369 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:54.410 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:54.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:54.413 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:54.414 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:54.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:54.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:05:54.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:05:54.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:54.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:54.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:54.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:54.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:54.454 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:54.458 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:54.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:54.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:54.459 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:54.459 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:05:54.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:54.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:54.459 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:05:59.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:05:59.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:05:59.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:59.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:59.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:59.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:59.464 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:05:59.464 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:59.464 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:59.465 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:05:59.465 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:05:59.465 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:05:59.466 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:05:59.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:59.466 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:59.466 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:05:59.466 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:05:59.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:05:59.466 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:05:59.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:05:59.467 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:05:59.467 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:05:59.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:59.467 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:59.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:05:59.467 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:05:59.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:05:59.467 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:05:59.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:05:59.468 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:05:59.468 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:05:59.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:59.468 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:05:59.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:05:59.468 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:05:59.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:05:59.468 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:05:59.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:05:59.471 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:05:59.471 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:05:59.471 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:05:59.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:05:59.954 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:05:59.984 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:05:59.984 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:05:59.985 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:05:59.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:05:59.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:05:59.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:00.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:00.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:00.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:00.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:00.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:00.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:00.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:00.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:00.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:00.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:00.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:00.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:00.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:00.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:00.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:00.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:00.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:00.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:00.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:00.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:00.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:00.134 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:00.134 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:00.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:00.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:00.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:00.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:00.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:00.426 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:06:00.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:00.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:00.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:00.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:00.897 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:06:01.371 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:06:01.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:01.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:01.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:01.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:01.843 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:06:02.316 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:06:02.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:02.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:02.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:02.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:02.786 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:06:03.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:03.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.144 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:03.144 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:03.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:03.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:03.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:03.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:03.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:03.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:03.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:03.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:03.215 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:03.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:03.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:03.257 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:06:03.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.260 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:03.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:03.276 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:03.276 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:03.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:03.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.277 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:03.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:03.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:03.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:03.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:03.305 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:03.305 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:03.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:03.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:03.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:03.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:03.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:03.728 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:06:04.201 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:06:04.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:04.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:04.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:04.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:04.674 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:06:05.146 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:06:05.620 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:06:06.093 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:06:06.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:06.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:06.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:06.312 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:06.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:06.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:06.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:06.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:06.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:06.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:06.331 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:06.331 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:06.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:06.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:06.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:06.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:06.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:06.563 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:06:07.037 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:06:07.510 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:06:07.982 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:06:08.453 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:06:08.927 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:06:09.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:09.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:09.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:09.399 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:06:09.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:09.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:09.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:09.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:09.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:09.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:09.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:09.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:09.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:09.455 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:09.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:09.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:09.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:09.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:09.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:09.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:09.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:09.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:09.526 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:09.526 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:09.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:09.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:09.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:09.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:09.871 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:06:10.342 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:06:10.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:10.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:10.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:10.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:10.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:10.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:10.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:10.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:10.567 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:10.567 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:10.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:10.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:10.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:10.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:10.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:10.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:10.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:10.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:10.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:10.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:10.667 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:10.667 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:10.667 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:10.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:10.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:10.718 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:10.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:10.815 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:06:11.288 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:06:11.760 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:06:12.231 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:06:12.705 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:06:13.177 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:06:13.649 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:06:13.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:13.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:13.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:13.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:13.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:13.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:13.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:13.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:13.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:13.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:13.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:13.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:13.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:13.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:13.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:13.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:13.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:13.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:13.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:13.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:13.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:13.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:13.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:13.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:13.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:13.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:13.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:13.877 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:13.877 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:13.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:13.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:13.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:13.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:13.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:14.120 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:06:14.594 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:06:15.066 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:06:15.539 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:06:16.009 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:06:16.480 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:06:16.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:16.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:16.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:16.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:16.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:16.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:16.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:16.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:16.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:16.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:16.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:16.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:16.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:16.953 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:06:16.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:16.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:16.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:16.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:17.426 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:06:17.898 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:06:18.369 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:06:18.840 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:06:19.313 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:06:19.786 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:06:19.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:19.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:19.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:19.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:19.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:19.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:19.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:19.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:19.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:19.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:19.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:19.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:20.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:20.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:20.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:20.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:20.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:20.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:20.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:20.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:20.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:20.134 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:20.134 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:20.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:20.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:20.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:20.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:20.136 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:20.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:20.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:20.169 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:20.169 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:20.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:20.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:20.258 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:06:20.729 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:06:21.203 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:06:21.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:21.378 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:21.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:21.380 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:21.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:21.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:21.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:21.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:21.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:21.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:21.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:21.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:21.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:21.444 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:21.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:21.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:21.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:21.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:21.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:21.666 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:21.666 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:21.675 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:06:21.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:21.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:21.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:21.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:21.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:21.681 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:21.681 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:21.681 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:21.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:21.730 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:21.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:21.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:21.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:22.147 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:06:22.618 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:06:23.089 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:06:23.560 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:06:24.030 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:06:24.501 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:06:24.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:24.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:24.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:24.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:24.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:24.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:24.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:24.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:24.754 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:24.755 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:24.755 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:24.755 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:24.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:24.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:24.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:24.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:24.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:24.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:24.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:24.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:24.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:24.971 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:06:24.980 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:24.980 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:24.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:24.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:24.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:24.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:24.982 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:24.982 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:25.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:25.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:25.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:25.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:25.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:25.443 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:06:25.913 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:06:26.384 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:06:26.858 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:06:27.330 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:06:27.802 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:06:28.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:28.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:28.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:28.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:28.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:28.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:28.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:28.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:28.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:28.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:28.047 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:28.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:28.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:28.091 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:28.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:28.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:28.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:28.273 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:06:28.744 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:06:29.218 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:06:29.690 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:06:30.162 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:06:30.633 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:06:31.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:31.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.098 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:31.098 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:31.106 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:06:31.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:31.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:31.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:31.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:31.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:31.113 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:31.113 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:31.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:31.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:31.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:31.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:31.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:31.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:31.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:31.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:31.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:31.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:31.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:31.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:31.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:31.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:31.393 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:31.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:31.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:31.579 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:06:32.051 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:06:32.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:32.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:32.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:32.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:32.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:32.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:32.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.115 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:32.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:32.116 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:32.116 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:32.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:32.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:32.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:32.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:32.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:32.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:32.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:32.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:32.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:32.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.229 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:32.229 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:32.229 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:32.229 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:32.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:32.233 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:32.233 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:32.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:32.521 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:06:32.992 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:06:33.466 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:06:33.938 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:06:34.410 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:06:34.881 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:06:35.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:35.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:35.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:35.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:35.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:35.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:35.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.257 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:35.257 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:35.257 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:35.257 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:35.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:35.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:35.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:35.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.352 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:06:35.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:35.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:35.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:35.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:35.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:35.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:35.526 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.526 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:35.526 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:35.526 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:35.526 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:35.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:35.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:35.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:35.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:35.823 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:06:36.296 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:06:36.769 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:06:37.241 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:06:37.714 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:06:38.187 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:06:38.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:38.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:38.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:38.540 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:38.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:38.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:38.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:38.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:38.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:38.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:38.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:38.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:38.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:38.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:38.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:38.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:38.618 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:38.658 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:06:39.130 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:06:39.603 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:06:40.075 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:06:40.548 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:06:41.021 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:06:41.493 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:06:41.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:41.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:41.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:41.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:41.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:41.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:41.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:41.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:41.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:41.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:41.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:41.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:41.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:41.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:41.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:41.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:41.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:41.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:41.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:41.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.908 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:41.908 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:41.908 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:41.908 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:41.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:41.912 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:41.912 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:41.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:41.965 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:06:42.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:42.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:42.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:42.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:42.436 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:06:42.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:42.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:42.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:42.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:42.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:06:42.443 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:06:42.443 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:06:42.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:06:42.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:06:42.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:06:42.444 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:06:47.450 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:06:47.450 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:06:47.450 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:06:47.450 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:06:47.450 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:06:47.450 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:06:47.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:06:47.462 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:06:47.462 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:47.462 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:06:47.462 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:06:47.464 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:06:47.464 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:06:47.465 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:06:47.465 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:47.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:06:47.465 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:06:47.465 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:06:47.465 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:06:47.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:47.466 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:06:47.466 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:06:47.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:06:47.466 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:47.466 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:06:47.466 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:06:47.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:06:47.466 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:06:47.466 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:47.467 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:06:47.468 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:06:47.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:06:47.468 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:47.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:06:47.468 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:06:47.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:06:47.468 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:06:47.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:47.469 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:06:47.469 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:06:47.470 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:06:47.470 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:06:47.470 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:47.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:47.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:06:47.953 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:06:47.993 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:06:47.994 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:06:47.996 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:06:47.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:48.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.025 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:48.025 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:48.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.056 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.114 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:48.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.134 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:48.134 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:48.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.276 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:48.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:48.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:48.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.425 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:06:48.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:48.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:48.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:48.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:48.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.599 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.599 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:48.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:48.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:48.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:48.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:48.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:48.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:48.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:48.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:48.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:48.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:48.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:48.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:48.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:06:48.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:06:48.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:06:48.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:06:48.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:06:48.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:06:48.756 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:06:48.756 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=278 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:06:53.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:06:53.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:06:53.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:06:53.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:06:53.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:06:53.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:06:53.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:06:53.787 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:06:53.787 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:53.788 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:06:53.788 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:06:53.789 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:06:53.789 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:06:53.790 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:06:53.790 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:53.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:06:53.790 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:06:53.790 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:06:53.790 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:06:53.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:53.793 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:06:53.793 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:06:53.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:06:53.793 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:53.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:06:53.793 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:06:53.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:06:53.793 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:06:53.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:53.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:06:53.796 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:06:53.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:06:53.796 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:06:53.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:06:53.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:06:53.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:06:53.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:06:53.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:06:53.800 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:06:53.800 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:06:53.800 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:06:53.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:06:53.804 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:06:54.284 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:06:54.327 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:06:54.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:54.329 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:06:54.332 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:06:54.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:54.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:54.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:54.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:54.361 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:54.361 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:54.361 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:54.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:54.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:54.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:54.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:54.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:54.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:54.754 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:06:54.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:54.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:54.765 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:54.765 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:54.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:54.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:54.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:54.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:54.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:54.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:54.786 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:54.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:54.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:54.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:54.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:54.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:54.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:54.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:54.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:54.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:54.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:55.227 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:06:55.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:55.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.490 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:55.490 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:55.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:55.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:55.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:55.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:55.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:55.500 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:55.500 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:55.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:55.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:55.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:55.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:55.667 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:55.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:55.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:55.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:55.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:06:55.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:55.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:55.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:06:55.689 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:06:55.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:55.696 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:06:55.696 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:06:55.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:55.698 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:06:55.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:55.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:55.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:55.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:56.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:06:56.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:06:56.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:06:56.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:06:56.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:06:56.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:06:56.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:06:56.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:06:56.102 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:06:56.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:06:56.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:06:56.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:06:56.102 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:06:56.102 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:06:56.102 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:07:01.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:01.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:01.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:01.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:01.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:01.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:01.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:01.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:01.123 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:01.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:01.123 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:07:01.124 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:07:01.124 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:07:01.124 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:01.124 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:01.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:01.124 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:07:01.124 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:01.124 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:07:01.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:01.125 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:07:01.125 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:07:01.125 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:01.125 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:01.125 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:01.125 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:07:01.125 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:01.125 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:07:01.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:01.126 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:07:01.126 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:07:01.126 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:01.126 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:01.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:01.126 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:07:01.127 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:01.127 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:07:01.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:01.128 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:07:01.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:07:01.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:07:01.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:07:01.129 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:07:01.129 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:07:01.129 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:01.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:01.133 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:07:01.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:07:01.654 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:07:01.657 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:07:01.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:01.659 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:07:01.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:01.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:01.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:01.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:01.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:01.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:01.692 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:01.692 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:01.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:01.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:01.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:01.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:01.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:01.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:01.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:01.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:01.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:01.900 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:01.900 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:01.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:01.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:01.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:01.902 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:01.902 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:01.902 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:01.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:01.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:01.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:01.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:01.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.083 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:07:02.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:02.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:02.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:02.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:02.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:02.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:02.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:02.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:02.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:02.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:02.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:02.248 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:02.248 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:02.248 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:02.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:02.272 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:02.273 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:02.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:02.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:02.549 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:02.555 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:07:02.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:02.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:02.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:02.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:02.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:02.569 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:02.569 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:02.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:02.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:02.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:02.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:02.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:02.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:02.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:02.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:02.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:02.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:02.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:02.958 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:02.958 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:02.958 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:02.958 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:02.958 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:07:02.959 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:02.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:07.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:07.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:07.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:07.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:07.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:07.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:07.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:07.970 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:07.970 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:07.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:07.971 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:07:07.974 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:07:07.974 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:07:07.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:07.974 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:07.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:07.974 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:07:07.975 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:07.975 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:07:07.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:07.978 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:07:07.979 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:07:07.979 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:07.979 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:07.979 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:07.979 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:07:07.979 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:07.979 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:07:07.979 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:07.983 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:07:07.983 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:07:07.983 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:07.983 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:07.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:07.983 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:07:07.983 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:07.983 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:07:07.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:07.988 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:07:07.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:07:07.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:07:07.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:07:07.988 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:07:07.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:07:07.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:07:07.989 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:07:07.989 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:07.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:07.994 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:07:08.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:07:08.520 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:07:08.523 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:07:08.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:08.525 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:07:08.550 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:08.550 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:08.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:08.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:08.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:08.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:08.552 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:08.552 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:08.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:08.573 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:08.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:08.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:08.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:08.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:08.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:08.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:08.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:08.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:08.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:08.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:08.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:08.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:08.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:08.753 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:08.753 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:08.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:08.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:08.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:08.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:08.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:08.945 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:07:08.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:08.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:08.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:08.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:09.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:09.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:09.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:09.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:09.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:09.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:09.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:09.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:09.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:09.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:09.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:09.131 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:09.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:09.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:09.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:09.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:09.418 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:07:09.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:09.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:09.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:09.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:09.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:09.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:09.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:09.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:09.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:09.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:09.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:09.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:09.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:09.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:09.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:09.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:09.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:09.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:09.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:09.821 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:09.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:09.821 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:07:09.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:09.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:09.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:09.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=396 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:07:09.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=396 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:07:09.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=396 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:07:09.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=396 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:07:09.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=396 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:07:09.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=396 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:07:14.827 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:14.827 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:14.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:14.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:14.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:14.827 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:14.834 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:14.835 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:14.835 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:14.836 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:14.836 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:07:14.838 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:07:14.838 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:07:14.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:14.838 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:14.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:14.839 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:07:14.839 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:14.839 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:07:14.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:14.841 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:07:14.841 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:07:14.841 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:14.841 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:14.841 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:14.841 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:07:14.841 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:14.841 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:07:14.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:14.843 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:07:14.843 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:07:14.843 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:14.843 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:14.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:14.843 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:07:14.844 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:14.844 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:07:14.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:14.845 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:07:14.846 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:07:14.846 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:07:14.846 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:14.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:14.851 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:07:15.329 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:07:15.368 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:07:15.369 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:07:15.371 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:07:15.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:15.383 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:15.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:15.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:15.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:15.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:15.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:15.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:15.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:15.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:15.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:15.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:15.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:15.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:15.801 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:07:15.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:15.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:15.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:15.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:16.272 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:07:16.743 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:07:16.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:16.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:16.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:16.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:17.214 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:07:17.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:17.262 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:17.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:17.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:17.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:17.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:17.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:17.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:17.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:17.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:17.282 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:17.282 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:17.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:17.314 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:17.314 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:17.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:17.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:17.685 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:07:17.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:17.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:17.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:17.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:18.159 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:07:18.631 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:07:18.851 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:18.851 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:18.852 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:18.852 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:19.102 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:07:19.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:19.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:19.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:19.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:19.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:19.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:19.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:19.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:19.455 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:19.455 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:19.455 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:19.455 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:19.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:19.482 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:19.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:19.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:19.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:19.573 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:07:19.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:19.852 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:19.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:19.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:20.046 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:07:20.518 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:07:20.991 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:07:21.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:21.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:21.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:21.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:21.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:21.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:21.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:21.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:21.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:21.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:21.052 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:21.052 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:21.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:21.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:21.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:21.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:21.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:21.462 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:07:21.935 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:07:22.407 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:07:22.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:22.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:22.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:22.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:22.879 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:07:22.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:22.882 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:22.882 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:22.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:27.888 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:27.888 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:27.888 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:27.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:27.888 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:27.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:27.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:27.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:27.896 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:27.896 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:27.896 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:07:27.900 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:07:27.901 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:07:27.901 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:27.901 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:27.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:27.902 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:07:27.903 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:27.903 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:07:27.903 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:27.905 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:07:27.906 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:07:27.906 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:27.906 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:27.906 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:27.906 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:07:27.907 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:27.907 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:07:27.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:27.909 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:07:27.909 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:07:27.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:27.909 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:27.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:27.909 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:07:27.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:27.909 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:07:27.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:07:27.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:07:27.914 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:07:27.914 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:07:27.914 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:27.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:27.919 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:07:28.397 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:07:28.438 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:07:28.441 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:07:28.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:28.442 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:07:28.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:28.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:28.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:28.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:28.467 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:28.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:28.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:28.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:28.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:28.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:28.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:28.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:28.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:28.868 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:07:28.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:28.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:28.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:28.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:29.340 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:07:29.813 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:07:29.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:29.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:29.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:29.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:30.286 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:07:30.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:30.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:30.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:30.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:30.348 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:30.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:30.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:30.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:30.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:30.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:30.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:30.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:30.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:30.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:30.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:30.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:30.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:30.758 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:07:30.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:30.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:30.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:30.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:31.231 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:07:31.702 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:07:31.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:31.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:31.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:31.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:32.175 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:07:32.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:32.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:32.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:32.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:32.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:32.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:32.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:32.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:32.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:32.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:32.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:32.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:32.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:32.552 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:32.552 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:32.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:32.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:32.647 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:07:32.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:32.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:32.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:32.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:33.119 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:07:33.590 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:07:34.061 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:07:34.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:34.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:34.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:34.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:34.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:34.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:34.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:34.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:34.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:34.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:34.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:34.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:34.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:34.161 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:34.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:34.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:34.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:34.532 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:07:35.005 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:07:35.477 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:07:35.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:35.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:35.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:35.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:35.949 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:07:35.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:35.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:35.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:35.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:35.956 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:35.956 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:35.956 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:35.956 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:35.956 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:07:35.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:35.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:40.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:07:40.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:07:40.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:40.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:40.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:40.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:40.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:07:40.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:40.971 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:40.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:07:40.972 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:07:40.976 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:07:40.976 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:07:40.977 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:40.977 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:40.977 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:07:40.977 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:07:40.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:07:40.978 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:07:40.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:40.980 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:07:40.980 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:07:40.980 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:40.980 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:40.980 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:07:40.980 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:07:40.980 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:07:40.980 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:07:40.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:40.983 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:07:40.983 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:07:40.983 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:40.983 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:07:40.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:07:40.983 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:07:40.983 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:07:40.983 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:07:40.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:07:40.987 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:07:40.987 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:07:40.987 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:07:40.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:07:40.992 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:07:41.469 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:07:41.511 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:07:41.514 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:07:41.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:41.517 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:07:41.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:41.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:41.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:41.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:41.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:41.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:41.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:41.546 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:41.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:41.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:41.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:41.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:41.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:41.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:41.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:41.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:41.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:41.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:41.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:41.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:41.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:41.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:41.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:41.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:41.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:41.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:41.806 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:41.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:41.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:41.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:41.942 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:07:41.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:41.990 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:41.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:41.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:42.413 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:07:42.886 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:07:42.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:42.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:42.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:42.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:43.359 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:07:43.831 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:07:43.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:43.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:43.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:43.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:43.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:43.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:43.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:43.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:43.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:43.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:43.898 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:43.898 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:43.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:43.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:43.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:43.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:43.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:43.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:43.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:43.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:43.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:44.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:44.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:44.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:44.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:44.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:44.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:44.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:44.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:44.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:44.113 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:44.113 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:44.113 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:44.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:44.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:44.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:44.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:44.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:44.302 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:07:44.776 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:07:44.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:44.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:44.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:44.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:45.248 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:07:45.719 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:07:45.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:07:45.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:07:45.996 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:07:45.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:07:46.190 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:07:46.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:46.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:46.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:46.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:46.298 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:46.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:46.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:46.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:46.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:46.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:46.301 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:46.301 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:46.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:46.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:46.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:46.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:46.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:46.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:46.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:46.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:46.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:46.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:46.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:46.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:46.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:46.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:46.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:46.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:46.660 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:07:46.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:46.668 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:46.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:46.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:46.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:47.131 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:07:47.602 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:07:48.073 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:07:48.547 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:07:48.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:48.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:48.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:48.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:48.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:48.943 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:48.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:48.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:48.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:48.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:48.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:48.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:48.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:48.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:48.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:48.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:48.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:49.019 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:07:49.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:49.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:49.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:49.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:49.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:49.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:49.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:49.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:49.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:49.303 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:49.303 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:49.303 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:49.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:49.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:49.354 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:49.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:49.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:49.490 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:07:49.961 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:07:50.433 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:07:50.905 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:07:51.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:51.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:51.329 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:51.329 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:51.345 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:51.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:51.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:51.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:51.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:51.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:51.347 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:51.347 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:51.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:51.377 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:07:51.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:51.382 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:51.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:51.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:51.850 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:07:52.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:52.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:52.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:52.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:52.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:52.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:52.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:52.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:52.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:52.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:52.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:52.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:52.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:52.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:52.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:52.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:52.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:52.320 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:07:52.791 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:07:53.265 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:07:53.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:53.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:53.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:53.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:53.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:53.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:53.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:53.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:53.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:53.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:53.723 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:53.723 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:53.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:53.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:53.730 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:53.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:53.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:53.736 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:07:54.208 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:07:54.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:54.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:54.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:54.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:54.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:54.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:54.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:54.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:54.386 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:54.386 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:54.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:54.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:54.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:54.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:54.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:54.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:54.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:54.681 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:07:55.154 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:07:55.626 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:07:56.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:56.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:56.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:56.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:56.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:56.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:56.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:56.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:56.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:56.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:56.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:56.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:56.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:56.095 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:56.095 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:56.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:56.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:56.097 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:07:56.568 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:07:56.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:56.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:56.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:56.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:56.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:56.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:56.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:56.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:56.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:56.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:56.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:56.674 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:56.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:56.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:56.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:56.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:56.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:57.041 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:07:57.514 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:07:57.986 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:07:58.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:58.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:58.380 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:58.381 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:58.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:58.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:58.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:58.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:58.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:58.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:58.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:58.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:58.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:58.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:58.403 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:58.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:58.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:58.457 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:07:58.928 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:07:59.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:59.012 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:59.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:59.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:59.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:07:59.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:07:59.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:07:59.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:59.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:59.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:59.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:07:59.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:07:59.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:07:59.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:07:59.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:07:59.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:59.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:07:59.401 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:07:59.873 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:08:00.345 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:08:00.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:00.739 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:00.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:00.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:00.750 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:00.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:00.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:00.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:00.753 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:00.753 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:00.753 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:00.753 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:08:00.753 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:00.753 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:00.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:00.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4272 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:00.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4272 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:00.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4272 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:00.753 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4272 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:00.754 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4272 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:00.754 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4272 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:05.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:05.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:05.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:05.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:05.757 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:05.757 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:05.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:05.763 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:05.763 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:05.764 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:05.764 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:08:05.766 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:08:05.767 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:08:05.767 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:05.767 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:05.767 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:05.768 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:08:05.768 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:05.768 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:08:05.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:05.769 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:08:05.770 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:08:05.770 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:05.770 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:05.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:05.770 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:08:05.770 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:05.770 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:08:05.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:05.772 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:08:05.772 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:08:05.772 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:05.772 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:05.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:05.772 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:08:05.772 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:05.772 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:08:05.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:05.775 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:08:05.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:08:05.775 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:08:05.775 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:08:05.775 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:08:05.775 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:08:05.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:08:05.776 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:08:05.776 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:08:05.776 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:05.781 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:08:06.259 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:08:06.300 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:08:06.302 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:08:06.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.305 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:08:06.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.329 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:06.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.335 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:06.335 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:06.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.364 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.439 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.439 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:06.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.457 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.457 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:06.457 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:06.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:06.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:06.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:06.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.727 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:08:06.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:06.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.752 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.752 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.752 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:06.752 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:06.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:06.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:06.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:06.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:06.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:06.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:06.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:06.873 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.874 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:06.874 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:06.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:06.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:06.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:06.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:06.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:07.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:07.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:07.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:07.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:07.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:07.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:07.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:07.138 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:07.138 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:07.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:07.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:07.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:07.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.199 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:08:07.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:07.355 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:07.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:07.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:07.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:07.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:07.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.375 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:07.375 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:07.375 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:07.375 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:07.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:07.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:07.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:07.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:07.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:07.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:07.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:07.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:07.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:07.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:07.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:07.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:07.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:07.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:07.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:07.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:07.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.581 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.671 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:08:07.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:07.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:07.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:07.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:07.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:07.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:07.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:07.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:07.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:07.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:07.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:07.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:07.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:07.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:07.773 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:08:12.776 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:12.776 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:12.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:12.776 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:12.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:12.776 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:12.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:12.784 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:12.785 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:12.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:12.785 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:08:12.787 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:08:12.788 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:08:12.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:12.788 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:12.788 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:12.788 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:08:12.789 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:12.789 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:08:12.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:12.790 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:08:12.790 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:08:12.790 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:12.790 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:12.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:12.790 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:08:12.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:12.791 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:08:12.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:12.792 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:08:12.792 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:08:12.792 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:12.792 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:12.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:12.792 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:08:12.792 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:12.792 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:08:12.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:08:12.795 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:08:12.795 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:08:12.795 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:12.800 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:08:13.279 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:08:13.317 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:08:13.319 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:08:13.321 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:08:13.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:13.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:13.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:13.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:13.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:13.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:13.349 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:13.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:13.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:13.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:13.382 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:13.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:13.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:13.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:13.751 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:08:13.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:13.797 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:13.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:13.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:14.222 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:08:14.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:14.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:14.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:14.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:14.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:14.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:14.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:14.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:14.259 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:14.259 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:14.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:14.265 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:14.265 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:14.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.693 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:08:14.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:14.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:14.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:14.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:14.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:14.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:14.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:14.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:14.742 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:14.742 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:14.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:14.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:14.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:14.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:14.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:14.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:14.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:14.798 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:15.164 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:08:15.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:15.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:15.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:15.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:15.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:15.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:15.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:15.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:15.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:15.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:15.461 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:15.461 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:15.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:15.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:15.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:15.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:15.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:15.637 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:08:15.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:15.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:15.799 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:15.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:15.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:15.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:15.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:15.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:15.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:15.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:15.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:15.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:15.942 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:15.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:15.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:15.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:15.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:15.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:15.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:15.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:15.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:16.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:16.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:16.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:16.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:16.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:16.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:16.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:16.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:16.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:16.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:16.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:16.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:16.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.109 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:08:16.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:16.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.551 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:16.551 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:16.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:16.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:16.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:16.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:16.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:16.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:16.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:16.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:16.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:16.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:16.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.580 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:08:16.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:16.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:16.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:16.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:16.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:16.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:16.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:16.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:16.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:16.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:16.996 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:16.996 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:16.996 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:16.996 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:16.996 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:17.052 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:08:17.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:17.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:17.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:17.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:17.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:17.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:17.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:17.447 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:17.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:17.458 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:17.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:17.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:17.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:17.461 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:17.461 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:17.461 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:17.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:17.461 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:17.461 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:17.461 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:08:17.462 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1009 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:17.462 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1009 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:17.462 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1009 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:17.462 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1009 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:17.462 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1009 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:17.462 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1009 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:17.462 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1009 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:22.464 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:22.464 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:22.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:22.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:22.464 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:22.464 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:22.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:22.477 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:22.477 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:22.477 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:22.477 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:08:22.480 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:08:22.480 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:08:22.480 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:22.480 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:22.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:22.480 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:08:22.481 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:22.481 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:08:22.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:22.482 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:08:22.482 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:08:22.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:22.482 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:22.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:22.482 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:08:22.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:22.483 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:08:22.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:22.484 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:08:22.484 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:08:22.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:22.484 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:22.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:22.484 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:08:22.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:22.485 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:08:22.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.487 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:08:22.487 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:08:22.488 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:08:22.488 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:22.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:22.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:22.492 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:08:22.970 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:08:23.018 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:08:23.020 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:08:23.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.022 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:08:23.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:23.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.050 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:23.050 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:23.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.074 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:23.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.152 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.152 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.152 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:23.152 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:23.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.217 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.217 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:23.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.286 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.286 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.286 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:23.286 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:23.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.392 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.392 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:23.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:23.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:23.437 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:08:23.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.447 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.447 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.490 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:23.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:23.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:23.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:23.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.525 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.525 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:23.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:23.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:23.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.586 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.667 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.667 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.681 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.681 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:23.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.682 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:23.682 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:23.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.727 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.727 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.908 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:08:23.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:23.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:23.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:23.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.923 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:23.923 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:23.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:23.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:23.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:23.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:23.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:24.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:24.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:24.066 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:24.066 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:24.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:24.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:24.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:24.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:24.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:24.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:24.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:24.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:24.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:24.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:24.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:24.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:24.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:24.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:24.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:24.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:24.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:24.304 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:24.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:24.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:24.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:24.307 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:24.307 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:24.307 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:24.307 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:24.307 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:24.307 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:24.307 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:08:29.310 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:29.310 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:29.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:29.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:29.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:29.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:29.324 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:29.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:29.324 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:29.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:29.325 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:08:29.326 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:08:29.327 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:08:29.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:29.327 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:29.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:29.327 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:08:29.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:29.327 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:08:29.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:29.328 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:08:29.329 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:08:29.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:29.329 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:29.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:29.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:08:29.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:29.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:08:29.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:29.330 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:08:29.330 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:08:29.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:29.330 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:29.330 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:29.330 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:08:29.330 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:29.330 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:08:29.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:29.332 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:08:29.333 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:08:29.333 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:08:29.333 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.333 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:29.337 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:08:29.815 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:08:29.858 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:08:29.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:29.862 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:08:29.863 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:08:29.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:29.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:29.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:29.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:29.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:29.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:29.895 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:29.895 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:29.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:29.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:29.914 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:29.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:29.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:30.287 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:08:30.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:30.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:30.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:30.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:30.758 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:08:30.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:30.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:30.781 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:30.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:30.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:30.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:30.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:30.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:30.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:30.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:30.801 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:30.801 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:30.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:30.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:30.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:30.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:30.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:31.231 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:08:31.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:31.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:31.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:31.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:31.704 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:08:31.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:31.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:31.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:31.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:31.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:31.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:31.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:31.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:31.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:31.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:31.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:31.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:31.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:31.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:31.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:31.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:31.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:32.176 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:08:32.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:32.350 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:32.351 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:32.351 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:32.648 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:08:32.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:32.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:32.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:32.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:32.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:32.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:32.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:32.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:32.967 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:32.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:32.967 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:32.967 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:32.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:32.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:32.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:32.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:32.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:33.121 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:08:33.351 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:33.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:33.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:33.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:33.593 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:08:33.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:33.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:33.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:33.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:33.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:33.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:33.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:33.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:33.925 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:33.925 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:33.925 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:33.925 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:33.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:33.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:33.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:33.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:33.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:34.065 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:08:34.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:34.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:34.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:34.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:34.536 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:08:34.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:34.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:34.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:34.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:34.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:34.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:34.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:34.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:34.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:34.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:34.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:34.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:34.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:34.633 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:34.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:34.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:34.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:35.007 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:08:35.481 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:08:35.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:35.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:35.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:35.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:35.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:35.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:35.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:35.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:35.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:35.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:35.539 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:35.539 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:35.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:35.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:35.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:35.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:35.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:35.953 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:08:36.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:36.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:36.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:36.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:36.425 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:08:36.437 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:36.437 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:36.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:36.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:36.439 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:36.439 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:36.439 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:36.439 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:36.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:36.480 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:36.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:36.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:36.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:36.896 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:08:37.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:37.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:37.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:37.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:37.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:37.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:37.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:37.367 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:08:42.374 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:42.374 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:42.374 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:42.374 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:42.374 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:42.374 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:42.382 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:42.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:42.383 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:42.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:42.383 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:08:42.385 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:08:42.386 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:08:42.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:42.386 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:42.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:42.387 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:08:42.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:42.387 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:08:42.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:42.388 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:08:42.388 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:08:42.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:42.388 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:42.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:42.388 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:08:42.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:42.389 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:08:42.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:42.390 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:08:42.390 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:08:42.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:42.390 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:42.390 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:42.391 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:08:42.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:42.391 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:08:42.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:42.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:08:42.394 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:08:42.394 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:08:42.394 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:42.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:42.398 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:08:42.877 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:08:42.907 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:08:42.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:42.908 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:08:42.908 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:08:42.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:42.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:42.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:42.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:42.924 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:42.924 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:42.925 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:42.925 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:42.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:42.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:42.982 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:42.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:43.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:43.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:43.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:43.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:43.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:43.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.120 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:43.120 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:43.120 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:43.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:43.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:43.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:43.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:43.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:43.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:43.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:43.350 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:08:43.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:43.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:43.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:43.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:43.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:43.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:43.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:43.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:43.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:43.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:43.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:43.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:43.404 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:43.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:43.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:43.578 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:43.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:43.597 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:43.597 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:43.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:43.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:43.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:43.598 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:43.598 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:43.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:43.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:43.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:43.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.820 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:08:43.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:43.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:43.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:43.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:43.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:43.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:43.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:43.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:43.989 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:43.989 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:43.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:43.989 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:43.989 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:43.989 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:43.989 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:08:48.994 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:48.994 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:48.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:48.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:48.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:48.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:49.002 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:49.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:49.003 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:49.003 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:49.003 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:08:49.005 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:08:49.006 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:08:49.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:49.006 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:49.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:49.006 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:08:49.006 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:49.006 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:08:49.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:49.009 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:08:49.009 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:08:49.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:49.009 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:49.009 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:49.009 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:08:49.009 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:49.009 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:08:49.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:49.013 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:08:49.013 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:08:49.013 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:49.013 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:49.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:49.013 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:08:49.014 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:49.014 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:08:49.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.018 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:08:49.018 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:08:49.018 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:08:49.018 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:49.019 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:49.023 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:08:49.501 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:08:49.549 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:08:49.552 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:08:49.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:49.554 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:08:49.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:49.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:49.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:49.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:49.585 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:49.586 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:49.586 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:49.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:49.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:49.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:49.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:49.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:49.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:49.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:49.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:49.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:49.745 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.745 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:49.745 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:49.745 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:49.745 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:49.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:49.789 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:49.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:49.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:49.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.921 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:49.921 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:49.939 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:49.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:49.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:49.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:49.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:49.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:49.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:49.973 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:08:49.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:49.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:49.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:49.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:49.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:50.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:50.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:50.022 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:50.022 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:50.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:50.203 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:50.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:50.205 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:50.205 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=256 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:50.221 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:50.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:50.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:50.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:50.222 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:50.222 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:50.222 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:50.222 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:50.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:50.264 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:50.264 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:50.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:50.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:50.444 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:08:50.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:50.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:50.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:50.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:50.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:50.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:50.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:50.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:50.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:50.614 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:50.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:50.614 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:50.614 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:50.614 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:50.614 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:08:55.619 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:55.619 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:55.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:55.619 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:55.619 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:55.619 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:55.628 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:55.629 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:55.629 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:55.629 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:08:55.629 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:08:55.634 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:08:55.634 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:08:55.634 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:55.634 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:55.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:55.634 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:08:55.634 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:08:55.634 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:08:55.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:55.638 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:08:55.638 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:08:55.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:55.638 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:55.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:55.639 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:08:55.639 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:08:55.639 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:08:55.639 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:55.642 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:08:55.642 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:08:55.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:55.643 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:08:55.643 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:55.643 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:08:55.643 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:08:55.643 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:08:55.643 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:55.648 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:08:55.648 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:08:55.648 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:08:55.648 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:08:55.648 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.649 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:08:55.649 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:08:55.649 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:08:55.650 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.650 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.651 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:08:55.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:08:55.654 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:08:56.132 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:08:56.183 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:08:56.185 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:08:56.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.187 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:08:56.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:56.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:56.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:56.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.215 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:56.215 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:56.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:56.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:56.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:56.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:56.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:56.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:56.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:56.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:56.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:56.595 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=204 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:08:56.600 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:08:56.611 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:56.611 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:56.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:56.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.612 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.612 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.612 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:56.612 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:56.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:56.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.655 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:56.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:56.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:56.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.827 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.828 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:56.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:56.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:56.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:56.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:08:56.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.847 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:08:56.847 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:08:56.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:56.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:08:56.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:08:56.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:56.890 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:57.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:08:57.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:08:57.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:08:57.228 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:08:57.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:08:57.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:08:57.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:08:57.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:08:57.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:08:57.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:08:57.239 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:08:57.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:08:57.239 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:08:57.239 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:08:57.239 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:08:57.239 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:02.244 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:02.244 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:02.244 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:02.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:02.244 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:02.244 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:02.252 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:02.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:02.253 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:02.253 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:02.253 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:02.256 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:02.256 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:02.257 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:02.257 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:02.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:02.257 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:02.258 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:02.258 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:02.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:02.259 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:02.259 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:02.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:02.259 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:02.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:02.259 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:02.259 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:02.259 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:02.259 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:02.261 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:02.261 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:02.261 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:02.261 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:02.261 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:02.262 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:02.262 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:02.262 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:02.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:02.264 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:02.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:02.264 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:02.264 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:02.264 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:02.264 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:02.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:02.265 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:02.265 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:02.265 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:02.269 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:02.748 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:02.790 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:02.793 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:02.793 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:02.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:02.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:02.816 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:02.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:02.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:02.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:02.819 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:02.820 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:02.820 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:02.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:02.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:02.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:02.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:02.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:02.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:02.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:02.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:02.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:02.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:02.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:02.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:02.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:02.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:02.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:02.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:02.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:02.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:02.982 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:02.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:02.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:02.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:03.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:03.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:03.151 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:03.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:03.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:03.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:03.153 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:03.153 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:03.153 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:03.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:03.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:03.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:03.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.220 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:09:03.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:03.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:03.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:03.267 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:03.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:03.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:03.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:03.469 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:03.469 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:03.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:03.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:03.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:03.471 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:03.471 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:03.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:03.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:03.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:03.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.692 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:09:03.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:03.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:03.848 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:03.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:03.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:03.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:03.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:03.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:03.859 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:03.859 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:03.859 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:03.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:03.859 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:03.859 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:03.859 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:08.865 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:08.865 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:08.865 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:08.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:08.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:08.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:08.874 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:08.875 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:08.875 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:08.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:08.876 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:08.882 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:08.882 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:08.882 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:08.882 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:08.882 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:08.882 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:08.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:08.883 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:08.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:08.887 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:08.887 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:08.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:08.887 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:08.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:08.888 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:08.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:08.888 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:08.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:08.891 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:08.892 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:08.892 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:08.892 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:08.892 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:08.892 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:08.892 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:08.892 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:08.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:08.898 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:08.898 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:08.898 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:08.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:08.903 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:09.382 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:09.429 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:09.431 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:09.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:09.434 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:09.451 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:09.451 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:09.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:09.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:09.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:09.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:09.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:09.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:09.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:09.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:09.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:09.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:09.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:09.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:09.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:09.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:09.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:09.820 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:09.820 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:09.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:09.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:09.822 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:09.822 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:09.822 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:09.822 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:09.854 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:09:09.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:09.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:09.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:09.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:09.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:09.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:09.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:09.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:09.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:10.325 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:09:10.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:10.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:10.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:10.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:10.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:10.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:10.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:10.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:10.358 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:10.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:10.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:10.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:10.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:10.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:10.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:10.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:10.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:10.796 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:09:10.903 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:10.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:10.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:10.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:11.269 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:09:11.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:11.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:11.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:11.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:11.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:11.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:11.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:11.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:11.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:11.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:11.448 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:11.448 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:11.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:11.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:11.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:11.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:11.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:11.742 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:09:11.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:11.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:11.905 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:11.905 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:12.214 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:09:12.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:12.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:12.534 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:12.534 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:12.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:12.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:12.541 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:12.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:12.542 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:12.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:12.542 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:12.542 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:12.542 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:12.542 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:12.542 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:17.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:17.549 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:17.549 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:17.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:17.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:17.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:17.561 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:17.562 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:17.562 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:17.562 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:17.563 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:17.564 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:17.565 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:17.565 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:17.565 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:17.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:17.565 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:17.565 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:17.565 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:17.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:17.566 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:17.567 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:17.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:17.567 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:17.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:17.567 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:17.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:17.567 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:17.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:17.568 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:17.568 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:17.568 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:17.568 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:17.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:17.568 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:17.568 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:17.568 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:17.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:17.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:17.571 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:17.571 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:17.571 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:17.575 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:18.053 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:18.092 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:18.093 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:18.094 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:18.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:18.111 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:18.111 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:18.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:18.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:18.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:18.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:18.118 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:18.118 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:18.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:18.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:18.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:18.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:18.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:18.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:18.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:18.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:18.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:18.493 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:18.493 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:18.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:18.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:18.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:18.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:18.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:18.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:18.525 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:09:18.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:18.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:18.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:18.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:18.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:18.574 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:18.574 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:18.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:18.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:18.996 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:09:19.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:19.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:19.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:19.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:19.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:19.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:19.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:19.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:19.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:19.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:19.028 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:19.028 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:19.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:19.045 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:19.045 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:19.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:19.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:19.470 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:09:19.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:19.576 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:19.576 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:19.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:19.942 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:09:20.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:20.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:20.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:20.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:20.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:20.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:20.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:20.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:20.121 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:20.121 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:20.121 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:20.121 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:20.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:20.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:20.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:20.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:20.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:20.414 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:09:20.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:20.577 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:20.577 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:20.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:20.885 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:09:21.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:21.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:21.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:21.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:21.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:21.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:21.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:21.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:21.221 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:21.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:21.222 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:21.222 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:21.222 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:21.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:21.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:21.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:21.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:21.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:21.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:21.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:21.223 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:26.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:26.225 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:26.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:26.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:26.225 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:26.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:26.231 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:26.231 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:26.231 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:26.231 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:26.231 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:26.233 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:26.233 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:26.234 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:26.234 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:26.234 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:26.234 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:26.235 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:26.235 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:26.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:26.236 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:26.236 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:26.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:26.237 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:26.237 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:26.237 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:26.237 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:26.237 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:26.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:26.239 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:26.240 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:26.240 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:26.240 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:26.240 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:26.240 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:26.240 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:26.240 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:26.240 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:26.243 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:26.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:26.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:26.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:26.243 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:26.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:26.244 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:26.244 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:26.244 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.244 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:26.249 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:26.727 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:26.768 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:26.769 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:26.770 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:26.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:26.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:26.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:26.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:26.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:26.793 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:26.793 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:26.793 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:26.793 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:26.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:26.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:26.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:26.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:26.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:27.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:27.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:27.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:27.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:27.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:27.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:27.164 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:27.164 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:27.164 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:27.199 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:09:27.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:27.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:27.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:27.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.247 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:27.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:27.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:27.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:27.670 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:09:27.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:27.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:27.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:27.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:27.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:27.702 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:27.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.704 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:27.704 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:27.704 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:27.704 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:27.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:27.714 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:27.714 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:27.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:27.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:28.143 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:09:28.248 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:28.249 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:28.249 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:28.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:28.616 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:09:28.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:28.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:28.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:28.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:28.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:28.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:28.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:28.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:28.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:28.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:28.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:28.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:28.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:28.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:28.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:28.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:28.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:29.088 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:09:29.249 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:29.250 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:29.250 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:29.250 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:29.559 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:09:29.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:29.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:29.879 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:29.879 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:29.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:29.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:29.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:29.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:29.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:29.893 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:29.893 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:29.893 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:29.894 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:29.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:29.894 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:29.894 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:29.894 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:29.894 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:29.894 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:29.894 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:29.894 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:34.904 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:34.904 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:34.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:34.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:34.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:34.905 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:34.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:34.913 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:34.913 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:34.913 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:34.913 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:34.915 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:34.916 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:34.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:34.916 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:34.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:34.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:34.917 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:34.917 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:34.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:34.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:34.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:34.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:34.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:34.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:34.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:34.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:34.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:34.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:34.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:34.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:34.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:34.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:34.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:34.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:34.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:34.920 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:34.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:34.922 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:34.923 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:34.923 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:34.923 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:34.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:34.928 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:35.406 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:35.450 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:35.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:35.454 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:35.457 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:35.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:35.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:35.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:35.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:35.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:35.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:35.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:35.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:35.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:35.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:35.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:35.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:35.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:35.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:35.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:35.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:35.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:35.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:35.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:35.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:35.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:35.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:35.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:35.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:35.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:35.878 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:09:35.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:35.887 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:35.887 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:35.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:35.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:35.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:35.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:35.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:35.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:36.349 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:09:36.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:36.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:36.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:36.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:36.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:36.382 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:36.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:36.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:36.384 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:36.384 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:36.384 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:36.384 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:36.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:36.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:36.392 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:36.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:36.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:36.820 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:09:36.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:36.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:36.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:36.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:37.291 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:09:37.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:37.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:37.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:37.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:37.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:37.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:37.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:37.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:37.466 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:37.467 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:37.467 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:09:37.467 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:09:37.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:37.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:09:37.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:09:37.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:37.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:37.761 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:09:37.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:37.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:37.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:37.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:38.232 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:09:38.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:38.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:09:38.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:38.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:38.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:38.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:38.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:38.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:38.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:38.568 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:38.568 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:38.568 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:38.568 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=788 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.569 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.570 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.570 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:38.570 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=789 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:43.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:43.571 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:43.571 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:43.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:43.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:43.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:43.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:43.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:43.581 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:43.582 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:43.582 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:43.587 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:43.588 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:43.588 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:43.588 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:43.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:43.588 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:43.589 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:43.589 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:43.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:43.592 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:43.592 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:43.592 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:43.592 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:43.593 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:43.593 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:43.593 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:43.593 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:43.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:43.596 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:43.596 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:43.596 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:43.596 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:43.596 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:43.596 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:43.597 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:43.597 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:43.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:43.600 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:43.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:43.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:43.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:43.600 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:43.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:43.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:43.601 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:43.601 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:43.601 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:43.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:43.606 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:44.084 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:44.132 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:44.134 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:44.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:44.136 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:44.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:44.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:44.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:44.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:44.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:44.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:44.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:44.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:44.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:44.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:44.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:44.172 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:44.172 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:44.172 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:49.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:49.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:49.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:49.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:49.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:49.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:49.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:49.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:49.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:49.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:49.184 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:49.186 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:49.186 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:49.186 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:49.186 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:49.186 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:49.187 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:49.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:49.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:49.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:49.188 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:49.188 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:49.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:49.188 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:49.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:49.188 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:49.188 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:49.188 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:49.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:49.190 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:49.190 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:49.190 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:49.190 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:49.190 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:49.190 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:49.190 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:49.190 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:49.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:49.194 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:49.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:49.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:49.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:49.194 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.195 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:49.195 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:49.195 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:49.196 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:49.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:49.200 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:49.679 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:49.726 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:49.728 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:49.730 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:49.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:49.763 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:49.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:49.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:49.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:49.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:49.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:49.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:49.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:49.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:49.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:49.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:49.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:49.783 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:49.783 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:49.783 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:49.783 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:49.783 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:49.783 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:54.789 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:54.789 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:54.789 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:54.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:54.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:54.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:54.795 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:54.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:54.796 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:54.796 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:09:54.796 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:09:54.798 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:09:54.799 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:09:54.799 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:54.799 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:54.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:54.800 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:09:54.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:09:54.800 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:09:54.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:54.802 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:09:54.803 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:09:54.803 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:54.803 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:54.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:54.803 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:09:54.804 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:09:54.804 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:09:54.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:54.806 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:09:54.807 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:09:54.807 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:54.807 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:09:54.807 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:54.807 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:09:54.807 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:09:54.807 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:09:54.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:54.812 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:09:54.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:09:54.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:09:54.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.813 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:09:54.813 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:09:54.814 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:09:54.814 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:09:54.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:09:54.818 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:09:55.297 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:09:55.347 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:09:55.350 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:09:55.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:09:55.354 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:09:55.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:09:55.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:09:55.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:09:55.393 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:09:55.393 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:09:55.393 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:09:55.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:09:55.397 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:09:55.397 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:09:55.397 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:09:55.397 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:09:55.397 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:09:55.397 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:09:55.397 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:09:55.397 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:55.397 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:55.397 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:55.397 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:55.397 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:09:55.397 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:00.400 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:00.400 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:00.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:00.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:00.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:00.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:00.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:00.409 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:00.409 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:00.409 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:00.409 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:10:00.413 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:10:00.414 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:10:00.414 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:00.414 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:00.414 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:00.414 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:10:00.415 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:00.415 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:10:00.415 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:00.419 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:10:00.419 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:10:00.419 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:00.419 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:00.419 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:00.419 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:10:00.419 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:00.419 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:10:00.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:00.423 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:10:00.423 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:10:00.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:00.424 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:00.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:00.424 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:10:00.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:00.424 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:10:00.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:10:00.431 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:10:00.431 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:10:00.431 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:10:00.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:00.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:00.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:00.434 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:00.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:00.434 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:00.434 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:00.434 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:10:00.434 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:05.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:05.441 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:05.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:05.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:05.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:05.441 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:05.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:05.448 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:05.448 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:05.448 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:05.448 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:10:05.451 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:10:05.452 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:10:05.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:05.452 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:05.453 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:05.453 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:10:05.453 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:05.453 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:10:05.454 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:05.455 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:10:05.456 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:10:05.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:05.456 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:05.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:05.456 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:10:05.456 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:05.456 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:10:05.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:05.459 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:10:05.459 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:10:05.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:05.459 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:05.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:05.459 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:10:05.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:05.459 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:10:05.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:10:05.463 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:10:05.463 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:10:05.463 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:05.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:05.468 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:10:05.945 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:10:05.991 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:10:05.994 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:10:05.996 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:10:05.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:06.048 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:06.048 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:06.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:06.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:06.056 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:06.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:06.057 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:06.057 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:06.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:06.097 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:06.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:06.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:06.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:06.418 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:10:06.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:06.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:06.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:06.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:06.889 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:10:06.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:06.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:06.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:07.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:07.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:07.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:07.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:07.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:07.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:07.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:07.021 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:07.021 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:07.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:07.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:07.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:07.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:07.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:07.359 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:10:07.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:07.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:07.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:07.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:07.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:10:07.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:07.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:07.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:07.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:07.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:07.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:07.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:07.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:07.986 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:07.986 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:07.986 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:07.986 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:08.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:08.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:08.023 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:08.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:08.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:08.305 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:10:08.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:08.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:08.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:08.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:08.777 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:10:08.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:08.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:08.936 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:08.936 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:08.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:08.954 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:08.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:08.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:08.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:08.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:08.956 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:08.956 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:09.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:09.025 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:09.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:09.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:09.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:09.248 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:10:09.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:09.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:09.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:09.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:09.722 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:10:09.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:09.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:09.895 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:09.895 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:09.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:09.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:09.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:09.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:09.913 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:09.913 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:09.913 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:09.913 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:09.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:09.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:09.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:09.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:09.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:10.194 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:10:10.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:10.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:10.471 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:10.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:10.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:10.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:10.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:10.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:10.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:10.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:10.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:10.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:10.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:10.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:10.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:10.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:10.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:10.578 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:10.578 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:10.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:10.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:10.666 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:10:11.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:11.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:11.137 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:10:11.138 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:11.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:11.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:11.157 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:11.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:11.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:11.159 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:11.159 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:11.159 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:11.159 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:11.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:11.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:11.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:11.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:11.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:11.608 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:10:11.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:11.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:11.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:11.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:11.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:11.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:11.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:11.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:11.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:11.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:11.758 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:11.758 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:11.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:11.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:11.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:11.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:11.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:11.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:12.081 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:10:12.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:12.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:12.394 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:12.394 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:12.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:12.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:12.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:12.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:12.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:12.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:12.415 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:12.415 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:12.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:12.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:12.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:12.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:12.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:12.553 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:10:13.025 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:10:13.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:13.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:13.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:13.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:13.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:13.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:13.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:13.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:13.055 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:13.055 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:13.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:13.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:13.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:13.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:13.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.496 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:10:13.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:13.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:13.622 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:13.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:13.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:13.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:13.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:13.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:13.642 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:13.642 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:13.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:13.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:13.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:13.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:13.970 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:10:14.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:14.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:14.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:14.278 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:14.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:14.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:14.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:14.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:14.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:14.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:14.298 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:14.298 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:14.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:14.349 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:14.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:14.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:14.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:14.441 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:10:14.914 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:10:14.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:14.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:14.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:14.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:14.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:14.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:14.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:14.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:14.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:14.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:14.979 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:14.979 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:15.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:15.013 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:15.013 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:15.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:15.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:15.387 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:10:15.860 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:10:15.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:15.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:15.866 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:15.866 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:15.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:15.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:15.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:15.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:15.876 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:15.876 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:15.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:15.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:15.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:15.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:15.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:15.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:15.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:16.332 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:10:16.803 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:10:16.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:16.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:16.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:16.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:16.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:16.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:16.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:16.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:16.851 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:16.852 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:16.852 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:16.852 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:16.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:16.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:16.904 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:16.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:16.904 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:17.276 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:10:17.748 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:10:17.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:17.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:17.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:17.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:17.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:17.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:17.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:17.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:17.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:17.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:17.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:17.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:17.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:17.849 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:17.849 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:17.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:17.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:18.220 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:10:18.692 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:10:18.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:18.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:18.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:18.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:18.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:18.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:18.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:18.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:18.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:18.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:18.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:18.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:18.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:18.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:18.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:18.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:18.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:19.162 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:10:19.633 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:10:19.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:19.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:19.717 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:19.717 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:19.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:19.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:19.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:19.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:19.729 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:19.729 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:19.729 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:19.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:19.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:19.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:19.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:19.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:19.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:20.104 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:10:20.577 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:10:20.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:20.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:20.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:20.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:20.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:20.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:20.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:20.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:20.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:20.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:20.693 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:20.693 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:20.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:20.718 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:20.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:20.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:20.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:21.049 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:10:21.541 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:10:21.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:21.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:21.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:21.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:21.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:21.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:21.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:21.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:21.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:21.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:21.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:21.675 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:21.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:21.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:21.736 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:21.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:21.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:22.012 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:10:22.484 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:10:22.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:22.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:22.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:22.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:22.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:22.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:22.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:22.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:22.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:22.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:22.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:22.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:22.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:22.637 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:22.637 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:10:22.638 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:22.638 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:22.638 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:22.638 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:22.638 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:22.639 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:27.638 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:27.638 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:27.638 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:27.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:27.638 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:27.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:27.645 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:27.646 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:27.646 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:27.647 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:27.647 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:10:27.650 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:10:27.651 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:10:27.651 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:27.651 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:27.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:27.652 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:10:27.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:27.653 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:10:27.653 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:27.654 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:10:27.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:10:27.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:27.654 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:27.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:27.655 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:10:27.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:27.655 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:10:27.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:27.657 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:10:27.657 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:10:27.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:27.657 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:27.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:27.657 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:10:27.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:27.657 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:10:27.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:27.660 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:10:27.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:10:27.661 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:10:27.661 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:10:27.661 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:27.666 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:10:28.144 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:10:28.188 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:10:28.190 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:10:28.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:28.193 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:10:28.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:28.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:28.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:28.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.220 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:28.220 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:28.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:28.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:28.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:28.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:28.244 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:28.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:28.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:28.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:28.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:28.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:28.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:28.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:28.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:28.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:28.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:28.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:28.517 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:28.517 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:28.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.617 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:10:28.665 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:28.665 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:28.665 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:28.665 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:28.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:28.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:28.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:28.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:28.762 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:28.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:28.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.764 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:28.764 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:28.764 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:28.764 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:28.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:28.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:28.811 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:28.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:28.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:29.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:29.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:29.010 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:29.010 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:29.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:29.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:29.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:10:29.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:29.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:29.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:29.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:10:29.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:10:29.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:29.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:10:29.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:10:29.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:29.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:29.087 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:10:29.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:10:29.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:10:29.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:10:29.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:10:29.272 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:29.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:29.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:29.272 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:29.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:29.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:29.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:29.274 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:29.274 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:10:29.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:29.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:34.284 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:34.284 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:34.284 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:34.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:34.284 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:34.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:34.295 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:34.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:34.296 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:34.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:10:34.296 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:10:34.298 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:10:34.299 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:10:34.299 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:34.299 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:34.299 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:34.299 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:10:34.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:10:34.300 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:10:34.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:10:34.302 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:10:34.302 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:10:34.302 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:34.302 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:34.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:34.303 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:10:34.303 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:10:34.303 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:10:34.303 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:10:34.305 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:10:34.305 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:10:34.305 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:34.305 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:10:34.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:34.305 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:10:34.305 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:10:34.305 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:10:34.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:10:34.309 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:10:34.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:10:34.309 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:10:34.309 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:10:34.309 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:10:34.309 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:10:34.310 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:10:34.310 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:10:34.310 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.310 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:10:34.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.312 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:10:34.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:10:34.315 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:10:34.793 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:10:35.265 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:10:35.740 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:10:36.212 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:10:36.688 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:10:37.159 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:10:37.633 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:10:38.106 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:10:38.577 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:10:39.053 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:10:39.525 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:10:40.000 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:10:40.472 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:10:40.948 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:10:41.419 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:10:41.895 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:10:42.367 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:10:42.842 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:10:43.314 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:10:43.790 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:10:44.262 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:10:44.737 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:10:45.209 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:10:45.683 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:10:46.155 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:10:46.627 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:10:47.101 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:10:47.573 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:10:48.045 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:10:48.520 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:10:48.992 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:10:49.467 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:10:49.939 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:10:50.414 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:10:50.886 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:10:51.362 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:10:51.834 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:10:52.309 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:10:52.781 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:10:53.256 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:10:53.728 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:10:54.204 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:10:54.676 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:10:55.151 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:10:55.623 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:10:56.098 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:10:56.570 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:10:57.046 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:10:57.517 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:10:57.993 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:10:58.346 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:10:58.346 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:10:58.346 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:10:58.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:10:58.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:10:58.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:10:58.347 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:10:58.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5178 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:58.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5178 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:58.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5178 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:58.348 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5178 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:58.348 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5178 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:58.348 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5178 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:10:58.348 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5178 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:11:03.353 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:11:03.353 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:11:03.353 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:11:03.353 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:11:03.353 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:11:03.353 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:11:03.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:11:03.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:11:03.362 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:03.362 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:11:03.362 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:11:03.365 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:11:03.365 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:11:03.366 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:11:03.366 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:03.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:11:03.366 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:11:03.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:11:03.367 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:11:03.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:11:03.368 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:11:03.368 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:11:03.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:11:03.368 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:03.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:11:03.369 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:11:03.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:11:03.369 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:11:03.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:11:03.371 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:11:03.371 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:11:03.371 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:11:03.371 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:03.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:11:03.371 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:11:03.371 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:11:03.371 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:11:03.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:11:03.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:11:03.375 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:11:03.375 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:03.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:03.380 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:11:03.859 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:11:04.331 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:11:04.805 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:11:05.277 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:11:05.749 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:11:06.224 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:11:06.696 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:11:07.171 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:11:07.643 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:11:08.119 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:11:08.592 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:11:09.066 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:11:09.538 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:11:10.014 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:11:10.486 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:11:10.961 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:11:11.433 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:11:11.908 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:11:12.380 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:11:12.855 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:11:13.327 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:11:13.803 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:11:14.275 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:11:14.751 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:11:15.223 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:11:15.698 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:11:16.170 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:11:16.646 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:11:17.117 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:11:17.591 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:11:18.064 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:11:18.536 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:11:19.010 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:11:19.482 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:11:19.954 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:11:20.428 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:11:20.900 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:11:21.372 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:11:21.847 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:11:22.319 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:11:22.794 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:11:23.263 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:11:23.726 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:11:24.189 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:11:24.652 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:11:25.116 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:11:25.584 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:11:26.047 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:11:26.511 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:11:26.974 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:11:27.437 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:11:27.908 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:11:28.371 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:11:28.834 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:11:29.298 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:11:29.761 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:11:30.224 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:11:30.687 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:11:31.159 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:11:31.622 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:11:32.085 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:11:32.549 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:11:33.012 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:11:33.475 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:11:33.947 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:11:34.411 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:11:34.883 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:11:35.355 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:11:35.831 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:11:36.303 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:11:36.778 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:11:37.250 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:11:37.725 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:11:38.197 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:11:38.671 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:11:39.143 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:11:39.615 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:11:40.091 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:11:40.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:40.562 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:11:41.038 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:11:41.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:41.510 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:11:41.985 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:11:42.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:42.457 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:11:42.932 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:11:43.404 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:11:43.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:43.880 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:11:44.352 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:11:44.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:44.827 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:11:45.299 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:11:45.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:45.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:11:45.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:11:45.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:11:45.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:11:45.415 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:11:45.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:11:45.415 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:11:50.423 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:11:50.423 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:11:50.423 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:11:50.423 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:11:50.423 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:11:50.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:11:50.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:11:50.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:11:50.431 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:50.431 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:11:50.432 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:11:50.434 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:11:50.434 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:11:50.434 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:11:50.434 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:50.434 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:11:50.435 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:11:50.435 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:11:50.435 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:11:50.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:11:50.436 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:11:50.436 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:11:50.436 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:11:50.436 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:50.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:11:50.436 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:11:50.437 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:11:50.437 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:11:50.437 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:11:50.438 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:11:50.438 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:11:50.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:11:50.438 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:11:50.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:11:50.438 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:11:50.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:11:50.438 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:11:50.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:11:50.441 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:11:50.441 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:11:50.441 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:11:50.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:11:50.446 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:11:50.924 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:11:50.963 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:11:50.965 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:11:50.967 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:11:50.967 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:11:50.993 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:11:50.993 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:11:50.993 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:11:50.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:50.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:11:50.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:11:50.997 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:11:50.997 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:11:51.016 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:11:51.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:11:51.035 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:11:51.035 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:11:51.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:51.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:51.396 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:11:51.444 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:51.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:11:51.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:11:51.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:11:51.870 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:11:51.882 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:11:52.343 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:11:52.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:52.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:11:52.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:11:52.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:11:52.815 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:11:53.286 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:11:53.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:53.447 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:11:53.447 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:11:53.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:11:53.757 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:11:54.230 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:11:54.448 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:54.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:11:54.449 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:11:54.449 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:11:54.703 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:11:55.175 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:11:55.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:11:55.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:55.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:11:55.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:11:55.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:11:55.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:11:55.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:11:55.278 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:55.278 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:11:55.278 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:11:55.278 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:11:55.278 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:11:55.312 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:11:55.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:11:55.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:11:55.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:11:55.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:55.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:55.449 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:11:55.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:11:55.450 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:11:55.450 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:11:55.646 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:11:56.116 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:11:56.454 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:11:56.590 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:11:57.062 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:11:57.535 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:11:58.008 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:11:58.481 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:11:58.953 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:11:59.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:11:59.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:59.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:11:59.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:11:59.369 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:11:59.369 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:11:59.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:11:59.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:59.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:11:59.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:11:59.371 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:11:59.371 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:11:59.423 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:11:59.424 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:11:59.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:11:59.438 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:11:59.438 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:11:59.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:59.439 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:11:59.859 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:11:59.895 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:12:00.365 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:12:00.836 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:12:01.307 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:12:01.778 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:12:02.248 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:12:02.719 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:12:03.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:03.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:03.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:03.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:03.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:03.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:03.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:03.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:03.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:03.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:03.180 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:03.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:03.185 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:03.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:03.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:03.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:03.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:03.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:03.192 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:12:03.665 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:12:04.055 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:04.137 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:12:04.526 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:04.608 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:12:05.081 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:12:05.467 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:05.554 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:12:06.026 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:12:06.497 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:12:06.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:06.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:06.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:06.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:06.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:06.904 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:06.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:06.904 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:06.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:12:06.906 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:12:06.906 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:12:06.906 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:12:06.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:12:06.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:12:06.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:12:06.907 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3559 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:06.907 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3559 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:06.907 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3559 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:06.907 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3559 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:06.907 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3559 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:06.907 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3559 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:06.907 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3559 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:11.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:12:11.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:12:11.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:12:11.912 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:12:11.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:12:11.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:12:11.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:12:11.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:12:11.919 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:11.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:12:11.920 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:12:11.924 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:12:11.924 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:12:11.924 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:12:11.925 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:11.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:12:11.925 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:12:11.926 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:12:11.926 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:12:11.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:11.927 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:12:11.927 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:12:11.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:12:11.927 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:11.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:12:11.928 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:12:11.928 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:12:11.928 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:12:11.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:11.930 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:12:11.930 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:12:11.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:12:11.930 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:11.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:12:11.930 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:12:11.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:12:11.930 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:12:11.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.934 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:12:11.935 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:12:11.935 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:12:11.935 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:11.939 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:12:12.418 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:12:12.460 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:12:12.461 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:12.463 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:12:12.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:12.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:12.484 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:12.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:12.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:12.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:12.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:12.490 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:12.490 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:12.511 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:12.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:12.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:12.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:12.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:12.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:12.890 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:12:12.896 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:12.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:12.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:12.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:12.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:13.361 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:12:13.375 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:13.378 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:13.834 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:12:13.855 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:13.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:13.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:13.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:13.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:14.307 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:12:14.341 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:14.779 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:12:14.821 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:14.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:14.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:14.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:14.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:15.250 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:12:15.301 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:15.724 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:12:15.781 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:15.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:15.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:15.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:15.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:16.196 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:12:16.268 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:16.682 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:12:16.762 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:16.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:16.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:16.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:16.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:17.154 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:12:17.242 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:17.625 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:12:17.723 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:18.099 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:12:18.202 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:18.571 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:12:18.688 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:19.044 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:12:19.168 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:19.517 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:12:19.649 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:19.990 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:12:20.135 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:20.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:20.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:20.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:20.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:20.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:20.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:20.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:20.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:20.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:20.150 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:20.150 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:20.150 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:20.175 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:20.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:20.189 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:20.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:20.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:20.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:20.462 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:12:20.856 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:20.936 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:12:21.336 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:21.338 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:21.408 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:12:21.822 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:21.880 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:12:22.301 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:22.351 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:12:22.781 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:22.825 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:12:23.262 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:23.297 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:12:23.747 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:23.769 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:12:24.227 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:24.240 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:12:24.707 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:24.711 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:12:25.182 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:12:25.187 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:25.655 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:12:25.667 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:26.128 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:12:26.153 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:26.600 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:12:26.633 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:27.074 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:12:27.113 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:27.546 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:12:27.600 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:28.019 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:12:28.079 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:28.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:28.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:28.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:28.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:28.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:28.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:28.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:28.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:28.093 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:28.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:28.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:28.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:28.107 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:28.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:28.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:28.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:28.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:28.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:28.453 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:28.489 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:12:28.923 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:28.926 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:28.960 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:12:29.394 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:29.431 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:12:29.865 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:29.902 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:12:30.336 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:30.372 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:12:30.807 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:30.843 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:12:31.277 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:31.317 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:12:31.748 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:31.789 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:12:32.225 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:32.261 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:12:32.695 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:32.732 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:12:33.166 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:33.205 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:12:33.637 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:33.678 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:12:34.114 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:34.150 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:12:34.584 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:34.621 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:12:35.055 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:35.092 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:12:35.526 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:35.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:35.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:35.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:35.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:35.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:35.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:35.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:35.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:35.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:35.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:35.550 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:35.550 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:35.558 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:35.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:35.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:35.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:35.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:35.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:35.565 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:12:35.952 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:36.037 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:12:36.427 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:36.430 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:36.509 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:12:36.898 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:36.901 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:36.980 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:12:37.369 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:37.453 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:12:37.840 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:37.842 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:12:37.926 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:12:38.316 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:38.398 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:12:38.787 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:38.869 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:12:39.258 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:39.342 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:12:39.728 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:39.815 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:12:40.205 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:40.287 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:12:40.676 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:40.758 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:12:41.146 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:41.231 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:12:41.617 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:41.703 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:12:42.094 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:42.176 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:12:42.564 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:42.649 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:12:43.035 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:43.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:43.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:43.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:43.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:43.043 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6718 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:43.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:43.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:43.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:43.054 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:43.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:12:43.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:12:43.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:12:43.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:12:43.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:12:43.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:12:43.056 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:12:43.056 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:43.056 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:43.056 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:43.056 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:43.056 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:43.056 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:43.056 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:48.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:12:48.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:12:48.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:12:48.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:12:48.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:12:48.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:12:48.074 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:12:48.075 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:12:48.075 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:48.075 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:12:48.075 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:12:48.077 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:12:48.078 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:12:48.078 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:12:48.078 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:48.078 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:12:48.078 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:12:48.078 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:12:48.078 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:12:48.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:48.080 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:12:48.080 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:12:48.080 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:12:48.080 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:48.080 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:12:48.080 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:12:48.080 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:12:48.080 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:12:48.080 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:48.081 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:12:48.081 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:12:48.081 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:12:48.081 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:12:48.081 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:12:48.081 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:12:48.081 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:12:48.081 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:12:48.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:12:48.084 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:12:48.084 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:12:48.084 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:12:48.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:12:48.089 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:12:48.567 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:12:48.607 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:12:48.608 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:12:48.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:48.609 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:12:48.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:48.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:48.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:48.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:48.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:48.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:48.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:48.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:48.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:48.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:48.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:48.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:48.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:49.040 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:12:49.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:49.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:49.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:49.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:49.514 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:12:49.986 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:12:50.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:50.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:50.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:50.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:50.459 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:12:50.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:50.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:50.780 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:50.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:50.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:50.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:50.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:50.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:50.801 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:50.801 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:50.801 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:50.801 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:50.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:50.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:50.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:50.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:50.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:50.931 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:12:51.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:51.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:51.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:51.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:51.405 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:12:51.877 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:12:52.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:52.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:52.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:52.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:52.348 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:12:52.821 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:12:52.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:52.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:52.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:52.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:52.962 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:52.962 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:52.962 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:12:52.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:52.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:52.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:52.964 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:12:52.964 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:12:53.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:53.014 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:12:53.014 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:12:53.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:53.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:53.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:53.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:53.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:53.094 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:53.294 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:12:53.766 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:12:54.240 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:12:54.712 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:12:55.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:12:55.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:12:55.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:12:55.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:12:55.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:12:55.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:12:55.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:12:55.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:12:55.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:12:55.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:12:55.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:12:55.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:12:55.130 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:12:55.130 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:12:55.130 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:12:55.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:55.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:55.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:55.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:55.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:12:55.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:00.132 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:00.132 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:00.132 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:00.132 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:00.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:00.132 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:00.138 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:00.139 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:00.139 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:00.140 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:00.140 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:13:00.143 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:13:00.143 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:13:00.143 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:00.143 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:00.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:00.144 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:13:00.144 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:00.144 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:13:00.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:00.147 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:13:00.147 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:13:00.147 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:00.147 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:00.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:00.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:13:00.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:00.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:13:00.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:00.149 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:13:00.149 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:13:00.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:00.149 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:00.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:00.150 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:13:00.150 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:00.150 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:13:00.150 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:13:00.153 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:13:00.153 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:13:00.153 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.153 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:00.158 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:13:00.638 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:13:00.681 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:13:00.682 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:13:00.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:00.683 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:13:00.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:00.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:00.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:00.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:00.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:00.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:00.698 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:00.698 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:00.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:00.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:00.743 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:00.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:00.743 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:01.109 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:13:01.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:01.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:01.157 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:01.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:01.581 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:13:02.053 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:13:02.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:02.157 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:02.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:02.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:02.524 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:13:02.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:02.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:02.837 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:02.837 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:02.854 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:02.854 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:02.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:02.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:02.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:02.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:02.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:02.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:02.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:02.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:02.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:02.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:02.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:02.997 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:13:03.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:03.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:03.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:03.159 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:03.469 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:13:03.942 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:13:04.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:04.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:04.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:04.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:04.415 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:13:04.888 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:13:05.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:05.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:05.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:05.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:05.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:05.019 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:05.019 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:05.019 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:05.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:05.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:05.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:05.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:05.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:05.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:05.023 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:13:05.024 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:05.024 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:05.024 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:05.024 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:05.024 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:05.024 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:10.027 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:10.027 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:10.027 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:10.027 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:10.027 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:10.027 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:10.034 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:10.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:10.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:10.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:10.036 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:13:10.042 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:13:10.042 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:13:10.042 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:10.042 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:10.043 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:10.043 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:13:10.043 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:10.043 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:13:10.043 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:10.046 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:13:10.046 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:13:10.046 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:10.046 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:10.046 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:10.047 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:13:10.047 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:10.047 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:13:10.047 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:10.049 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:13:10.050 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:13:10.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:10.050 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:10.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:10.050 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:13:10.050 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:10.050 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:13:10.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:13:10.054 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:13:10.054 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:13:10.054 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:10.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:10.059 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:13:10.538 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:13:10.578 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:13:10.579 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:13:10.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:10.581 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:13:10.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:10.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:10.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:10.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:10.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:10.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:10.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:10.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:10.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:10.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:10.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:10.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:10.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:11.010 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:13:11.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:11.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:11.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:11.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:11.481 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:13:11.955 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:13:12.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:12.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:12.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:12.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:12.427 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:13:12.740 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:12.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:12.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:12.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:12.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:12.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:12.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:12.767 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:12.767 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:12.767 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:12.767 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:12.767 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:12.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:12.811 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:12.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:12.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:12.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:12.899 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:13:13.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:13.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:13.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:13.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:13.370 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:13:13.841 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:13:14.062 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:14.062 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:14.062 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:14.062 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:14.312 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:13:14.786 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:13:14.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:14.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:14.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:14.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:14.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:14.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:14.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:14.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:14.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:14.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:14.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:14.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:14.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:14.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:14.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:14.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:14.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:15.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:15.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:15.064 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:15.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:15.258 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:13:15.730 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:13:16.201 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:13:16.674 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:13:17.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:17.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:17.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:17.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:17.084 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:17.084 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:17.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:17.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:17.085 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:17.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:17.085 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:17.085 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:17.085 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:13:17.085 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:17.085 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:22.091 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:22.092 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:22.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:22.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:22.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:22.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:22.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:22.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:22.100 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:22.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:22.101 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:13:22.103 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:13:22.104 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:13:22.104 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:22.104 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:22.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:22.105 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:13:22.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:22.106 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:13:22.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:22.107 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:13:22.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:13:22.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:22.108 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:22.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:22.108 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:13:22.108 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:22.108 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:13:22.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:22.110 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:13:22.110 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:13:22.110 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:22.110 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:22.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:22.111 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:13:22.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:22.111 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:13:22.111 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.114 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:13:22.114 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:13:22.114 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:13:22.114 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:22.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:22.119 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:13:22.597 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:13:22.643 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:13:22.646 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:13:22.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:22.648 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:13:22.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:22.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:22.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:22.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:22.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:22.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:22.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:22.674 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:22.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:22.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:22.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:22.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:22.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:23.068 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:13:23.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:23.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:23.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:23.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:23.540 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:13:24.014 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:13:24.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:24.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:24.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:24.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:24.486 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:13:24.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:24.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:24.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:24.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:24.842 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:24.842 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:24.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:24.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:24.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:24.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:24.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:24.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:24.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:24.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:24.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:24.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:24.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:24.958 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:13:25.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:25.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:25.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:25.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:25.429 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:13:25.903 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:13:26.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:26.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:26.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:26.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:26.376 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:13:26.848 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:13:26.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:26.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:26.953 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:26.953 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:26.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:26.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:26.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:26.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:26.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:26.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:26.965 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:26.965 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:26.965 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:26.965 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:26.965 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:13:31.970 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:31.970 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:31.970 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:31.970 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:31.970 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:31.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:31.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:31.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:31.977 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:31.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:31.978 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:13:31.980 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:13:31.980 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:13:31.980 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:31.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:31.981 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:31.981 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:13:31.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:31.982 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:13:31.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:31.982 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:13:31.983 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:13:31.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:31.983 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:31.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:31.983 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:13:31.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:31.983 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:13:31.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:31.985 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:13:31.985 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:13:31.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:31.985 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:31.985 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:31.985 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:13:31.985 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:31.985 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:13:31.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:31.988 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:13:31.988 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:13:31.988 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:13:31.988 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:13:31.988 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:13:31.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:13:31.989 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:13:31.989 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:31.994 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:13:32.471 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:13:32.508 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:13:32.509 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:13:32.511 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:13:32.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:32.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:32.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:32.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:32.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:32.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:32.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:32.535 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:32.535 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:32.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:32.579 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:32.579 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:32.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:32.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:32.941 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:13:32.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:32.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:32.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:32.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:33.415 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:13:33.887 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:13:33.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:33.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:33.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:33.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:34.358 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:13:34.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:34.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:34.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:34.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:34.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:34.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:34.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:34.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:34.767 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:34.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:34.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:34.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:34.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:34.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:34.768 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:13:34.768 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=601 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:34.768 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=601 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:34.768 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=601 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:34.768 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=601 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:34.768 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=601 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:34.768 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=601 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:39.772 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:39.772 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:39.772 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:39.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:39.772 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:39.772 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:39.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:39.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:39.782 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:39.782 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:39.782 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:13:39.786 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:13:39.786 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:13:39.786 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:39.787 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:39.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:39.787 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:13:39.788 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:39.788 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:13:39.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:39.790 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:13:39.790 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:13:39.790 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:39.790 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:39.791 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:39.791 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:13:39.791 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:39.791 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:13:39.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:39.793 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:13:39.793 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:13:39.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:39.793 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:39.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:39.793 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:13:39.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:39.793 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:13:39.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:39.796 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:13:39.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:13:39.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:13:39.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:13:39.796 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:13:39.797 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:13:39.797 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:13:39.797 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:39.802 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:13:40.279 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:13:40.320 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:13:40.321 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:13:40.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:40.323 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:13:40.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:40.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:40.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:40.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:40.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:40.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:40.335 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:40.335 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:40.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:40.380 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:40.380 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:40.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:40.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:40.749 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:13:40.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:40.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:40.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:40.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:41.222 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:13:41.694 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:13:41.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:41.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:41.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:41.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:42.165 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:13:42.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:42.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:42.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:42.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:42.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:42.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:42.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:42.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:42.590 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:42.590 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:42.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:42.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:42.590 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:42.590 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:42.591 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:13:42.591 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=604 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:42.591 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=604 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:42.591 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=604 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:42.591 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=604 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:42.591 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=604 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:42.591 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=604 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:47.593 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:47.593 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:47.593 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:47.593 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:47.593 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:47.593 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:47.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:47.599 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:47.600 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:47.600 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:47.600 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:13:47.601 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:13:47.601 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:13:47.602 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:47.602 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:47.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:47.602 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:13:47.603 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:47.603 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:13:47.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:47.604 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:13:47.604 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:13:47.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:47.604 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:47.604 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:47.604 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:13:47.604 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:47.604 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:13:47.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:47.606 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:13:47.606 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:13:47.606 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:47.606 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:47.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:47.606 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:13:47.606 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:47.606 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:13:47.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:13:47.609 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:13:47.609 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:13:47.609 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:47.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:47.613 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:13:48.090 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:13:48.132 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:13:48.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:48.134 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:13:48.138 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:13:48.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:48.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:48.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:48.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:48.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:48.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:48.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:48.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:48.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:48.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:48.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:48.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:48.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:48.563 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:13:48.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:48.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:48.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:48.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:48.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:48.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:48.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:48.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:48.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:48.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:48.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:48.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:48.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:48.642 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:48.642 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:48.642 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:48.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:48.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:48.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:48.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:48.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:49.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:49.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:49.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:49.034 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:13:49.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:49.044 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:49.044 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:49.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:49.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:49.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:49.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:49.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:49.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:49.049 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:49.049 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:49.049 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:13:49.049 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:49.049 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:49.050 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:49.050 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:49.050 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:49.050 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:13:54.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:54.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:54.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:54.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:54.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:54.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:54.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:54.056 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:54.056 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:54.056 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:13:54.056 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:13:54.057 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:13:54.057 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:13:54.057 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:54.057 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:54.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:54.057 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:13:54.057 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:13:54.057 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:13:54.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:54.060 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:13:54.060 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:13:54.060 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:54.060 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:54.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:54.060 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:13:54.061 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:13:54.061 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:13:54.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:54.063 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:13:54.063 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:13:54.063 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:54.063 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:13:54.063 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:54.063 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:13:54.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:13:54.064 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:13:54.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.068 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:13:54.068 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:13:54.068 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:13:54.069 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:13:54.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:13:54.073 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:13:54.550 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:13:54.595 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:13:54.596 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:13:54.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:54.598 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:13:54.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:54.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:54.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:54.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:54.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:54.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:54.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:54.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:54.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:54.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:54.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:54.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:54.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:55.023 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:13:55.067 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:55.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:55.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:55.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:55.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:55.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:55.076 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:55.076 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:55.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:55.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:55.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:13:55.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:55.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:55.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:55.104 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:13:55.104 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:13:55.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:55.114 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:13:55.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:13:55.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:55.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:55.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:13:55.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:13:55.494 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:13:55.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:13:55.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:13:55.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:13:55.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:13:55.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:13:55.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:13:55.505 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:13:55.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:13:55.505 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:13:55.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:13:55.505 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:13:55.505 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:13:55.505 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:00.512 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:00.512 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:00.512 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:00.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:00.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:00.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:00.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:00.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:00.522 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:00.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:00.523 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:00.529 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:00.529 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:00.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:00.529 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:00.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:00.529 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:00.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:00.530 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:00.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:00.534 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:00.534 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:00.534 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:00.534 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:00.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:00.534 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:00.535 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:00.535 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:00.535 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:00.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:00.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:00.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:00.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:00.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:00.538 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:00.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:00.538 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:00.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:00.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:00.544 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:00.544 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:00.544 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:00.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:00.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:00.549 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:01.024 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:01.068 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:01.069 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:01.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:01.071 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:01.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:01.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:01.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:01.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:01.130 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:01.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:01.131 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:01.131 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:01.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:01.171 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:01.171 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:01.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:01.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:01.496 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:01.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:01.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:01.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:01.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:01.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:01.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:01.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:01.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:01.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:01.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:01.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:01.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:01.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:01.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:01.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:01.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:01.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:01.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:01.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:01.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:01.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:01.967 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:14:02.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:02.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:02.008 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:02.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:02.018 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:02.018 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:02.018 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:02.018 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:02.019 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:02.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:02.019 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:02.019 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:02.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:02.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:02.020 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:07.026 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:07.026 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:07.026 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:07.026 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:07.026 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:07.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:07.033 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:07.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:07.035 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:07.035 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:07.035 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:07.040 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:07.040 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:07.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:07.041 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:07.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:07.041 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:07.041 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:07.041 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:07.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:07.044 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:07.044 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:07.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:07.045 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:07.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:07.045 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:07.045 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:07.045 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:07.045 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:07.048 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:07.048 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:07.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:07.048 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:07.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:07.048 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:07.048 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:07.048 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:07.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:07.053 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:07.054 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:07.054 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:07.054 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.054 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:07.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:07.059 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:07.536 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:07.587 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:07.589 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:07.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:07.591 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:07.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:07.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:07.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:07.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:07.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:07.656 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:07.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:07.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:07.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:07.685 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:07.685 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:07.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:07.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:08.008 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:08.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:08.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:08.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:08.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:08.479 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:14:08.953 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:14:09.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:09.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:09.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:09.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:09.425 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:14:09.897 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:14:10.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:10.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:10.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:10.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:10.368 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:14:10.841 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:14:11.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:11.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:11.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:11.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:11.314 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:14:11.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:11.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:11.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:11.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:11.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:11.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:11.696 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:11.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:11.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:11.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:11.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:11.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:11.696 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:16.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:16.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:16.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:16.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:16.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:16.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:16.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:16.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:16.711 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:16.711 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:16.711 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:16.714 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:16.714 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:16.714 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:16.714 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:16.715 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:16.715 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:16.715 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:16.715 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:16.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:16.717 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:16.717 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:16.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:16.717 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:16.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:16.717 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:16.717 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:16.717 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:16.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:16.719 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:16.719 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:16.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:16.719 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:16.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:16.719 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:16.719 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:16.719 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:16.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:16.722 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:16.722 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:16.722 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:16.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:16.727 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:17.205 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:17.243 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:17.244 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:17.245 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:17.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:17.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:17.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:17.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:17.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:17.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:17.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:17.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:17.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:17.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:17.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:17.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:17.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:17.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:17.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:17.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:17.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:17.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:17.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:17.536 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:17.536 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:17.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:17.588 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:17.588 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:17.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.673 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:17.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:17.725 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:17.725 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:17.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:17.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:17.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:17.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:17.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:17.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:17.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:17.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:17.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:17.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:17.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:17.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:17.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:17.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:17.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:17.811 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:22.817 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:22.817 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:22.817 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:22.817 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:22.817 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:22.817 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:22.824 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:22.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:22.824 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:22.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:22.824 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:22.827 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:22.828 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:22.828 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:22.828 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:22.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:22.829 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:22.830 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:22.830 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:22.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:22.832 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:22.832 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:22.832 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:22.832 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:22.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:22.833 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:22.833 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:22.833 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:22.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:22.835 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:22.835 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:22.835 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:22.835 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:22.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:22.835 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:22.836 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:22.836 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:22.836 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:22.839 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:22.840 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:22.840 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:22.840 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:22.844 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:23.323 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:23.366 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:23.368 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:23.369 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:23.369 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:23.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:23.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:23.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:23.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:23.433 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:23.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:23.434 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:23.434 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:23.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:23.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:23.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:23.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:23.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:23.793 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:23.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:23.843 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:23.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:23.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:24.266 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:14:24.738 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:14:24.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:24.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:24.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:24.845 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:25.211 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:14:25.685 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:14:25.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:25.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:25.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:25.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:26.157 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:14:26.628 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:14:26.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:26.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:26.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:26.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:27.101 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:14:27.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:27.474 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:27.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:27.479 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:27.479 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:27.479 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:27.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1002 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:32.486 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:32.486 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:32.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:32.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:32.487 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:32.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:32.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:32.497 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:32.497 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:32.497 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:32.498 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:32.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:32.503 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:32.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:32.504 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:32.504 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:32.504 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:32.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:32.505 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:32.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:32.508 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:32.508 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:32.508 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:32.509 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:32.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:32.509 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:32.510 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:32.510 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:32.510 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:32.512 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:32.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:32.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:32.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:32.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:32.512 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:32.513 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:32.513 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:32.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:32.518 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:32.518 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:32.518 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:32.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:32.522 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:33.001 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:33.046 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:33.048 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:33.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:33.051 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:33.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:33.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:33.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:33.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:33.113 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:33.114 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:33.114 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:33.114 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:33.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:33.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:33.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:33.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:33.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:33.471 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:33.521 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:33.521 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:33.522 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:33.522 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:33.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:33.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:33.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:33.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:33.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:33.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:33.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:33.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:33.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:33.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:33.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:33.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:33.875 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:33.875 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:33.876 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:33.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:33.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:33.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:33.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:33.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:33.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:38.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:38.877 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:38.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:38.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:38.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:38.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:38.884 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:38.885 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:38.885 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:38.886 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:38.886 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:38.890 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:38.890 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:38.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:38.891 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:38.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:38.892 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:38.892 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:38.893 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:38.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:38.895 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:38.895 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:38.895 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:38.895 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:38.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:38.896 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:38.896 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:38.896 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:38.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:38.898 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:38.899 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:38.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:38.899 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:38.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:38.899 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:38.899 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:38.899 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:38.899 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:38.904 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:38.904 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:38.904 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:38.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:38.908 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:39.386 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:39.434 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:39.436 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:39.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:39.437 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:39.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:39.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:39.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:39.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:39.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:39.512 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:39.512 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:39.512 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:39.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:39.532 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:39.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:39.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:39.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:39.856 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:39.907 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:39.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:39.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:39.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:40.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:40.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:40.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:40.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:40.258 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:40.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:40.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:40.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:40.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:40.262 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:40.262 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:40.263 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:40.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:40.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:40.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:40.263 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:40.263 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:40.264 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:40.264 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:40.264 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:40.264 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:40.264 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:45.265 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:45.265 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:45.265 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:45.265 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:45.265 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:45.265 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:45.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:45.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:45.273 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:45.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:45.274 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:45.278 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:45.279 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:45.279 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:45.279 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:45.280 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:45.280 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:45.281 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:45.281 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:45.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:45.283 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:45.283 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:45.283 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:45.283 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:45.284 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:45.284 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:45.284 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:45.284 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:45.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:45.287 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:45.287 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:45.287 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:45.287 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:45.287 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:45.287 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:45.287 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:45.287 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:45.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:45.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:45.292 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:45.292 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:45.292 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.292 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:45.297 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:45.775 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:45.817 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:45.819 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:45.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:45.821 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:45.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:45.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:45.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:45.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:45.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:45.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:45.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:45.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:45.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:45.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:45.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:45.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:45.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:46.245 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:46.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:46.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:46.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:46.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:46.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:46.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:46.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:46.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:46.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:46.648 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:46.648 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:46.648 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:46.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:46.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:46.649 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:46.649 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:46.649 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:46.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:46.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:51.655 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:51.656 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:51.656 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:51.656 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:51.656 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:51.656 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:51.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:51.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:51.664 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:51.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:51.665 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:51.667 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:51.668 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:51.668 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:51.668 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:51.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:51.668 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:51.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:51.669 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:51.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:51.670 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:51.670 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:51.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:51.670 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:51.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:51.671 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:51.671 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:51.671 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:51.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:51.673 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:51.673 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:51.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:51.673 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:51.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:51.673 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:51.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:51.673 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:51.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.677 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:51.677 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:51.677 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:51.678 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:51.682 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:52.160 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:52.200 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:52.201 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:52.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:52.203 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:52.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:52.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:52.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:52.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:52.274 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:52.274 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:52.274 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:52.274 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:52.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:52.306 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:52.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:52.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:52.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:52.630 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:52.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:52.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:52.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:52.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:53.103 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:14:53.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:53.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:53.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:53.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:53.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:53.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:53.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:53.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:53.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:53.176 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:53.176 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:53.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:53.176 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:53.176 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:53.176 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:58.180 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:58.180 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:58.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:58.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:58.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:58.180 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:58.191 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:58.191 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:58.191 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:58.191 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:14:58.191 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:14:58.192 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:14:58.192 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:14:58.192 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:58.192 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:58.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:58.192 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:14:58.193 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:58.193 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:14:58.193 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:14:58.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:58.194 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:14:58.194 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:14:58.194 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:58.194 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:14:58.194 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:58.194 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:14:58.194 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:14:58.194 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:14:58.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.198 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:14:58.198 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:14:58.198 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:14:58.199 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:14:58.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:14:58.203 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:14:58.682 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:14:58.727 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:14:58.729 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:14:58.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:58.731 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:14:58.753 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:58.753 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:58.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:14:58.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:58.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:58.787 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:58.787 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:14:58.787 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:14:58.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:58.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:14:58.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:14:58.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:58.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:59.155 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:14:59.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:59.201 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:59.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:59.202 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:59.539 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:14:59.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:14:59.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:14:59.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:14:59.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:14:59.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:14:59.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:14:59.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:14:59.560 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:14:59.560 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:14:59.560 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:14:59.560 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:14:59.560 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:14:59.560 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:14:59.560 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:14:59.560 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:59.560 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:59.560 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:59.560 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:59.560 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:14:59.560 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:04.565 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:04.565 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:04.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:04.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:04.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:04.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:04.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:04.575 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:04.576 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:04.576 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:04.576 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:15:04.582 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:15:04.582 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:15:04.583 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:04.583 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:04.583 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:04.583 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:15:04.583 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:04.583 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:15:04.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:04.587 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:15:04.588 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:15:04.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:04.588 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:04.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:04.588 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:15:04.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:04.588 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:15:04.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:04.592 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:15:04.592 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:15:04.592 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:04.592 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:04.592 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:04.592 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:15:04.592 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:04.592 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:15:04.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:04.596 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:15:04.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:15:04.596 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:15:04.596 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:15:04.596 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:15:04.596 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:15:04.597 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:15:04.597 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:15:04.597 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.597 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:04.602 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:15:05.081 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:15:05.120 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:15:05.122 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:15:05.124 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:15:05.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:05.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:05.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:05.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:15:05.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:05.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:05.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:05.157 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:15:05.157 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:15:05.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:05.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:05.177 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:05.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:05.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:05.553 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:15:05.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:05.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:05.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:05.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:05.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:05.996 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:06.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:06.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:06.011 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:06.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:06.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:06.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:06.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:06.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:06.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:06.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:06.013 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:06.013 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:06.013 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:15:11.018 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:11.018 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:11.018 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:11.018 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:11.018 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:11.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:11.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:11.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:11.021 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:11.021 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:11.021 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:15:11.022 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:15:11.022 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:15:11.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:11.022 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:11.022 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:11.022 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:15:11.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:11.022 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:15:11.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:11.023 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:15:11.023 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:15:11.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:11.023 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:11.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:11.023 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:15:11.023 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:11.023 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:15:11.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:11.024 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:15:11.024 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:15:11.024 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:11.025 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:11.025 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:11.025 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:15:11.025 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:11.025 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:15:11.025 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:15:11.027 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:15:11.027 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:15:11.027 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.027 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:11.032 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:15:11.509 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:15:11.551 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:15:11.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:11.553 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:15:11.553 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:15:11.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:11.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:11.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:15:11.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:11.571 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:11.571 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:11.571 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:15:11.571 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:15:11.980 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:15:12.030 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:12.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:12.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:12.034 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:12.452 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:15:12.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:12.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:12.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:12.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:12.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:12.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:12.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:15:12.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:12.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:12.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:12.748 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:15:12.748 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:15:12.924 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:15:13.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:13.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:13.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:13.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:13.398 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:15:13.794 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:15:13.870 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:15:13.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:15:13.910 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:13.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:13.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:13.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:13.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:13.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:13.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:13.923 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:13.923 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:13.923 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:13.923 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:15:13.923 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:13.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:13.923 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:13.923 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:13.923 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:13.923 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:13.923 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:13.923 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:18.927 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:18.927 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:18.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:18.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:18.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:18.927 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:18.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:18.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:18.934 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:18.934 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:18.935 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:15:18.938 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:15:18.938 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:15:18.938 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:18.938 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:18.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:18.939 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:15:18.939 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:18.939 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:15:18.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:18.941 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:15:18.941 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:15:18.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:18.942 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:18.942 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:18.942 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:15:18.942 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:18.942 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:15:18.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:18.944 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:15:18.944 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:15:18.944 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:18.944 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:18.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:18.944 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:15:18.945 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:18.945 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:15:18.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:15:18.948 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:15:18.949 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:15:18.949 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:15:18.949 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.949 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:18.954 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:15:19.432 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:15:19.481 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:15:19.483 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:15:19.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:19.485 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:15:19.510 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:19.511 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:19.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:15:19.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:19.516 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:19.516 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:19.517 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:15:19.517 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:15:19.905 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:15:19.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:19.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:19.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:19.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:20.376 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:15:20.849 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:15:20.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:20.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:20.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:20.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:21.321 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:15:21.793 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:15:21.955 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:21.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:21.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:21.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:22.264 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:15:22.738 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:15:22.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:22.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:22.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:22.957 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:23.210 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:15:23.682 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:15:23.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:23.957 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:23.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:23.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:24.153 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:15:24.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:15:24.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:24.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:24.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:24.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:24.627 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:15:25.100 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:15:25.573 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:15:26.045 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:15:26.511 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:15:26.983 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:15:27.457 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:15:27.930 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:15:28.404 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:15:28.877 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:15:29.351 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:15:29.823 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:15:30.297 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:15:30.769 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:15:31.241 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:15:31.715 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:15:32.188 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:15:32.660 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:15:33.134 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:15:33.606 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:15:34.078 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:15:34.552 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:15:35.024 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:15:35.496 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:15:35.971 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:15:36.443 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:15:36.915 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:15:37.387 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:15:37.861 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:15:38.333 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:15:38.804 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:15:39.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:15:39.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:39.125 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:39.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:39.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:39.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:39.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:39.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:39.139 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:39.139 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:39.139 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:39.139 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:15:39.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:39.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:39.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4358 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4358 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4358 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4358 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4358 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4358 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:39.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4359 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:44.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:44.142 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:44.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:44.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:44.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:44.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:44.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:44.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:44.152 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:44.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:15:44.152 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:15:44.155 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:15:44.155 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:15:44.155 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:44.155 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:44.155 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:44.156 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:15:44.156 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:15:44.156 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:15:44.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:44.158 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:15:44.158 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:15:44.158 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:44.158 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:44.158 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:44.158 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:15:44.158 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:15:44.159 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:15:44.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:44.161 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:15:44.161 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:15:44.161 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:44.161 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:15:44.161 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:44.161 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:15:44.161 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:15:44.162 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:15:44.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:15:44.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:15:44.168 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:15:44.168 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:15:44.168 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:15:44.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:15:44.173 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:15:44.652 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:15:44.699 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:15:44.701 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:15:44.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:15:44.702 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:15:44.712 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:44.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:44.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:15:44.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:44.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:44.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:44.716 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:15:44.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:15:45.123 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:15:45.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:45.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:45.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:45.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:45.595 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:15:46.068 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:15:46.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:46.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:46.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:46.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:46.541 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:15:47.013 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:15:47.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:47.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:47.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:47.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:47.484 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:15:47.955 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:15:48.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:48.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:48.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:48.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:48.428 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:15:48.900 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:15:49.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:49.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:49.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:49.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:49.373 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:15:49.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:15:49.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:15:49.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:15:49.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:49.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:49.847 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:15:50.319 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:15:50.793 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:15:51.266 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:15:51.738 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:15:52.212 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:15:52.684 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:15:53.156 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:15:53.629 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:15:54.102 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:15:54.573 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:15:55.048 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:15:55.520 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:15:55.992 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:15:56.466 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:15:56.631 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:15:56.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:15:56.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:15:56.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:15:56.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:15:56.646 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:15:56.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:15:56.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:15:56.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:15:56.650 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:15:56.650 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:15:56.650 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:15:56.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:15:56.651 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:15:56.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:15:56.651 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2694 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:56.651 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2694 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:56.651 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2694 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:56.651 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2694 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:56.652 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2694 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:56.652 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2694 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:15:56.652 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2694 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:01.653 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:01.653 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:01.653 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:01.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:01.653 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:01.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:01.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:01.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:01.664 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:01.664 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:01.664 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:16:01.670 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:16:01.670 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:16:01.670 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:01.670 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:01.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:01.671 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:16:01.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:01.671 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:16:01.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:01.675 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:16:01.676 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:16:01.676 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:01.676 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:01.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:01.676 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:16:01.676 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:01.676 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:16:01.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:01.680 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:16:01.680 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:16:01.680 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:01.680 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:01.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:01.681 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:16:01.681 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:01.681 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:16:01.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:01.686 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:16:01.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:16:01.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:16:01.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:16:01.686 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.687 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:16:01.687 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:16:01.687 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:16:01.688 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:01.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:01.692 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:16:02.171 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:16:02.220 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:16:02.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:16:02.224 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:16:02.226 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:16:02.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:16:02.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:16:02.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:16:02.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:02.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:16:02.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:16:02.256 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:16:02.256 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:16:02.643 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:16:02.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:02.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:02.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:02.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:03.114 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:16:03.585 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:16:03.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:03.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:03.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:03.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:04.058 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:16:04.531 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:16:04.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:04.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:04.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:04.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:05.003 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:16:05.474 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:16:05.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:05.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:05.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:05.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:05.947 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:16:06.420 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:16:06.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:06.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:06.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:06.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:06.891 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:16:07.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:16:07.153 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:16:07.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:16:07.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:07.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:07.362 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:16:07.833 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:16:08.307 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:16:08.780 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:16:09.254 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:16:09.726 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:16:10.198 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:16:10.672 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:16:11.145 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:16:11.610 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:16:11.730 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:16:11.733 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:11.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:16:11.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:16:11.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:11.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:11.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:11.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:11.747 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:11.747 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:11.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:11.747 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:11.748 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:11.748 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:16:11.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:11.748 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:11.748 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:11.748 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:11.748 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:11.748 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:11.748 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:16.754 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:16.754 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:16.754 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:16.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:16.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:16.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:16.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:16.765 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:16.765 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:16.765 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:16.766 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:16:16.770 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:16:16.770 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:16:16.771 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:16.771 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:16.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:16.771 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:16:16.772 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:16.772 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:16:16.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:16.775 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:16:16.776 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:16:16.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:16.776 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:16.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:16.777 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:16:16.777 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:16.777 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:16:16.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:16.779 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:16:16.780 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:16:16.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:16.780 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:16.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:16.780 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:16:16.780 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:16.780 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:16:16.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:16.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:16:16.786 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:16:16.786 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:16:16.786 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:16.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:16.791 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:16:17.268 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:16:17.321 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:16:17.324 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:16:17.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:16:17.324 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:16:17.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:16:17.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:16:17.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:16:17.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:17.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:16:17.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:16:17.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:16:17.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:16:17.739 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:16:17.789 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:17.789 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:17.789 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:17.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:18.211 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:16:18.682 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:16:18.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:18.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:18.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:18.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:19.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:16:19.628 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:16:19.792 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:19.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:19.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:19.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:20.100 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:16:20.571 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:16:20.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:20.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:20.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:20.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:21.044 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:16:21.516 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:16:21.794 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:21.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:21.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:21.795 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:21.988 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:16:22.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:16:22.249 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:16:22.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:16:22.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:22.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:22.462 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:16:22.934 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:16:23.406 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:16:23.879 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:16:24.352 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:16:24.824 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:16:25.298 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:16:25.770 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:16:26.242 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:16:26.716 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:16:26.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:16:26.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:26.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:16:26.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:16:26.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:26.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:26.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:26.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:26.853 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:26.853 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:26.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:26.853 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:26.853 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:26.853 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:26.853 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:16:26.853 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:26.853 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:26.853 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:26.853 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:26.853 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:16:31.858 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:31.858 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:31.858 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:31.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:31.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:31.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:31.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:31.868 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:31.868 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:31.869 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:31.869 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:16:31.872 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:16:31.872 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:16:31.873 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:31.873 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:31.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:31.873 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:16:31.874 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:31.874 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:16:31.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:31.875 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:16:31.875 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:16:31.875 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:31.876 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:31.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:31.876 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:16:31.876 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:31.876 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:16:31.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:31.878 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:16:31.879 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:16:31.879 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:31.879 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:31.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:31.879 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:16:31.879 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:31.879 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:16:31.879 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:31.884 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:16:31.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:16:31.884 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:16:31.884 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:16:31.884 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:16:31.884 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.885 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:16:31.885 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:16:31.885 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:16:31.885 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:31.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:31.890 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:16:32.368 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:16:32.421 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:16:32.423 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:16:32.424 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:16:32.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:16:32.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:16:32.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:16:32.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:16:32.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:32.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:16:32.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:16:32.443 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:16:32.443 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:16:32.841 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:16:32.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:32.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:32.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:32.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:33.312 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:16:33.785 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:16:33.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:33.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:33.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:33.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:34.257 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:16:34.729 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:16:34.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:34.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:34.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:34.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:35.200 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:16:35.673 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:16:35.894 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:35.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:35.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:35.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:36.146 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:16:36.618 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:16:36.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:36.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:36.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:36.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:37.089 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:16:37.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:16:37.356 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:16:37.356 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:16:37.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:37.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:37.561 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:16:38.026 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:16:38.490 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:16:38.958 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:16:39.432 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:16:39.897 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:16:40.366 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:16:40.833 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:16:41.297 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:16:41.764 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:16:41.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:16:41.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:16:41.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:16:41.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:16:41.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:41.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:41.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:41.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:41.905 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:41.905 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:41.905 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:41.905 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:41.905 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:41.905 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:41.905 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:16:46.908 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:46.908 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:46.909 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:46.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:46.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:46.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:46.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:46.915 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:46.915 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:46.915 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:16:46.916 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:16:46.919 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:16:46.919 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:16:46.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:46.920 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:46.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:46.921 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:16:46.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:16:46.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:16:46.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:46.924 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:16:46.924 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:16:46.925 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:46.925 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:46.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:46.926 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:16:46.926 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:16:46.926 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:16:46.926 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:46.928 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:16:46.929 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:16:46.929 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:46.929 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:16:46.929 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:46.929 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:16:46.929 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:16:46.929 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:16:46.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:46.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:16:46.936 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:16:46.936 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:16:46.936 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:16:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:16:46.941 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:16:47.416 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:16:47.465 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:16:47.466 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:16:47.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:16:47.467 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:16:47.888 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:16:47.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:47.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:47.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:47.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:48.363 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:16:48.835 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:16:48.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:48.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:48.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:48.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:49.311 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:16:49.782 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:16:49.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:49.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:49.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:49.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:50.253 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:16:50.729 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:16:50.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:50.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:50.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:50.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:51.200 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:16:51.671 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:16:51.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:51.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:51.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:51.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:52.145 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:16:52.617 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:16:53.089 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:16:53.565 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:16:54.037 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:16:54.512 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:16:54.984 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:16:55.459 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:16:55.931 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:16:56.405 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:16:56.873 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:16:57.347 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:16:57.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:16:57.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:16:57.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:16:57.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:16:57.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:16:57.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:16:57.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:16:57.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:16:57.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:16:57.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:16:57.480 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:02.484 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:02.484 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:02.485 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:02.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:02.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:02.485 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:02.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:02.496 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:02.496 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:02.497 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:02.497 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:17:02.502 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:17:02.502 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:17:02.502 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:02.502 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:02.503 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:02.503 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:17:02.503 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:02.503 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:17:02.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:02.507 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:17:02.507 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:17:02.507 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:02.508 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:02.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:02.508 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:17:02.508 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:02.508 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:17:02.508 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:02.511 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:17:02.511 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:17:02.511 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:02.511 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:02.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:02.512 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:17:02.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:02.512 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:17:02.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:17:02.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:17:02.516 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:17:02.517 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:17:02.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:17:02.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:02.518 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:02.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:02.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:02.519 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:02.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:07.526 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:07.526 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:07.526 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:07.526 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:07.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:07.526 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:07.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:07.531 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:07.531 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:07.531 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:07.531 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:17:07.533 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:17:07.534 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:17:07.534 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:07.534 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:07.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:07.535 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:17:07.535 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:07.535 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:17:07.535 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:07.536 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:17:07.536 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:17:07.536 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:07.536 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:07.536 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:17:07.537 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:07.537 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:17:07.537 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:07.538 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:17:07.538 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:17:07.538 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:07.538 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:07.539 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:07.539 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:17:07.539 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:07.539 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:17:07.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:17:07.541 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:17:07.542 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:17:07.542 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:17:07.542 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.542 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:07.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:07.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:07.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:07.546 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:17:08.024 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:17:08.065 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:17:08.067 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:17:08.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:17:08.070 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:17:08.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:17:08.072 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:17:08.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:17:08.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:17:08.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:17:08.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:17:08.073 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:17:08.073 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:17:08.496 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:17:08.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:08.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:08.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:08.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:08.967 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:17:09.440 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:17:09.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:09.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:09.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:09.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:09.913 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:17:10.385 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:17:10.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:10.856 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:17:11.329 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:17:11.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:11.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:11.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:11.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:11.802 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:17:12.274 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:17:12.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:12.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:12.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:12.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:12.745 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:17:13.219 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:17:13.691 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:17:14.163 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:17:14.634 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:17:15.107 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:17:15.580 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:17:16.052 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:17:16.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:17:16.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:17:16.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:16.121 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:16.121 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:16.121 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:16.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:16.122 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:16.122 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:16.122 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:16.122 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:16.122 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:16.122 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:21.129 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:21.129 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:21.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:21.129 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:21.129 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:21.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:21.137 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:21.138 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:21.139 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:21.139 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:21.139 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:17:21.144 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:17:21.144 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:17:21.145 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:21.145 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:21.145 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:21.146 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:17:21.146 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:21.147 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:17:21.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:21.148 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:17:21.149 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:17:21.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:21.149 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:21.149 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:21.149 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:17:21.149 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:21.149 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:17:21.150 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:21.152 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:17:21.152 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:17:21.152 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:21.152 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:21.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:21.152 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:17:21.153 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:21.153 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:17:21.153 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:21.156 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:17:21.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:17:21.156 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:17:21.156 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:17:21.156 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:17:21.156 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:17:21.157 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:17:21.157 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:17:21.157 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.157 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.158 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.158 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.158 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.158 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:21.159 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:21.159 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:21.159 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:26.170 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:26.171 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:26.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:26.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:26.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:26.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:26.186 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:26.187 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:26.187 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:26.188 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:26.188 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:17:26.190 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:17:26.191 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:17:26.191 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:26.191 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:26.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:26.191 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:17:26.192 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:26.192 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:17:26.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:26.194 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:17:26.194 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:17:26.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:26.194 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:26.194 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:26.195 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:17:26.195 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:26.195 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:17:26.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:26.196 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:17:26.196 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:17:26.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:26.197 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:26.197 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:26.197 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:17:26.197 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:26.197 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:17:26.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.200 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:17:26.201 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:17:26.201 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:17:26.201 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:26.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:26.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:26.205 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:17:26.683 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:17:26.726 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:17:26.728 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:17:26.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:17:26.731 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:17:26.734 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:17:26.734 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:17:26.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:17:26.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:17:26.735 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:17:26.735 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:17:26.735 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:17:26.735 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:17:27.155 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:17:27.203 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:27.204 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:27.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:27.204 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:27.627 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:17:28.100 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:17:28.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:28.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:28.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:28.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:28.572 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:17:29.044 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:17:29.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:29.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:29.206 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:29.206 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:29.517 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:17:29.990 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:17:30.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:30.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:30.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:30.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:30.462 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:17:30.935 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:17:31.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:31.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:31.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:31.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:31.408 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:17:31.880 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:17:32.351 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:17:32.824 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:17:33.297 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:17:33.769 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:17:34.242 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:17:34.715 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:17:34.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:17:34.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:17:34.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:34.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:34.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:34.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:34.782 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:34.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:34.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:34.782 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:34.782 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:34.782 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:34.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:39.789 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:39.789 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:39.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:39.790 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:39.790 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:39.790 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:39.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:39.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:39.793 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:39.793 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:39.793 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:17:39.794 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:17:39.794 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:17:39.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:39.794 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:39.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:39.794 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:17:39.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:39.795 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:39.795 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:39.795 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:17:39.795 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:39.796 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:17:39.797 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:17:39.797 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:39.797 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:39.797 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:39.797 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:17:39.797 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:39.797 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:17:39.797 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:17:39.799 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:17:39.799 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:17:39.799 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:39.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.800 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:39.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:39.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:39.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:39.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:39.800 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:39.800 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:39.801 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:44.809 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:44.809 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:44.809 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:44.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:44.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:44.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:44.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:44.817 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:44.817 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:44.817 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:44.817 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:17:44.819 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:17:44.820 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:17:44.820 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:44.820 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:44.820 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:44.821 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:17:44.821 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:44.821 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:17:44.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:44.822 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:17:44.822 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:17:44.822 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:44.822 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:44.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:44.822 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:17:44.823 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:44.823 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:17:44.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:44.824 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:17:44.824 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:17:44.824 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:44.824 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:44.824 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:44.824 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:17:44.825 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:44.825 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:17:44.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:17:44.827 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:17:44.827 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:17:44.827 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:17:44.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:44.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:44.832 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:17:45.310 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:17:45.347 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:17:45.349 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:17:45.350 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:17:45.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:17:45.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:17:45.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:17:45.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:17:45.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:17:45.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:17:45.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:17:45.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:17:45.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:17:45.782 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:17:45.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:45.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:45.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:45.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:46.253 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:17:46.726 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:17:46.831 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:46.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:46.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:46.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:47.199 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:17:47.671 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:17:47.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:47.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:47.833 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:47.833 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:48.144 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:17:48.617 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:17:48.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:48.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:48.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:48.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:49.089 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:17:49.560 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:17:49.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:49.835 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:49.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:49.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:50.033 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:17:50.506 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:17:50.978 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:17:51.452 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:17:51.924 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:17:52.396 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:17:52.867 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:17:53.341 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:17:53.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:17:53.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:17:53.408 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:53.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:53.408 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:53.408 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:53.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:53.412 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:53.412 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:53.412 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:53.412 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:53.412 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:53.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:53.412 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:17:53.412 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:17:53.412 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:17:53.412 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:17:53.412 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:17:53.412 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:17:58.416 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:58.416 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:58.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:58.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:58.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:58.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:58.423 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:58.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:58.425 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:58.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:17:58.425 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:17:58.430 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:17:58.430 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:17:58.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:58.430 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:58.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:58.430 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:17:58.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:17:58.430 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:17:58.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:17:58.433 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:17:58.433 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:17:58.433 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:58.433 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:58.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:58.434 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:17:58.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:17:58.434 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:17:58.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:17:58.436 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:17:58.436 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:17:58.437 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:58.437 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:17:58.437 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:17:58.437 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:17:58.437 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:17:58.437 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:17:58.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.441 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:17:58.442 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:17:58.442 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.442 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:17:58.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:17:58.444 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:17:58.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:03.452 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:03.452 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:03.452 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:03.452 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:03.452 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:03.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:03.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:03.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:03.459 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:03.459 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:03.459 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:18:03.463 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:18:03.463 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:18:03.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:03.463 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:03.463 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:03.463 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:18:03.464 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:03.464 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:18:03.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:03.466 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:18:03.466 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:18:03.466 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:03.467 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:03.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:03.467 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:18:03.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:03.467 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:18:03.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:03.469 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:18:03.469 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:18:03.469 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:03.469 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:03.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:03.470 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:18:03.470 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:03.470 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:18:03.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.473 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:18:03.473 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:18:03.473 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:03.478 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:18:03.956 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:18:03.997 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:18:03.999 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:18:04.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:18:04.001 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:18:04.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:18:04.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:18:04.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:18:04.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:18:04.006 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:18:04.006 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:18:04.006 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:18:04.007 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:18:04.429 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:18:04.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:04.476 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:04.476 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:04.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:04.900 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:18:05.373 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:18:05.476 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:05.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:05.477 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:05.477 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:05.846 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:18:06.318 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:18:06.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:06.478 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:06.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:06.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:06.791 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:18:07.264 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:18:07.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:07.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:07.480 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:07.480 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:07.736 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:18:08.207 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:18:08.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:08.481 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:08.481 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:08.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:08.681 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:18:09.153 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:18:09.625 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:18:10.099 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:18:10.571 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:18:11.043 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:18:11.514 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:18:11.985 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:18:12.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:18:12.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:18:12.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:12.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:12.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:12.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:12.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:12.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:12.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:12.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:12.060 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:18:12.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:12.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:12.060 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:12.061 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:12.061 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:12.061 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:12.061 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:12.061 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:17.062 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:17.062 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:17.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:17.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:17.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:17.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:17.069 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:17.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:17.070 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:17.070 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:17.071 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:18:17.073 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:18:17.073 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:18:17.073 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:17.073 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:17.074 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:17.074 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:18:17.074 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:17.074 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:18:17.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:17.076 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:18:17.076 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:18:17.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:17.076 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:17.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:17.076 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:18:17.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:17.076 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:18:17.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:17.078 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:18:17.079 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:18:17.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:17.079 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:17.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:17.079 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:18:17.079 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:17.079 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:18:17.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.083 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:18:17.083 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:18:17.083 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:18:17.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.084 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:18:17.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.084 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:18:17.084 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.084 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.084 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.085 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:17.086 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:17.086 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:18:17.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:22.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:22.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:22.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:22.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:22.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:22.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:22.101 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:22.102 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:22.102 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:22.102 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:22.102 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:18:22.104 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:18:22.105 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:18:22.105 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:22.105 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:22.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:22.105 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:18:22.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:22.106 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:18:22.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:22.107 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:18:22.107 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:18:22.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:22.107 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:22.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:22.107 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:18:22.107 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:22.107 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:18:22.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:22.109 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:18:22.109 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:18:22.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:22.109 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:22.109 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:22.109 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:18:22.109 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:22.109 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:18:22.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:18:22.112 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:18:22.112 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.112 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:22.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:22.117 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:18:22.592 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:18:22.637 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:18:22.639 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:18:22.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:18:22.641 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:18:22.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:18:22.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:18:22.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:18:22.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:18:22.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:18:22.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:18:22.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:18:22.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:18:23.064 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:18:23.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:23.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:23.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:23.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:23.535 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:18:24.008 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:18:24.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:24.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:24.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:24.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:24.481 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:18:24.952 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:18:25.117 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:25.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:25.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:25.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:25.424 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:18:25.897 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:18:26.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:26.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:26.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:26.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:26.369 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:18:26.841 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:18:27.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:27.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:27.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:27.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:27.315 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:18:27.787 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:18:28.259 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:18:28.730 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:18:29.203 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:18:29.675 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:18:30.147 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:18:30.618 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:18:31.091 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:18:31.564 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:18:32.036 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:18:32.509 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:18:32.982 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:18:33.454 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:18:33.927 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:18:34.400 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:18:34.872 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:18:35.343 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:18:35.816 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:18:36.289 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:18:36.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:18:36.686 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:18:36.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:36.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:36.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:36.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:36.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:36.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:36.689 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:36.689 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:36.689 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:18:36.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:36.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:41.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:41.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:41.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:41.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:41.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:41.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:41.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:41.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:41.705 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:41.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:41.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:18:41.708 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:18:41.709 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:18:41.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:41.709 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:41.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:41.710 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:18:41.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:41.710 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:18:41.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:41.711 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:18:41.711 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:18:41.711 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:41.712 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:41.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:41.712 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:18:41.712 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:41.712 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:18:41.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:41.714 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:18:41.714 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:18:41.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:41.714 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:41.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:41.714 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:18:41.714 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:41.714 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:18:41.714 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:41.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:18:41.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:18:41.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:18:41.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:18:41.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:18:41.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:18:41.717 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:41.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:41.718 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:41.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:46.726 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:46.726 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:46.726 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:46.726 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:46.726 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:46.726 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:46.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:46.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:46.729 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:46.729 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:18:46.729 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:18:46.730 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:18:46.730 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:18:46.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:46.731 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:46.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:46.731 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:18:46.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:18:46.731 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:18:46.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:46.732 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:18:46.732 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:18:46.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:46.732 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:46.732 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:46.732 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:18:46.732 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:18:46.732 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:18:46.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:46.733 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:18:46.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:18:46.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:46.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:18:46.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:46.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:18:46.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:18:46.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:18:46.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:18:46.735 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:18:46.736 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:18:46.736 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:18:46.736 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:18:46.740 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:18:47.218 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:18:47.258 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:18:47.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:18:47.260 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:18:47.263 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:18:47.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:18:47.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:18:47.267 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:18:47.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:18:47.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:18:47.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:18:47.269 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:18:47.269 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:18:47.690 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:18:47.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:47.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:47.739 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:47.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:48.161 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:18:48.634 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:18:48.741 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:48.741 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:48.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:48.741 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:49.107 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:18:49.579 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:18:49.742 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:49.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:49.742 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:49.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:50.050 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:18:50.523 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:18:50.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:50.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:50.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:50.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:50.995 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:18:51.468 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:18:51.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:51.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:51.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:51.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:51.938 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:18:52.412 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:18:52.884 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:18:53.356 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:18:53.830 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:18:54.302 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:18:54.774 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:18:55.245 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:18:55.312 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:18:55.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:18:55.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:18:55.317 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:18:55.317 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:18:55.318 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:18:55.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:18:55.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:18:55.319 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:18:55.319 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:18:55.319 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:18:55.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:18:55.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:18:55.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:55.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:55.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:55.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:55.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:18:55.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:00.325 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:00.325 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:00.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:00.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:00.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:00.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:00.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:00.335 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:00.335 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:00.336 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:00.336 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:19:00.341 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:19:00.342 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:19:00.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:00.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:00.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:00.342 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:19:00.343 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:00.343 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:19:00.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:00.347 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:19:00.347 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:19:00.347 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:00.347 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:00.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:00.347 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:19:00.348 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:00.348 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:19:00.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:00.351 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:19:00.351 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:19:00.351 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:00.351 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:00.351 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:00.351 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:19:00.351 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:00.351 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:19:00.352 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:00.355 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:19:00.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:19:00.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:19:00.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:19:00.355 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:19:00.356 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:19:00.356 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:19:00.356 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.356 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:19:00.357 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.357 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.357 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:00.358 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:00.358 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:19:00.358 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:05.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:05.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:05.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:05.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:05.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:05.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:05.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:05.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:05.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:05.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:05.380 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:19:05.384 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:19:05.385 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:19:05.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:05.385 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:05.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:05.385 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:19:05.385 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:05.385 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:19:05.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:05.389 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:19:05.389 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:19:05.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:05.389 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:05.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:05.390 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:19:05.390 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:05.390 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:19:05.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:05.392 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:19:05.393 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:19:05.393 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:05.393 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:05.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:05.393 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:19:05.393 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:05.393 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:19:05.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.397 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:19:05.397 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:19:05.397 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:19:05.397 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:05.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:05.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:05.402 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:19:05.879 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:19:05.921 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:19:05.923 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:19:05.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:19:05.924 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:19:05.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:19:05.926 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:19:05.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:19:05.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:19:05.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:19:05.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:19:05.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:19:05.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:19:06.350 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:19:06.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:06.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:06.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:06.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:06.822 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:19:07.295 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:19:07.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:07.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:07.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:07.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:07.767 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:19:08.239 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:19:08.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:08.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:08.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:08.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:08.710 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:19:09.184 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:19:09.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:09.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:09.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:09.405 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:09.656 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:19:10.128 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:19:10.405 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:10.405 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:10.405 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:10.406 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:10.599 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:19:11.070 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:19:11.543 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:19:12.016 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:19:12.488 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:19:12.958 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:19:13.429 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:19:13.903 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:19:14.375 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:19:14.847 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:19:15.321 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:19:15.793 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:19:15.976 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:19:15.976 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:19:15.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:15.978 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:15.978 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:15.978 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:15.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:15.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:15.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:15.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:15.982 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:19:15.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:15.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:15.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:19:20.986 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:20.986 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:20.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:20.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:20.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:20.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:20.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:20.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:20.996 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:20.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:20.996 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:19:21.001 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:19:21.001 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:19:21.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:21.002 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:21.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:21.003 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:19:21.003 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:21.003 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:19:21.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:21.005 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:19:21.005 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:19:21.005 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:21.006 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:21.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:21.006 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:19:21.006 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:21.006 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:19:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:21.008 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:19:21.008 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:19:21.008 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:21.008 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:21.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:21.008 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:19:21.008 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:21.008 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:19:21.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:19:21.012 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:19:21.012 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:19:21.012 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:19:21.012 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:19:21.013 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.013 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.013 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:21.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:21.014 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:19:21.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:26.020 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:26.020 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:26.020 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:26.020 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:26.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:26.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:26.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:26.030 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:26.031 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:26.031 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:26.031 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:19:26.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:19:26.037 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:19:26.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:26.037 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:26.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:26.037 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:19:26.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:26.038 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:19:26.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:26.041 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:19:26.042 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:19:26.042 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:26.042 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:26.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:26.042 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:19:26.042 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:26.042 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:19:26.043 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:26.045 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:19:26.045 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:19:26.045 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:26.045 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:26.046 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:26.046 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:19:26.046 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:26.046 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:19:26.046 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:19:26.050 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:19:26.050 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:19:26.050 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.050 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:26.052 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:26.055 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:19:26.532 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:19:26.571 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:19:26.572 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:19:26.573 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:19:26.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:19:26.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:19:26.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:19:26.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:19:26.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:19:26.575 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:19:26.575 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:19:26.575 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:19:26.575 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:19:27.004 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:19:27.054 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:27.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:27.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:27.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:27.476 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:19:27.949 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:19:28.056 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:28.056 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:28.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:28.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:28.421 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:19:28.893 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:19:29.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:29.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:29.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:29.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:29.364 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:19:29.838 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:19:30.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:30.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:30.060 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:30.060 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:30.310 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:19:30.782 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:19:31.060 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:31.060 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:31.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:31.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:31.253 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:19:31.727 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:19:32.199 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:19:32.671 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:19:33.142 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:19:33.613 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:19:34.086 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:19:34.559 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:19:35.031 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:19:35.502 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:19:35.975 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:19:36.448 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:19:36.920 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:19:37.391 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:19:37.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:19:37.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:19:37.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:37.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:37.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:37.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:37.633 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:37.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:37.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:37.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:37.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:37.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:37.634 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:19:42.639 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:42.639 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:42.639 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:42.639 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:42.639 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:42.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:42.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:42.647 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:42.647 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:42.648 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:42.648 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:19:42.650 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:19:42.650 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:19:42.650 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:42.650 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:42.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:42.651 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:19:42.651 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:42.651 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:19:42.651 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:42.652 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:19:42.652 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:19:42.652 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:42.652 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:42.653 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:42.653 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:19:42.653 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:42.653 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:19:42.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:42.654 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:19:42.654 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:19:42.654 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:42.654 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:42.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:42.655 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:19:42.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:42.655 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:19:42.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.657 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:19:42.657 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:19:42.657 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:19:42.658 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.658 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:42.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:42.659 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:19:42.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:47.667 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:19:47.667 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:19:47.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:47.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:47.667 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:47.667 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:47.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:19:47.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:47.675 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:47.676 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:19:47.676 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:19:47.678 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:19:47.678 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:19:47.678 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:47.678 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:47.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:19:47.679 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:19:47.679 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:19:47.679 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:19:47.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:47.680 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:19:47.680 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:19:47.680 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:47.680 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:47.680 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:19:47.681 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:19:47.681 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:19:47.681 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:19:47.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:47.682 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:19:47.682 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:19:47.682 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:47.683 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:19:47.683 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:19:47.683 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:19:47.683 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:19:47.683 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:19:47.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:19:47.685 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:19:47.686 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:19:47.686 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:19:47.686 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:19:47.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:19:47.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:19:47.690 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:19:48.168 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:19:48.208 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:19:48.209 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:19:48.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:19:48.210 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:19:48.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:19:48.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:19:48.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:19:48.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:19:48.212 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:19:48.212 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:19:48.212 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:19:48.213 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:19:48.640 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:19:48.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:48.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:48.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:48.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:49.112 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:19:49.585 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:19:49.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:49.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:49.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:49.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:50.058 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:19:50.530 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:19:50.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:50.692 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:50.692 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:50.692 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:51.001 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:19:51.474 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:19:51.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:51.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:51.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:51.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:51.947 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:19:52.418 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:19:52.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:19:52.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:19:52.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:19:52.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:19:52.889 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:19:53.363 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:19:53.835 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:19:54.307 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:19:54.781 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:19:55.253 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:19:55.725 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:19:56.198 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:19:56.671 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:19:57.143 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:19:57.616 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:19:58.089 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:19:58.561 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:19:59.032 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:19:59.506 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:19:59.978 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:20:00.450 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:20:00.921 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:20:01.394 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:20:01.867 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:20:02.339 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:20:02.810 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:20:03.283 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:20:03.755 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:20:04.228 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:20:04.701 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:20:05.173 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:20:05.645 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:20:06.116 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:20:06.587 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:20:07.061 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:20:07.533 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:20:08.005 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:20:08.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:20:08.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:20:08.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:08.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:08.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:08.273 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:08.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:08.274 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:08.274 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:08.274 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:08.274 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:08.274 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:08.274 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:20:13.280 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:13.280 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:13.281 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:13.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:13.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:13.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:13.289 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:13.290 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:13.290 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:13.291 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:13.291 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:20:13.294 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:20:13.295 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:20:13.295 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:13.295 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:13.296 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:13.296 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:20:13.296 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:13.297 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:20:13.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:13.298 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:20:13.298 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:20:13.299 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:13.299 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:13.299 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:13.299 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:20:13.299 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:13.299 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:20:13.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:13.301 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:20:13.301 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:20:13.302 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:13.302 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:13.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:13.302 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:20:13.302 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:13.302 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:20:13.302 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:13.305 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:20:13.305 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:20:13.305 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:20:13.305 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:20:13.305 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:20:13.306 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:20:13.306 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:20:13.306 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.306 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:20:13.307 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.307 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.307 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:13.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:13.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:13.308 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:20:18.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:18.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:18.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:18.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:18.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:18.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:18.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:18.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:18.324 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:18.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:18.325 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:20:18.327 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:20:18.328 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:20:18.328 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:18.328 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:18.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:18.329 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:20:18.329 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:18.329 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:20:18.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:18.330 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:20:18.330 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:20:18.330 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:18.330 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:18.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:18.330 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:20:18.331 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:18.331 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:20:18.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:18.333 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:20:18.333 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:20:18.333 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:18.333 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:18.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:18.333 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:20:18.333 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:18.333 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:20:18.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:20:18.336 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:20:18.336 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:20:18.336 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:20:18.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:18.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:18.341 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:20:18.820 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:20:18.862 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:20:18.864 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:20:18.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:20:18.866 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:20:19.290 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:20:19.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:19.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:19.339 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:19.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:19.762 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:20:20.225 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:20:20.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:20.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:20.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:20.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:20.689 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:20:21.152 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:20:21.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:21.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:21.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:21.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:21.623 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:20:22.090 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:20:22.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:22.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:22.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:22.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:22.561 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:20:23.025 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:20:23.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:23.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:23.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:23.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:23.497 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:20:23.968 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:20:24.438 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:20:24.906 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:20:25.377 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:20:25.840 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:20:26.304 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:20:26.775 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:20:27.250 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:20:27.717 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:20:28.181 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:20:28.649 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:20:28.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:28.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:28.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:28.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:28.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:28.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:28.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:28.876 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:20:28.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:28.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:28.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:28.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:28.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:28.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:28.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:28.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:28.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:33.883 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:33.883 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:33.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:33.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:33.883 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:33.883 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:33.893 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:33.893 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:33.894 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:33.894 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:33.894 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:20:33.896 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:20:33.896 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:20:33.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:33.896 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:33.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:33.896 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:20:33.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:33.896 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:20:33.897 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:33.898 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:20:33.898 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:20:33.898 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:33.898 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:33.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:33.898 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:20:33.898 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:33.898 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:20:33.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:33.900 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:20:33.900 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:20:33.900 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:33.900 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:33.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:33.900 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:20:33.900 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:33.900 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:20:33.900 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:20:33.902 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:20:33.902 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:20:33.902 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:33.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:33.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:33.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:33.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:33.904 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:33.904 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:33.904 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:20:38.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:38.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:38.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:38.912 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:38.912 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:38.912 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:38.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:38.920 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:38.920 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:38.921 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:38.921 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:20:38.924 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:20:38.924 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:20:38.924 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:38.925 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:38.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:38.925 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:20:38.926 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:38.926 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:20:38.926 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:38.927 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:20:38.927 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:20:38.927 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:38.927 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:38.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:38.928 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:20:38.928 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:38.928 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:20:38.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:38.930 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:20:38.930 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:20:38.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:38.930 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:38.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:38.930 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:20:38.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:38.930 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:20:38.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:20:38.934 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:20:38.934 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:20:38.934 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:38.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:38.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:38.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:38.938 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:20:39.416 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:20:39.459 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:20:39.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:20:39.463 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:20:39.464 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:20:39.888 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:20:39.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:39.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:39.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:39.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:40.364 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:20:40.836 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:20:40.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:40.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:40.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:40.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:41.311 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:20:41.783 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:20:41.940 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:41.940 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:41.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:41.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:42.257 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:20:42.729 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:20:42.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:42.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:42.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:42.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:43.201 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:20:43.676 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:20:43.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:43.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:43.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:43.944 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:44.148 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:20:44.624 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:20:45.095 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:20:45.571 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:20:46.045 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:20:46.518 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:20:46.990 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:20:47.465 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:20:47.937 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:20:48.411 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:20:48.883 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:20:49.355 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:20:49.831 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:20:50.302 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:20:50.778 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:20:51.249 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:20:51.478 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:51.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:51.479 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:51.479 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:51.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:51.480 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:51.480 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:51.480 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:20:51.480 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:51.480 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:51.480 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:51.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2704 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:51.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2704 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:51.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2704 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:51.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2704 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:51.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2704 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:51.480 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2704 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:20:56.487 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:56.487 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:56.487 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:56.487 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:56.487 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:56.487 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:56.490 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:56.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:56.490 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:56.490 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:20:56.490 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:20:56.491 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:20:56.491 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:20:56.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:56.492 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:56.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:56.492 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:20:56.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:20:56.492 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:20:56.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:20:56.493 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:20:56.493 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:20:56.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:56.493 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:56.493 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:56.493 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:20:56.493 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:20:56.493 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:20:56.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:20:56.494 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:20:56.494 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:20:56.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:56.494 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:20:56.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:56.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:20:56.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:20:56.494 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:20:56.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.496 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:20:56.496 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:20:56.496 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:20:56.496 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:20:56.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:20:56.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:20:56.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:20:56.498 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:20:56.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:20:56.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:20:56.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:20:56.498 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:21:01.506 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:01.506 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:01.506 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:01.506 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:01.506 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:01.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:01.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:01.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:01.513 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:01.513 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:01.514 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:21:01.517 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:21:01.517 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:21:01.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:01.518 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:01.518 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:01.518 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:21:01.518 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:01.519 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:21:01.519 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:01.520 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:21:01.520 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:21:01.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:01.521 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:01.521 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:01.521 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:21:01.521 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:01.521 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:21:01.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:01.522 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:21:01.523 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:21:01.523 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:01.523 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:01.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:01.523 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:21:01.523 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:01.523 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:21:01.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:21:01.526 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:21:01.526 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:21:01.526 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:21:01.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:01.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:01.531 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:21:02.008 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:21:02.048 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:21:02.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:21:02.052 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:21:02.055 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:21:02.058 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:21:02.058 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:21:02.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:21:02.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:02.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:02.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:02.059 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:21:02.059 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:21:02.098 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:02.098 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:02.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:02.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:02.480 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:21:02.528 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:02.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:02.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:02.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:02.952 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:21:03.423 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:21:03.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:03.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:03.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:03.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:03.896 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:21:04.368 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:21:04.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:04.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:04.531 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:04.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:04.840 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:21:05.311 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:21:05.531 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:05.532 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:05.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:05.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:05.784 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:21:06.256 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:21:06.533 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:06.533 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:06.533 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:06.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:06.729 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:21:07.200 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:21:07.673 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:21:08.145 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:21:08.617 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:21:09.088 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:21:09.561 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:21:10.034 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:21:10.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:21:10.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:21:10.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:10.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:10.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:10.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:10.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:10.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:10.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:10.106 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:10.106 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:10.106 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:21:10.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:15.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:15.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:15.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:15.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:15.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:15.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:15.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:15.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:15.123 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:15.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:15.124 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:21:15.127 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:21:15.127 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:21:15.128 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:15.128 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:15.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:15.129 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:21:15.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:15.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:21:15.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:15.131 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:21:15.131 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:21:15.132 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:15.132 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:15.132 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:15.132 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:21:15.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:15.133 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:21:15.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:15.134 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:21:15.135 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:21:15.135 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:15.135 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:15.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:15.135 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:21:15.135 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:15.135 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:21:15.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:15.138 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:21:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:21:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:21:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:21:15.138 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:21:15.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:21:15.139 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:21:15.139 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:21:15.139 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.139 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:15.140 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:15.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:15.141 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:21:15.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:20.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:20.147 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:20.147 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:20.147 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:20.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:20.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:20.159 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:20.160 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:20.160 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:20.161 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:20.161 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:21:20.163 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:21:20.163 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:21:20.164 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:20.164 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:20.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:20.164 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:21:20.164 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:20.165 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:21:20.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:20.166 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:21:20.166 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:21:20.166 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:20.166 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:20.166 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:20.166 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:21:20.166 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:20.166 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:21:20.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:20.168 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:21:20.168 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:21:20.168 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:20.168 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:20.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:20.168 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:21:20.168 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:20.168 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:21:20.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:21:20.171 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:21:20.171 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:21:20.171 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:20.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:20.176 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:21:20.654 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:21:20.692 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:21:20.693 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:21:20.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:21:20.694 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:21:20.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:21:20.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:21:20.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:21:20.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:20.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:20.696 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:20.696 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:21:20.696 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:21:20.697 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:20.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:20.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:20.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:21.126 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:21:21.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:21.174 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:21.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:21.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:21.598 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:21:22.068 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:21:22.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:22.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:22.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:22.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:22.541 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:21:23.014 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:21:23.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:23.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:23.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:23.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:23.486 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:21:23.957 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:21:24.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:24.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:24.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:24.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:24.430 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:21:24.903 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:21:25.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:25.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:25.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:25.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:25.375 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:21:25.848 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:21:26.320 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:21:26.792 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:21:27.263 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:21:27.737 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:21:28.209 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:21:28.681 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:21:28.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:21:28.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:21:28.706 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:28.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:28.707 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:28.707 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:28.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:28.709 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:28.709 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:28.709 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:21:28.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:28.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:28.709 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:28.710 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1844 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:28.710 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1844 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:28.710 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1844 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:28.710 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1844 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:28.710 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1844 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:28.710 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1844 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:33.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:33.713 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:33.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:33.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:33.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:33.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:33.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:33.724 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:33.724 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:33.725 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:33.725 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:21:33.730 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:21:33.730 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:21:33.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:33.731 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:33.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:33.731 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:21:33.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:33.731 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:21:33.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:33.735 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:21:33.735 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:21:33.735 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:33.736 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:33.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:33.736 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:21:33.736 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:33.736 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:21:33.736 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:33.739 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:21:33.739 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:21:33.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:33.739 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:33.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:33.739 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:21:33.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:33.739 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:21:33.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:33.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:21:33.744 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:21:33.744 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:21:33.744 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:33.745 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:33.745 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:33.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.751 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:38.751 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:38.751 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:38.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:38.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:38.751 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:38.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:38.762 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:38.762 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:38.763 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:38.763 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:21:38.767 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:21:38.767 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:21:38.767 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:38.767 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:38.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:38.768 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:21:38.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:38.769 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:21:38.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:38.771 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:21:38.771 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:21:38.772 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:38.772 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:38.772 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:38.773 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:21:38.773 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:38.773 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:21:38.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:38.774 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:21:38.775 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:21:38.775 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:38.775 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:38.775 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:38.775 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:21:38.775 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:38.775 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:21:38.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:38.778 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:21:38.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:21:38.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:21:38.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.779 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:21:38.779 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:21:38.779 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:21:38.779 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:38.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:38.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:38.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:38.784 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:21:39.263 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:21:39.305 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:21:39.307 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:21:39.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:21:39.308 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:21:39.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:21:39.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:21:39.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:21:39.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:39.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:39.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:39.310 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:21:39.310 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:21:39.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:39.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:39.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:39.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:39.734 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:21:39.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:39.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:39.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:39.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:40.206 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:21:40.679 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:21:40.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:40.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:40.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:40.783 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:41.152 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:21:41.624 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:21:41.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:41.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:41.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:41.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:42.095 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:21:42.568 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:21:42.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:42.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:42.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:42.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:43.041 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:21:43.513 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:21:43.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:43.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:43.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:43.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:43.984 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:21:44.454 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:21:44.928 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:21:45.399 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:21:45.872 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:21:46.345 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:21:46.817 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:21:47.289 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:21:47.358 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:21:47.358 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:21:47.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:47.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:47.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:47.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:47.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:47.367 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:47.367 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:47.367 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:21:47.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:47.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:47.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:47.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:47.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:47.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:47.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:47.369 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:47.369 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:21:52.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:52.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:52.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:52.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:52.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:52.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:52.377 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:52.377 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:52.377 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:52.378 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:52.378 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:21:52.381 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:21:52.381 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:21:52.381 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:52.381 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:52.381 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:52.381 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:21:52.382 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:52.382 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:21:52.382 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:52.386 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:21:52.386 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:21:52.386 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:52.386 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:52.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:52.386 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:21:52.387 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:52.387 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:21:52.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:52.390 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:21:52.390 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:21:52.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:52.391 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:52.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:52.391 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:21:52.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:52.391 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:21:52.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:52.396 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:21:52.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.398 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:21:52.398 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:21:52.398 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:21:52.398 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:21:52.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.398 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.398 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:21:52.398 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.399 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.399 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:52.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:52.401 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:21:52.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:57.407 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:21:57.407 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:21:57.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:57.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:57.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:57.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:57.414 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:21:57.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:57.416 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:57.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:21:57.416 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:21:57.419 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:21:57.419 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:21:57.419 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:57.419 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:57.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:21:57.420 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:21:57.420 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:21:57.420 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:21:57.421 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:57.422 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:21:57.422 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:21:57.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:57.422 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:57.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:21:57.422 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:21:57.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:21:57.422 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:21:57.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:57.424 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:21:57.424 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:21:57.424 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:57.424 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:21:57.424 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:21:57.424 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:21:57.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:21:57.425 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:21:57.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.427 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:21:57.428 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:21:57.428 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:21:57.428 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:21:57.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:21:57.432 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:21:57.911 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:21:57.950 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:21:57.952 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:21:57.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:21:57.955 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:21:57.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:21:57.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:21:57.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:21:57.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:57.960 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:57.960 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:57.960 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:21:57.960 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:21:58.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:21:58.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:21:58.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:58.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:21:58.382 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:21:58.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:58.430 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:58.430 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:58.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:58.854 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:21:59.325 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:21:59.430 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:21:59.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:21:59.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:21:59.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:21:59.798 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:22:00.270 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:22:00.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:00.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:00.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:00.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:00.742 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:22:01.213 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:22:01.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:01.433 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:01.686 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:22:02.159 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:22:02.433 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:02.434 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:02.434 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:02.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:02.631 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:22:03.102 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:22:03.575 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:22:04.048 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:22:04.520 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:22:04.991 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:22:05.464 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:22:05.936 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:22:06.005 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:22:06.005 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:22:06.010 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:06.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:06.010 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:06.010 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:06.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:06.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:06.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:06.014 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:22:06.015 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:06.015 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:06.015 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:06.015 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:06.015 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:06.016 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:06.016 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:06.016 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:06.016 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:11.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:11.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:11.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:11.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:11.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:11.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:11.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:11.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:11.027 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:11.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:11.027 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:22:11.029 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:22:11.030 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:22:11.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:11.030 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:11.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:11.031 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:22:11.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:11.031 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:22:11.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:11.032 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:22:11.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:22:11.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:11.033 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:11.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:11.033 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:22:11.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:11.033 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:22:11.033 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:11.035 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:22:11.035 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:22:11.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:11.036 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:11.036 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:11.036 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:22:11.036 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:11.036 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:22:11.036 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:11.039 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:22:11.039 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:22:11.039 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:22:11.039 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:22:11.039 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:22:11.040 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:22:11.040 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:22:11.040 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.040 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:22:11.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:11.042 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:11.042 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:11.042 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:22:16.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:16.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:16.050 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:16.050 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:16.050 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:16.050 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:16.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:16.058 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:16.059 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:16.059 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:16.059 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:22:16.061 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:22:16.062 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:22:16.062 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:16.062 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:16.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:16.063 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:22:16.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:16.063 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:22:16.063 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:16.064 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:22:16.064 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:22:16.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:16.065 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:16.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:16.065 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:22:16.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:16.065 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:22:16.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:16.066 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:22:16.066 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:22:16.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:16.067 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:16.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:16.067 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:22:16.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:16.067 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:22:16.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:22:16.070 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:22:16.070 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:22:16.070 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:16.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:16.074 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:22:16.553 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:22:16.592 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:22:16.594 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:22:16.596 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:22:16.596 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:22:16.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:22:16.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:22:16.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:22:16.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:22:16.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:22:16.600 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:22:16.600 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:22:16.600 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:22:16.642 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:22:16.643 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:22:16.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:22:16.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:22:17.025 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:22:17.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:17.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:17.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:17.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:17.496 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:22:17.967 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:22:18.072 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:18.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:18.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:18.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:18.440 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:22:18.913 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:22:19.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:19.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:19.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:19.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:19.384 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:22:19.855 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:22:20.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:20.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:20.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:20.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:20.326 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:22:20.799 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:22:21.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:21.077 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:21.077 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:21.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:21.272 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:22:21.744 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:22:22.215 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:22:22.689 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:22:23.161 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:22:23.633 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:22:24.106 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:22:24.579 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:22:25.051 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:22:25.522 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:22:25.995 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:22:26.467 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:22:26.939 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:22:27.410 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:22:27.884 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:22:28.356 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:22:28.828 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:22:29.299 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:22:29.772 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:22:30.245 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:22:30.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:22:30.648 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:22:30.649 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:30.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:30.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:30.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:30.650 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:30.650 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:30.650 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:30.650 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:30.650 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:22:30.650 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:30.650 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:35.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:35.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:35.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:35.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:35.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:35.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:35.663 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:35.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:35.665 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:35.665 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:35.665 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:22:35.670 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:22:35.670 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:22:35.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:35.671 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:35.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:35.672 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:22:35.672 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:35.673 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:22:35.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:35.675 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:22:35.676 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:22:35.676 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:35.676 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:35.677 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:35.677 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:22:35.678 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:35.678 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:22:35.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:35.680 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:22:35.681 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:22:35.681 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:35.681 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:35.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:35.681 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:22:35.682 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:35.682 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:22:35.682 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:35.686 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:22:35.688 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:22:35.688 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:22:35.688 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:35.690 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:35.690 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:22:35.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:40.697 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:40.697 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:40.697 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:40.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:40.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:40.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:40.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:40.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:40.705 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:40.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:40.705 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:22:40.708 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:22:40.709 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:22:40.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:40.709 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:40.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:40.710 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:22:40.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:40.710 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:22:40.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:40.712 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:22:40.713 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:22:40.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:40.713 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:40.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:40.714 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:22:40.714 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:40.714 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:22:40.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:40.716 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:22:40.716 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:22:40.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:40.717 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:40.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:40.717 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:22:40.717 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:40.717 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:22:40.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:22:40.722 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:22:40.723 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:22:40.723 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:22:40.723 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:40.724 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:40.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:40.728 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:22:41.206 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:22:41.247 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:22:41.249 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:22:41.250 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:22:41.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:22:41.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:22:41.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:22:41.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:22:41.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:22:41.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:22:41.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:22:41.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:22:41.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:22:41.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:22:41.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:22:41.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:22:41.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:22:41.678 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:22:41.726 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:41.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:41.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:41.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:42.150 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:22:42.623 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:22:42.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:42.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:42.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:42.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:43.096 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:22:43.567 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:22:43.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:43.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:43.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:43.730 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:44.039 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:22:44.512 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:22:44.730 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:44.730 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:44.730 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:44.731 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:44.984 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:22:45.456 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:22:45.731 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:45.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:45.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:45.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:45.927 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:22:46.401 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:22:46.873 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:22:47.345 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:22:47.816 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:22:48.287 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:22:48.761 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:22:49.233 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:22:49.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:22:49.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:22:49.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:49.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:49.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:49.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:49.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:49.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:49.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:49.308 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:22:49.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:49.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:49.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:49.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:49.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:49.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:49.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:49.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:49.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:49.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:22:54.314 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:54.314 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:54.314 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:54.314 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:54.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:54.314 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:54.323 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:54.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:54.324 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:54.324 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:54.324 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:22:54.328 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:22:54.328 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:22:54.328 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:54.328 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:54.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:54.329 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:22:54.329 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:54.329 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:22:54.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:54.332 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:22:54.332 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:22:54.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:54.332 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:54.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:54.332 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:22:54.332 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:54.333 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:22:54.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:54.335 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:22:54.335 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:22:54.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:54.335 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:54.335 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:54.335 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:22:54.335 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:54.335 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:22:54.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:54.338 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:22:54.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:22:54.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:22:54.339 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:22:54.339 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:22:54.339 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:54.341 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:54.341 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:22:54.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:59.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:22:59.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:22:59.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:59.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:59.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:59.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:59.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:22:59.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:59.363 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:59.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:22:59.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:22:59.366 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:22:59.366 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:22:59.366 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:59.366 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:59.366 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:22:59.366 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:22:59.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:22:59.367 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:22:59.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:22:59.368 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:22:59.368 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:22:59.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:59.368 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:59.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:22:59.368 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:22:59.368 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:22:59.368 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:22:59.368 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:22:59.369 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:22:59.370 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:22:59.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:59.370 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:22:59.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:22:59.370 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:22:59.370 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:22:59.370 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:22:59.370 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:22:59.372 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:22:59.372 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:22:59.372 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:22:59.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:22:59.377 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:22:59.854 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:22:59.885 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:22:59.886 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:22:59.887 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:22:59.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:22:59.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:22:59.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:22:59.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:22:59.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:22:59.888 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:22:59.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:22:59.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:22:59.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:23:00.325 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:23:00.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:00.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:00.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:00.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:00.797 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:23:01.269 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:23:01.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:01.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:01.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:01.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:01.740 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:23:02.213 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:23:02.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:02.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:02.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:02.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:02.686 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:23:03.158 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:23:03.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:03.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:03.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:03.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:03.631 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:23:04.104 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:23:04.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:04.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:04.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:04.380 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:04.575 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:23:05.047 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:23:05.517 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:23:05.991 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:23:06.463 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:23:06.935 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:23:07.406 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:23:07.880 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:23:08.352 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:23:08.824 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:23:09.295 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:23:09.768 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:23:09.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:23:09.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:23:09.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:09.909 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:09.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:09.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:09.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:09.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:09.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:09.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:09.913 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:09.913 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:09.913 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:23:09.914 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2278 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:23:09.914 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2278 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:23:09.914 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2278 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:23:09.914 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2278 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:23:09.914 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2278 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:23:09.914 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2278 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:23:14.916 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:14.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:14.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:14.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:14.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:14.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:14.921 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:14.922 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:14.922 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:14.922 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:14.922 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:23:14.925 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:23:14.925 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:23:14.925 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:14.926 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:14.926 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:14.926 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:23:14.926 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:14.927 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:23:14.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:14.928 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:23:14.928 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:23:14.928 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:14.928 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:14.928 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:14.928 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:23:14.928 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:14.928 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:23:14.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:14.930 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:23:14.930 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:23:14.930 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:14.930 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:14.930 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:14.930 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:23:14.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:14.931 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:23:14.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:14.933 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:23:14.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:23:14.933 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:23:14.933 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:23:14.933 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:23:14.933 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:23:14.934 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:23:14.934 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:23:14.934 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:14.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:14.935 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:23:14.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:19.943 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:19.943 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:19.943 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:19.943 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:19.943 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:19.943 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:19.951 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:19.951 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:19.952 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:19.952 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:19.952 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:23:19.954 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:23:19.955 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:23:19.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:19.955 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:19.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:19.955 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:23:19.956 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:19.956 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:23:19.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:19.957 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:23:19.957 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:23:19.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:19.957 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:19.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:19.957 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:23:19.957 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:19.957 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:23:19.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:19.959 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:23:19.959 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:23:19.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:19.959 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:19.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:19.959 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:23:19.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:19.959 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:23:19.960 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.962 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:23:19.962 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:23:19.962 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:23:19.962 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:19.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:19.967 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:23:20.445 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:23:20.486 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:23:20.487 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:23:20.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:23:20.488 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:23:20.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:23:20.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:23:20.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:23:20.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:23:20.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:23:20.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:23:20.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:23:20.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:23:20.535 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:23:20.535 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:23:20.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:23:20.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:23:20.917 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:23:20.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:20.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:20.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:20.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:21.388 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:23:21.861 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:23:21.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:21.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:21.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:21.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:22.334 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:23:22.806 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:23:22.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:22.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:22.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:22.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:23.277 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:23:23.750 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:23:23.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:23.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:23.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:23.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:24.223 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:23:24.695 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:23:24.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:24.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:24.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:24.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:25.166 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:23:25.639 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:23:26.112 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:23:26.584 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:23:27.055 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:23:27.528 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:23:28.001 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:23:28.473 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:23:28.946 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:23:29.419 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:23:29.891 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:23:30.362 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:23:30.835 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:23:31.308 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:23:31.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:23:31.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:23:31.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:31.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:31.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:31.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:31.543 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:31.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:31.543 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:31.543 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:31.543 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:23:36.549 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:36.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:36.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:36.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:36.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:36.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:36.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:36.559 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:36.559 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:36.559 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:36.559 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:23:36.562 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:23:36.562 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:23:36.563 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:36.563 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:36.563 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:36.563 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:23:36.563 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:36.563 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:23:36.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:36.567 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:23:36.567 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:23:36.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:36.567 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:36.568 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:36.568 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:23:36.568 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:36.568 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:23:36.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:36.572 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:23:36.572 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:23:36.572 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:36.572 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:36.572 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:36.572 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:23:36.573 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:36.573 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:23:36.573 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:36.578 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:23:36.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:23:36.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:23:36.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:23:36.578 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:23:36.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:23:36.579 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:23:36.579 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:23:36.579 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:23:36.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:36.582 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:36.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.582 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:36.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:36.582 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:36.582 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:36.582 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:36.582 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:23:41.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:41.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:41.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:41.589 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:41.589 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:41.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:41.596 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:41.597 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:41.597 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:41.598 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:41.598 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:23:41.602 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:23:41.603 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:23:41.603 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:41.603 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:41.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:41.604 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:23:41.604 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:41.605 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:23:41.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:41.606 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:23:41.606 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:23:41.607 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:41.607 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:41.607 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:41.607 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:23:41.607 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:41.607 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:23:41.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:41.610 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:23:41.610 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:23:41.610 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:41.610 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:41.611 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:41.611 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:23:41.611 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:41.611 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:23:41.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:23:41.614 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:23:41.614 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:23:41.614 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.614 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:41.615 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:41.619 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:23:42.096 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:23:42.136 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:23:42.138 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:23:42.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:23:42.139 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:23:42.568 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:23:42.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:42.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:42.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:42.618 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:43.043 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:23:43.515 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:23:43.619 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:43.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:43.619 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:43.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:43.988 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:23:44.461 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:23:44.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:44.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:44.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:44.621 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:44.933 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:23:45.407 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:23:45.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:45.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:45.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:45.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:45.879 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:23:46.351 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:23:46.623 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:46.623 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:46.624 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:46.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:46.825 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:23:47.297 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:23:47.769 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:23:48.244 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:23:48.716 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:23:49.191 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:23:49.663 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:23:50.139 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:23:50.610 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:23:51.085 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:23:51.556 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:23:52.028 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:23:52.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:52.149 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:52.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:52.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:52.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:52.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:52.151 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:52.151 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:52.151 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:52.151 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:52.151 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:23:57.156 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:57.156 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:57.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:57.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:57.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:57.166 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:57.166 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:57.167 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:23:57.167 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:23:57.171 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:23:57.171 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:23:57.171 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:57.172 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:57.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:57.172 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:23:57.173 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:23:57.173 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:23:57.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:23:57.174 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:23:57.175 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:23:57.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:57.175 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:57.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:57.175 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:23:57.175 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:23:57.175 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:23:57.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:23:57.177 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:23:57.177 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:23:57.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:57.177 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:23:57.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:23:57.177 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:23:57.177 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:23:57.177 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:23:57.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:23:57.182 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:23:57.182 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:23:57.182 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:23:57.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:23:57.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:23:57.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:23:57.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:23:57.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:23:57.183 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:23:57.184 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:02.192 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:02.192 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:02.192 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:02.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:02.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:02.192 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:02.199 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:02.200 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:02.201 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:02.201 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:02.201 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:24:02.203 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:24:02.203 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:24:02.204 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:02.204 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:02.204 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:02.204 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:24:02.205 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:02.205 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:24:02.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:02.207 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:24:02.207 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:24:02.207 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:02.207 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:02.208 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:02.208 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:24:02.208 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:02.208 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:24:02.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:02.211 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:24:02.211 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:24:02.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:02.212 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:02.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:02.212 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:24:02.212 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:02.212 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:24:02.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:24:02.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:24:02.219 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:24:02.219 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:24:02.219 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:02.224 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:24:02.702 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:24:02.755 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:24:02.757 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:24:02.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:24:02.760 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:24:03.174 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:24:03.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:03.224 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:03.224 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:03.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:03.650 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:24:04.122 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:24:04.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:04.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:04.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:04.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:04.597 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:24:05.069 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:24:05.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:05.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:05.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:05.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:05.544 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:24:06.016 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:24:06.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:06.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:06.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:06.228 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:06.491 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:24:06.966 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:24:07.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:07.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:07.229 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:07.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:07.439 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:24:07.911 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:24:08.386 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:24:08.859 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:24:09.333 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:24:09.807 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:24:10.280 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:24:10.752 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:24:11.223 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:24:11.697 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:24:12.169 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:24:12.641 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:24:13.112 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:24:13.583 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:24:14.057 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:24:14.529 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:24:14.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:14.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:14.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:14.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:14.779 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:14.779 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:14.779 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:14.779 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:14.779 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:24:14.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:14.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:14.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:14.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:14.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:14.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:14.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:14.779 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:19.784 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:19.784 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:19.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:19.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:19.784 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:19.784 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:19.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:19.796 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:19.796 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:19.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:19.797 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:24:19.802 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:24:19.803 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:24:19.803 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:19.803 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:19.804 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:19.804 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:24:19.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:19.805 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:24:19.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:19.808 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:24:19.808 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:24:19.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:19.809 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:19.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:19.810 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:24:19.810 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:19.810 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:24:19.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:19.812 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:24:19.812 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:24:19.813 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:19.813 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:19.813 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:19.813 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:24:19.813 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:19.813 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:24:19.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:19.817 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:24:19.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:24:19.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:24:19.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:24:19.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:24:19.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:24:19.818 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:24:19.818 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:24:19.818 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:19.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:19.823 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:24:20.301 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:24:20.347 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:24:20.349 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:24:20.351 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:24:20.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:24:20.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:24:20.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:24:20.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:24:20.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:24:20.355 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:24:20.355 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:24:20.355 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:24:20.355 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:24:20.773 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:24:20.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:20.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:20.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:20.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:21.244 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:24:21.718 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:24:21.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:21.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:21.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:21.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:22.190 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:24:22.662 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:24:22.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:22.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:22.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:22.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:23.133 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:24:23.607 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:24:23.824 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:23.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:23.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:23.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:24.079 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:24:24.551 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:24:24.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:24.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:24.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:24.826 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:25.022 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:24:25.495 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:24:25.968 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:24:26.440 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:24:26.911 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:24:27.384 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:24:27.856 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:24:28.328 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:24:28.799 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:24:29.272 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:24:29.744 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:24:30.217 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:24:30.690 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:24:31.162 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:24:31.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:24:31.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:24:31.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:31.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:31.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:31.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:31.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:31.403 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:31.403 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:31.403 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:24:31.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:31.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:31.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:31.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:31.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:31.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:31.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:31.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:31.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:24:36.410 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:36.410 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:36.410 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:36.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:36.410 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:36.410 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:36.418 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:36.420 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:36.420 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:36.421 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:36.421 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:24:36.426 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:24:36.426 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:24:36.427 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:36.427 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:36.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:36.427 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:24:36.428 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:36.428 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:24:36.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:36.430 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:24:36.430 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:24:36.431 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:36.431 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:36.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:36.431 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:24:36.431 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:36.431 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:24:36.431 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:36.433 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:24:36.433 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:24:36.433 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:36.433 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:36.433 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:36.433 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:24:36.434 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:36.434 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:24:36.434 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.437 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:24:36.437 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:24:36.437 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:24:36.438 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.438 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.439 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:36.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:36.439 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:36.442 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:24:36.920 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:24:36.960 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:24:36.961 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:24:36.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:24:36.962 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:24:36.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:24:36.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:24:36.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:24:36.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:24:36.964 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:24:36.964 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:24:36.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:24:36.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:24:37.392 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:24:37.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:37.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:37.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:37.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:37.863 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:24:38.337 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:24:38.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:38.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:38.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:38.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:38.809 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:24:39.281 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:24:39.442 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:39.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:39.443 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:39.443 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:39.752 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:24:40.226 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:24:40.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:40.444 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:40.444 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:40.444 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:40.698 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:24:41.170 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:24:41.445 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:41.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:41.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:41.445 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:41.641 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:24:42.114 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:24:42.586 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:24:43.058 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:24:43.529 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:24:44.003 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:24:44.475 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:24:44.947 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:24:45.418 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:24:45.889 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:24:46.362 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:24:46.834 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:24:47.307 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:24:47.777 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:24:48.251 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:24:48.723 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:24:49.195 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:24:49.666 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:24:50.137 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:24:50.611 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:24:51.083 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:24:51.555 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:24:52.016 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:24:52.016 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:24:52.021 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:52.021 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:52.021 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:52.021 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:52.022 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:52.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:52.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:52.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:52.023 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:24:52.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:52.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:57.028 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:57.028 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:57.028 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:57.028 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:57.028 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:57.028 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:57.035 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:57.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:57.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:57.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:24:57.036 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:24:57.038 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:24:57.039 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:24:57.039 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:57.039 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:57.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:57.040 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:24:57.040 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:24:57.040 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:24:57.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:57.041 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:24:57.041 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:24:57.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:57.041 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:57.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:57.041 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:24:57.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:24:57.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:24:57.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:57.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:24:57.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:24:57.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:57.043 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:24:57.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:24:57.043 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:24:57.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:24:57.043 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:24:57.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:24:57.046 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:24:57.046 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:24:57.046 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:24:57.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:24:57.051 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:24:57.530 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:24:57.567 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:24:57.568 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:24:57.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:24:57.569 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:24:57.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:24:57.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:24:57.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:24:57.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:24:57.580 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:24:57.580 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:24:57.580 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:24:57.581 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:24:57.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:24:57.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:24:57.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:24:57.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:24:57.629 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:24:57.629 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:24:57.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:24:57.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:24:57.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:24:57.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:24:57.630 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:24:57.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:24:57.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:02.637 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:25:02.637 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:25:02.637 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:02.637 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:02.637 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:02.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:02.644 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:02.645 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:25:02.645 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:02.645 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:25:02.645 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:25:02.649 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:25:02.650 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:25:02.650 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:25:02.650 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:02.651 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:02.651 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:25:02.652 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:25:02.652 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:25:02.652 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:02.654 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:25:02.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:25:02.654 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:25:02.654 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:02.654 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:02.655 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:25:02.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:25:02.655 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:25:02.655 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:02.657 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:25:02.657 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:25:02.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:25:02.657 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:02.657 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:02.657 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:25:02.657 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:25:02.657 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:25:02.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:25:02.662 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:25:02.662 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:25:02.662 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.662 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:02.663 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:02.666 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:25:03.145 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:25:03.181 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:25:03.182 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:25:03.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:03.184 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:25:03.200 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.200 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.200 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:03.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:03.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:03.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.223 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:03.223 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:03.223 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:03.223 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:03.236 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:03.236 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:03.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:03.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.347 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:03.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:03.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:03.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:03.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:03.376 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:03.376 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:03.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:03.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:03.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.617 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:25:03.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:03.625 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:03.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:03.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:03.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:03.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:03.645 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.645 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:03.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:03.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:03.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:03.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:03.660 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:03.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:03.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:03.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:03.665 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:03.666 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:04.007 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:04.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:04.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:04.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:04.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:04.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:04.028 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:04.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:04.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:04.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:04.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:04.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:04.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:04.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:04.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:04.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:04.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:04.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:04.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:04.087 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:25:04.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:04.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:04.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:04.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:04.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:04.422 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:04.422 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:04.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:04.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:04.426 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:04.427 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:25:04.427 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:25:04.427 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:25:04.427 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:04.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:04.427 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:04.428 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=381 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:04.428 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=381 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:04.428 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=381 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:04.428 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=381 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:04.428 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=381 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:04.428 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=381 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:09.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:25:09.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:25:09.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:09.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:09.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:09.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:09.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:09.437 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:25:09.437 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:09.437 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:25:09.437 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:25:09.441 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:25:09.441 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:25:09.441 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:25:09.442 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:09.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:09.442 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:25:09.443 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:25:09.443 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:25:09.443 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:09.445 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:25:09.445 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:25:09.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:25:09.445 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:09.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:09.445 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:25:09.446 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:25:09.446 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:25:09.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:09.448 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:25:09.448 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:25:09.448 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:25:09.448 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:09.448 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:09.448 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:25:09.448 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:25:09.448 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:25:09.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:09.451 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:25:09.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:25:09.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:25:09.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:25:09.451 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:25:09.452 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:25:09.452 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:25:09.452 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:09.453 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:09.457 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:25:09.935 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:25:09.979 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:25:09.980 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:25:09.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:09.981 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:25:09.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:09.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:09.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:10.023 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:10.023 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:10.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:10.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:10.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:10.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:10.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:10.032 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:10.032 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:10.073 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:10.073 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:10.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:10.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:10.407 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:25:10.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:10.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:10.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:10.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:10.878 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:25:11.349 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:25:11.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:11.457 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:11.457 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:11.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:11.822 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:25:12.295 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:25:12.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:12.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:12.458 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:12.458 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:12.768 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:25:13.241 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:25:13.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:13.460 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:13.460 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:13.460 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:13.714 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:25:14.186 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:25:14.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:14.461 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:14.461 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:14.461 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:14.657 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:25:15.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:15.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:15.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:15.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:15.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:15.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:15.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:15.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:15.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:15.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:15.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:15.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:15.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:15.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:15.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:15.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:15.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:15.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:15.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:15.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:15.130 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:25:15.602 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:25:16.075 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:25:16.548 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:25:17.020 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:25:17.493 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:25:17.966 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:25:18.439 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:25:18.911 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:25:19.384 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:25:19.857 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:25:20.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:20.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:20.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:20.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:20.155 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:20.155 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:20.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:20.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:20.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:20.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:20.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:20.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:20.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:20.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:20.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:20.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:20.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:20.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:20.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:20.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:20.329 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:25:20.800 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:25:21.273 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:25:21.746 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:25:22.218 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:25:22.691 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:25:23.164 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:25:23.636 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:25:24.107 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:25:24.577 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:25:25.048 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:25:25.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:25.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:25.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:25.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:25.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:25.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:25.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:25.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:25.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:25.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:25.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:25.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:25.218 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:25.218 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:25.218 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:25.218 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:25.228 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:25.228 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:25.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:25.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:25.519 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:25:25.992 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:25:26.465 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:25:26.936 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:25:27.408 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:25:27.881 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:25:28.353 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:25:28.825 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:25:29.296 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:25:29.770 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:25:30.232 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:30.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:30.235 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:30.235 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:30.242 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:25:30.246 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:30.247 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:30.247 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:30.247 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:30.250 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:30.251 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:30.251 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:25:30.251 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:25:30.251 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:25:30.251 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:30.252 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:35.254 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:25:35.255 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:25:35.255 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:35.255 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:35.255 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:35.255 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:35.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:35.263 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:25:35.264 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:35.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:25:35.264 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:25:35.267 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:25:35.267 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:25:35.268 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:25:35.268 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:35.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:35.268 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:25:35.269 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:25:35.269 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:25:35.269 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:35.270 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:25:35.270 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:25:35.271 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:25:35.271 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:35.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:35.271 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:25:35.271 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:25:35.271 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:25:35.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:35.273 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:25:35.273 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:25:35.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:25:35.273 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:25:35.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:35.273 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:25:35.273 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:25:35.274 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:25:35.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:25:35.276 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:25:35.277 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:25:35.277 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:25:35.277 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.278 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:25:35.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.278 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:25:35.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:25:35.281 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:25:35.760 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:25:35.803 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:25:35.805 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:25:35.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:35.807 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:25:35.832 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:35.832 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:35.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:35.847 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:35.847 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:35.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:35.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:35.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:35.852 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:35.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:35.853 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:35.853 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:35.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:35.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:35.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:35.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:36.232 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:25:36.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:36.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:36.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:36.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:36.703 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:25:37.177 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:25:37.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:37.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:37.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:37.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:37.649 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:25:38.122 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:25:38.281 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:38.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:38.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:38.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:38.595 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:25:39.068 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:25:39.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:39.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:39.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:39.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:39.540 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:25:40.013 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:25:40.283 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:40.283 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:40.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:40.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:40.486 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:25:40.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:40.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:40.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:40.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:40.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:40.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:40.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:40.930 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:40.930 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:40.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:40.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:40.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:40.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:40.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:40.932 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:40.932 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:40.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:40.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:40.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:40.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:40.958 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:25:41.429 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:25:41.900 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:25:42.371 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:25:42.844 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:25:43.317 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:25:43.789 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:25:44.262 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:25:44.735 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:25:45.207 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:25:45.678 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:25:45.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:45.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:45.966 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:45.966 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:45.984 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:45.984 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:45.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:45.989 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:45.989 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:45.989 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:45.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:45.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:45.991 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:45.991 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:45.991 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:45.991 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:46.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:46.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:46.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:46.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:46.150 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:25:46.623 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:25:47.095 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:25:47.566 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:25:48.037 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:25:48.510 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:25:48.983 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:25:49.455 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:25:49.926 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:25:50.399 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:25:50.872 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:25:51.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:51.005 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:51.009 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:51.009 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:51.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:51.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:51.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:51.032 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:51.032 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:51.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:25:51.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:51.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:51.034 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:51.034 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:51.034 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:25:51.034 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:25:51.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:25:51.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:25:51.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:51.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:51.343 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:25:51.815 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:25:52.285 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:25:52.759 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:25:53.231 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:25:53.703 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:25:54.174 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:25:54.647 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:25:55.120 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:25:55.592 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:25:56.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:25:56.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:25:56.063 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:25:56.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:25:56.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:25:56.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:25:56.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:25:56.070 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:25:56.070 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:25:56.071 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:25:56.071 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:25:56.071 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:25:56.071 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:25:56.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:25:56.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:25:56.071 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:25:56.071 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4492 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:56.071 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4492 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:56.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4492 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:56.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4492 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:56.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4492 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:25:56.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4492 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:01.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:26:01.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:26:01.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:01.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:01.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:01.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:01.090 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:01.091 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:26:01.091 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:01.091 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:26:01.091 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:26:01.093 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:26:01.093 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:26:01.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:26:01.093 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:01.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:01.093 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:26:01.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:26:01.093 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:26:01.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:01.095 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:26:01.095 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:26:01.095 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:26:01.095 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:01.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:01.095 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:26:01.095 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:26:01.095 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:26:01.095 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:01.096 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:26:01.096 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:26:01.096 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:26:01.096 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:01.096 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:01.096 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:26:01.096 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:26:01.096 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:26:01.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:26:01.098 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:26:01.099 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:26:01.099 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:26:01.099 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:01.103 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:26:01.582 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:26:01.626 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:26:01.628 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:26:01.630 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:26:01.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:01.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:01.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:01.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:01.672 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:01.672 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:01.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:01.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:01.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:01.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:01.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:01.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:01.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:01.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:01.721 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:01.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:01.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:02.054 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:26:02.101 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:02.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:02.101 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:02.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:02.526 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:26:02.999 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:26:03.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:03.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:03.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:03.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:03.472 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:26:03.944 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:26:04.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:04.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:04.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:04.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:04.418 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:26:04.890 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:26:05.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:05.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:05.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:05.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:05.362 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:26:05.834 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:26:06.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:06.106 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:06.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:06.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:06.307 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:26:06.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:06.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:06.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:06.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:06.746 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:06.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:06.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:06.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:06.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:06.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:06.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:06.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:06.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:06.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:06.753 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:06.753 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:06.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:06.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:06.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:06.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:06.779 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:26:07.251 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:26:07.722 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:26:08.193 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:26:08.667 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:26:09.139 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:26:09.611 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:26:10.082 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:26:10.555 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:26:11.028 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:26:11.501 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:26:11.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:11.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:11.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:11.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:11.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:11.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:11.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:11.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:11.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:11.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:11.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:11.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:11.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:11.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:11.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:11.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:11.825 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:11.825 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:11.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:11.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:11.971 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:26:12.442 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:26:12.913 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:26:13.384 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:26:13.857 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:26:14.330 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:26:14.802 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:26:15.273 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:26:15.746 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:26:16.219 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:26:16.691 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:26:16.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:16.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:16.833 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:16.833 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:16.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:16.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:16.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:16.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:16.856 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:16.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:16.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:16.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:16.857 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:16.857 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:16.857 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:16.857 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:16.871 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:16.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:16.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:16.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:17.161 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:26:17.633 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:26:18.106 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:26:18.578 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:26:19.050 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:26:19.521 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:26:19.994 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:26:20.467 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:26:20.939 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:26:21.410 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:26:21.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:21.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:21.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:21.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:21.881 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:26:21.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:21.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:21.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:21.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:21.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:21.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:26:21.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:26:21.895 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:26:21.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:21.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:21.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:21.895 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4493 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:21.895 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4493 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:21.895 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4493 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:21.895 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4493 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:21.895 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4493 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:21.895 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4493 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:26.900 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:26:26.900 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:26:26.900 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:26.900 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:26.900 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:26.900 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:26.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:26.916 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:26:26.916 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:26.916 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:26:26.916 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:26:26.918 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:26:26.919 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:26:26.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:26:26.919 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:26.919 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:26.919 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:26:26.919 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:26:26.919 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:26:26.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:26.921 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:26:26.921 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:26:26.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:26:26.921 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:26.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:26.921 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:26:26.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:26:26.921 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:26:26.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:26.922 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:26:26.922 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:26:26.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:26:26.922 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:26.922 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:26.922 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:26:26.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:26:26.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:26:26.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:26.924 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:26:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:26:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:26:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:26:26.924 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:26:26.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:26:26.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:26:26.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:26:26.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:26.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:26.929 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:26:27.408 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:26:27.451 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:26:27.453 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:26:27.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:27.456 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:26:27.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:27.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:27.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:27.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:27.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:27.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:27.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:27.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:27.498 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:27.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:27.498 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:27.498 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:27.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:27.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:27.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:27.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:27.880 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:26:27.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:27.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:27.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:27.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:28.351 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:26:28.824 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:26:28.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:28.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:28.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:28.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:29.297 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:26:29.770 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:26:29.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:29.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:29.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:29.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:30.243 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:26:30.716 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:26:30.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:30.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:30.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:30.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:31.188 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:26:31.659 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:26:31.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:31.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:31.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:31.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:32.130 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:26:32.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:32.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:32.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:32.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:32.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:32.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:32.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:32.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:32.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:32.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:32.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:32.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:32.582 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:32.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:32.582 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:32.582 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:32.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:32.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:32.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:32.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:32.602 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:26:33.075 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:26:33.547 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:26:34.020 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:26:34.493 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:26:34.965 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:26:35.439 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:26:35.911 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:26:36.383 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:26:36.857 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:26:37.329 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:26:37.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:37.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:37.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:37.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:37.603 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=2305 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:37.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:37.618 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:37.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:37.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:37.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:37.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:37.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:37.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:37.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:37.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:37.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:37.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:37.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:37.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:37.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:37.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:37.801 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:26:38.272 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:26:38.743 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:26:39.214 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:26:39.687 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:26:40.160 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:26:40.632 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:26:41.103 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:26:41.573 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:26:42.044 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:26:42.517 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:26:42.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:42.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:42.668 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:42.668 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:42.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:42.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:42.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:42.693 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:42.693 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:42.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:42.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:42.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:42.695 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:42.695 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:42.695 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:42.695 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:42.748 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:42.748 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:42.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:42.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:42.990 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:26:43.462 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:26:43.933 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:26:44.406 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:26:44.879 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:26:45.351 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:26:45.822 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:26:46.295 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:26:46.768 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:26:47.239 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:26:47.711 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:26:47.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:47.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:47.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:47.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:47.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:47.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:47.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:47.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:47.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:47.777 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:47.777 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:26:47.777 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:26:47.777 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:26:47.777 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4504 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:47.777 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4504 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:47.778 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4504 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:47.778 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4504 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:47.778 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4504 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:47.778 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4504 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:52.780 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:26:52.780 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:26:52.780 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:52.780 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:52.780 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:52.780 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:52.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:52.789 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:26:52.789 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:52.790 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:26:52.790 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:26:52.793 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:26:52.793 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:26:52.794 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:26:52.794 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:52.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:52.794 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:26:52.795 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:26:52.795 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:26:52.795 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:52.796 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:26:52.797 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:26:52.797 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:26:52.797 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:52.797 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:52.797 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:26:52.797 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:26:52.797 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:26:52.797 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:52.799 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:26:52.799 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:26:52.799 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:26:52.799 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:26:52.799 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:52.799 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:26:52.800 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:26:52.800 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:26:52.800 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:52.802 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:26:52.803 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:26:52.803 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:26:52.803 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:26:52.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:26:52.808 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:26:53.285 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:26:53.329 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:26:53.331 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:26:53.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:53.334 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:26:53.355 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:53.355 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:53.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:53.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:53.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:53.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:53.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:53.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:53.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:53.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:53.369 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:53.369 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:53.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:53.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:53.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:53.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:53.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:53.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:53.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:53.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:53.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:53.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:53.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:53.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:53.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:53.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:53.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:53.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:53.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:53.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:53.634 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:53.634 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:53.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:53.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:53.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:53.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:53.754 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:26:53.806 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:53.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:53.806 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:53.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:54.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:54.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:54.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:54.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:54.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:54.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:54.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:54.064 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:54.064 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:54.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:54.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:54.066 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:54.066 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:54.066 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:54.066 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:54.066 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:54.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:54.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:54.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:54.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:54.225 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:26:54.698 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:26:54.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:54.807 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:54.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:54.807 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:54.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:54.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:54.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:54.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:54.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:54.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:54.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:54.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:54.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:54.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:26:54.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:54.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:54.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:54.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:54.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:26:54.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:26:54.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:26:54.933 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:26:54.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:54.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:55.169 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:26:55.641 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:26:55.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:26:55.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:26:55.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:26:55.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:26:55.735 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:26:55.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:26:55.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:26:55.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:26:55.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:26:55.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:26:55.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:26:55.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:26:55.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:26:55.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:26:55.736 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:26:55.736 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=635 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:55.736 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=635 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:55.736 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=635 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:55.736 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=635 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:55.736 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=635 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:55.736 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=635 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:26:55.736 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=635 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:27:00.748 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:27:00.748 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:27:00.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:27:00.748 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:27:00.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:27:00.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:27:00.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:27:00.757 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:27:00.757 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:27:00.758 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:27:00.758 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:27:00.760 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:27:00.760 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:27:00.760 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:27:00.760 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:27:00.761 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:27:00.761 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:27:00.761 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:27:00.761 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:27:00.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:27:00.762 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:27:00.762 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:27:00.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:27:00.762 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:27:00.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:27:00.762 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:27:00.762 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:27:00.762 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:27:00.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:27:00.764 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:27:00.764 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:27:00.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:27:00.764 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:27:00.764 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:27:00.764 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:27:00.764 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:27:00.764 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:27:00.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:27:00.766 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:27:00.766 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:27:00.766 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:27:00.766 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:27:00.767 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:27:00.771 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:27:01.249 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:27:01.294 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:27:01.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:27:01.295 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:27:01.296 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:27:01.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:01.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:01.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:27:01.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:01.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:01.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:27:01.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:27:01.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:01.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:27:01.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:27:01.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:27:01.342 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:27:01.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:27:01.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:27:01.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:01.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:01.722 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:27:01.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:27:01.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:27:01.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:27:01.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:27:02.193 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:27:02.664 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:27:02.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:27:02.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:27:02.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:27:02.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:27:03.137 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:27:03.610 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:27:03.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:27:03.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:27:03.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:27:03.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:27:04.082 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:27:04.553 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:27:04.773 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:27:04.773 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:27:04.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:27:04.773 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:27:05.024 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:27:05.498 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:27:05.774 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:27:05.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:27:05.775 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:27:05.775 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:27:05.970 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:27:06.443 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:27:06.916 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:27:07.389 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:27:07.861 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:27:08.332 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:27:08.805 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:27:09.278 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:27:09.750 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:27:10.224 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:27:10.697 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:27:11.168 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:27:11.639 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:27:12.111 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:27:12.581 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:27:13.055 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:27:13.527 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:27:13.999 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:27:14.470 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:27:14.944 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:27:15.417 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:27:15.889 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:27:16.363 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:27:16.835 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:27:17.308 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:27:17.781 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:27:18.254 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:27:18.726 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:27:19.200 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:27:19.672 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:27:20.145 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:27:20.618 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:27:21.091 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:27:21.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:21.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:27:21.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:21.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:21.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:21.406 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:21.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:27:21.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:21.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:21.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:27:21.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:27:21.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:21.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:27:21.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:27:21.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:27:21.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:27:21.414 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:27:21.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:27:21.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:21.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:21.562 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:27:22.034 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:27:22.507 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:27:22.980 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:27:23.452 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:27:23.925 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:27:24.398 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:27:24.870 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:27:25.341 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:27:25.812 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:27:26.283 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:27:26.756 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:27:27.228 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:27:27.701 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:27:28.174 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:27:28.647 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:27:29.119 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:27:29.590 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:27:30.061 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:27:30.531 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:27:31.004 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:27:31.477 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:27:31.949 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:27:32.420 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:27:32.893 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:27:33.366 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:27:33.839 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:27:34.312 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:27:34.785 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:27:35.257 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:27:35.728 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:27:36.201 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:27:36.674 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:27:37.146 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:27:37.617 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:27:38.088 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:27:38.561 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:27:39.034 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:27:39.506 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:27:39.979 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:27:40.452 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:27:40.924 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:27:41.391 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:27:41.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:41.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:27:41.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:41.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:41.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:41.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:41.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:27:41.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:27:41.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:27:41.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:27:41.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:27:41.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:41.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:27:41.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:27:41.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:27:41.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:27:41.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:27:41.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:27:41.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:41.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:27:41.853 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:27:42.317 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:27:42.782 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:27:43.254 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:27:43.726 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:27:44.197 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:27:44.668 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:27:45.142 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:27:45.614 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:27:46.086 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:27:46.557 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:27:47.030 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:27:47.503 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:27:47.975 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:27:48.446 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 02:27:48.919 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 02:27:49.392 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 02:27:49.863 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 02:27:50.335 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 02:27:50.805 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 02:27:51.279 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 02:27:51.751 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 02:27:52.223 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 02:27:52.697 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 02:27:53.169 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 02:27:53.641 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 02:27:54.112 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 02:27:54.586 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 02:27:55.058 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 02:27:55.530 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 02:27:56.001 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 02:27:56.475 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 02:27:56.947 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 02:27:57.419 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 02:27:57.890 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 02:27:58.363 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 02:27:58.836 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 02:27:59.308 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 02:27:59.779 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 02:28:00.250 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 02:28:00.723 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 02:28:01.196 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 02:28:01.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:01.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:01.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:01.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:01.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:01.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:01.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:01.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:01.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:01.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:01.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:01.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:01.459 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:01.459 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:01.459 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:01.459 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:01.475 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:01.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:01.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:01.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:01.667 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 02:28:02.139 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 02:28:02.608 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 02:28:03.079 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 02:28:03.543 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 02:28:04.006 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 02:28:04.470 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 02:28:04.934 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 02:28:05.397 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 02:28:05.861 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 02:28:06.323 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 02:28:06.786 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 02:28:07.257 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 02:28:07.729 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 02:28:08.194 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 02:28:08.667 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 02:28:09.136 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 02:28:09.606 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 02:28:10.077 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 02:28:10.551 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 02:28:11.023 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 02:28:11.495 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 02:28:11.966 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 02:28:12.439 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 02:28:12.912 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 02:28:13.384 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 02:28:13.857 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 02:28:14.330 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 02:28:14.802 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 02:28:15.273 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 02:28:15.746 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 02:28:16.219 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 02:28:16.691 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 02:28:17.162 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 02:28:17.635 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 02:28:18.107 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 02:28:18.580 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 02:28:19.051 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 02:28:19.521 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 02:28:19.995 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 02:28:20.467 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 02:28:20.939 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 02:28:21.410 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 02:28:21.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:21.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:21.484 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:21.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:21.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:21.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:21.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:21.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:21.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:21.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:21.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:21.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:21.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:28:21.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:28:21.495 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:28:26.501 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:28:26.501 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:28:26.501 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:26.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:26.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:26.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:26.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:26.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:28:26.510 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:26.511 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:28:26.511 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:28:26.515 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:28:26.515 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:28:26.516 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:28:26.516 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:26.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:26.517 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:28:26.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:28:26.517 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:28:26.518 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:26.519 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:28:26.519 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:28:26.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:28:26.520 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:26.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:26.520 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:28:26.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:28:26.520 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:28:26.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:26.523 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:28:26.524 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:28:26.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:28:26.524 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:26.524 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:26.524 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:28:26.524 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:28:26.524 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:28:26.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.529 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:28:26.530 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:28:26.530 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:28:26.530 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.530 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:28:26.531 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.531 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.531 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:26.533 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:28:26.533 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:28:26.533 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:28:31.542 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:28:31.542 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:28:31.542 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:31.542 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:31.543 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:31.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:31.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:31.550 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:28:31.550 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:31.550 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:28:31.550 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:28:31.552 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:28:31.552 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:28:31.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:28:31.553 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:31.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:31.553 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:28:31.553 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:28:31.553 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:28:31.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:31.555 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:28:31.555 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:28:31.555 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:28:31.555 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:31.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:31.555 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:28:31.555 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:28:31.555 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:28:31.555 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:31.557 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:28:31.557 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:28:31.557 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:28:31.558 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:31.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:31.558 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:28:31.558 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:28:31.558 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:28:31.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.561 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:28:31.561 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:28:31.561 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:28:31.562 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:31.566 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:28:32.043 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:28:32.077 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:28:32.077 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:28:32.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.078 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:28:32.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:32.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:32.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.106 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.106 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.106 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:32.106 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:32.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.135 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:32.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:32.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:32.369 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.369 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.513 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:28:32.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:32.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:32.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:32.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:32.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.574 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.577 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.577 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:32.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:32.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:32.598 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.598 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.799 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.799 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:32.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:32.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:32.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:32.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:32.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.820 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:32.820 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:32.836 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:32.836 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:32.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:32.984 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:28:33.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:33.118 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:33.118 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:33.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:33.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:33.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:33.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:33.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:33.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:33.135 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:33.135 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:33.164 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:33.165 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:33.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:33.441 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:33.441 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:33.452 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:28:33.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:33.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:33.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:33.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:33.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:33.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:33.461 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:33.461 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:33.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:33.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:33.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.566 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:33.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:33.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:33.567 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:33.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:33.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:33.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:33.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:33.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:33.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:33.825 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:33.825 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:33.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:33.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:33.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.826 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:33.826 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:33.826 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:33.826 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:33.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:33.871 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:33.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:33.923 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:28:34.394 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:28:34.567 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:34.568 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:34.568 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:34.568 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:34.865 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:28:35.339 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:28:35.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:35.569 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:35.569 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:35.569 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:35.811 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:28:36.283 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:28:36.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:36.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:36.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:36.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:36.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:36.457 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:36.457 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:36.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:36.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:36.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:36.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:36.460 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:36.460 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:36.462 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:36.462 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:36.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:36.462 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:36.571 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:36.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:36.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:36.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:36.753 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:28:37.224 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:28:37.698 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:28:38.170 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:28:38.642 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:28:39.032 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:39.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:39.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:39.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:39.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:39.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:39.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:39.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:39.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:39.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:39.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:39.051 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:39.051 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:39.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:39.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:39.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:39.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:39.113 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:28:39.584 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:28:40.057 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:28:40.530 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:28:41.002 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:28:41.473 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:28:41.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:41.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:41.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:41.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:41.640 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:41.640 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:41.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:41.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:41.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:41.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:41.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:41.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:41.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:41.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:41.650 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:41.650 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:41.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:41.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:41.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:41.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:41.944 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:28:42.415 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:28:42.888 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:28:43.361 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:28:43.833 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:28:44.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:44.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:44.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:44.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:44.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:44.171 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:44.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:44.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:44.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:44.173 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:44.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:44.174 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:44.174 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:44.204 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:44.204 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:44.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:44.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:44.303 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:28:44.774 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:28:45.248 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:28:45.720 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:28:46.192 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:28:46.663 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:28:46.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:46.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:46.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:46.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:46.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:46.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:46.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:46.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:46.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:46.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:46.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:46.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:46.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:46.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:46.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:46.800 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:46.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:47.136 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:28:47.609 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:28:48.081 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:28:48.552 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:28:49.025 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:28:49.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:49.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:49.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:49.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:49.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:49.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:49.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:49.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:49.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:49.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:49.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:49.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:49.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:28:49.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:28:49.355 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:28:54.362 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:28:54.362 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:28:54.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:54.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:54.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:54.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:54.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:28:54.373 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:28:54.373 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:54.374 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:28:54.374 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:28:54.375 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:28:54.376 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:28:54.376 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:28:54.376 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:54.376 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:28:54.376 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:28:54.376 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:28:54.376 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:28:54.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:54.378 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:28:54.378 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:28:54.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:28:54.378 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:54.378 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:28:54.378 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:28:54.378 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:28:54.378 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:28:54.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:54.379 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:28:54.379 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:28:54.379 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:28:54.379 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:28:54.379 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:28:54.379 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:28:54.379 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:28:54.379 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:28:54.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:28:54.381 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:28:54.382 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:28:54.382 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:28:54.382 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:28:54.386 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:28:54.865 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:28:54.904 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:28:54.905 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:28:54.906 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:28:54.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:54.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:54.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:54.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:54.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:54.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:54.946 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:54.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:54.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:54.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:54.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:54.950 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:54.950 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:54.956 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:54.956 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:54.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:54.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:55.333 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:28:55.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:55.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:55.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:55.385 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:55.804 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:28:56.277 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:28:56.385 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:56.385 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:56.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:56.386 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:56.750 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:28:57.222 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:28:57.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:57.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:57.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:57.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:57.693 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:28:58.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:58.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:58.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:58.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:58.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:58.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:58.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:58.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:28:58.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:28:58.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:28:58.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:28:58.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:58.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:58.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:58.102 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:28:58.102 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:28:58.108 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:28:58.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:28:58.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:58.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:28:58.165 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:28:58.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:58.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:58.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:58.389 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:58.639 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:28:59.111 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:28:59.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:28:59.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:28:59.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:28:59.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:28:59.585 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:29:00.057 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:29:00.529 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:29:01.000 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:29:01.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:01.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:01.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:01.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:01.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:01.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:01.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:01.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:01.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:01.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:01.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:01.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:01.312 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:01.312 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:01.312 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:01.312 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:01.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:01.324 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:01.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:01.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:01.472 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:29:01.945 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:29:02.418 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:29:02.891 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:29:03.363 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:29:03.836 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:29:04.306 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:29:04.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:04.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:04.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:04.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:04.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:04.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:04.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:04.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:04.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:04.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:04.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:04.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:04.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:04.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:04.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:04.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:04.539 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:04.539 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:04.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:04.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:04.777 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:29:05.251 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:29:05.723 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:29:06.195 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:29:06.666 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:29:07.139 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:29:07.612 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:29:07.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:07.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:07.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:07.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:07.710 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:07.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:07.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:07.711 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:07.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:07.713 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:07.713 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:07.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:07.713 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:07.713 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:07.713 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:29:12.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:12.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:12.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:12.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:12.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:12.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:12.722 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:12.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:12.722 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:12.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:12.722 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:29:12.725 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:29:12.725 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:29:12.725 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:12.725 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:12.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:12.726 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:29:12.726 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:12.726 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:29:12.726 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:12.729 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:29:12.729 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:29:12.729 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:12.729 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:12.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:12.729 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:29:12.729 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:12.729 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:29:12.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:12.733 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:29:12.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:29:12.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:12.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:12.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:12.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:29:12.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:12.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:29:12.733 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:12.738 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:29:12.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.739 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:29:12.739 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:29:12.740 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:29:12.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:12.744 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:29:13.223 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:29:13.272 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:29:13.274 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:29:13.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:13.276 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:29:13.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:13.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:13.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:13.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:13.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:13.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:13.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:13.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:13.313 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:13.313 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:13.313 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:13.313 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:13.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:13.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:13.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:13.361 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:13.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:13.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:13.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:13.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:13.694 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:29:13.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:13.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:13.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:13.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:13.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:13.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:13.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:13.706 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:13.706 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:13.706 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:13.706 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:13.706 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:13.734 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:13.734 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:13.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:13.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:13.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:13.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:13.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:13.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:14.165 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:29:14.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:14.221 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:14.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:14.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:14.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:14.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:14.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:14.248 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:14.248 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:14.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:14.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:14.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:14.250 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:14.250 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:14.250 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:14.250 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:14.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:14.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:14.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:14.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:14.637 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:29:14.745 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:14.745 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:14.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:14.745 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:15.108 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:29:15.581 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:29:15.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:15.747 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:15.747 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:15.747 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:16.054 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:29:16.526 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:29:16.747 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:16.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:16.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:16.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:16.997 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:29:17.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:17.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:17.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:17.157 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:17.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:17.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:17.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:17.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:17.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:17.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:17.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:17.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:17.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:17.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:17.185 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:17.185 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:17.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:17.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:17.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:17.231 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:17.470 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:29:17.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:17.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:17.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:17.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:17.943 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:29:18.415 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:29:18.886 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:29:19.359 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:29:19.832 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:29:20.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:20.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:20.154 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:20.154 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:20.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:20.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:20.165 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:20.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:20.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:20.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:20.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:20.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:20.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:20.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:29:20.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:25.171 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:25.171 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:25.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:25.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:25.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:25.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:25.176 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:25.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:25.178 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:25.178 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:25.178 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:29:25.180 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:29:25.181 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:29:25.181 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:25.181 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:25.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:25.182 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:29:25.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:25.182 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:29:25.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:25.183 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:29:25.183 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:29:25.184 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:25.184 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:25.184 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:25.184 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:29:25.184 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:25.184 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:29:25.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:25.186 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:29:25.186 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:29:25.186 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:25.186 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:25.186 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:25.186 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:29:25.186 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:25.186 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:29:25.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.189 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:29:25.189 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:29:25.189 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:29:25.190 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:25.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:25.194 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:29:25.671 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:29:25.712 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:29:25.713 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:29:25.715 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:29:25.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:25.735 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:25.735 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:25.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:25.754 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:25.754 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:25.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:25.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:25.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:25.761 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:25.761 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:25.762 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:25.762 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:25.809 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:25.809 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:25.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:25.810 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:26.142 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:29:26.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:26.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:26.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:26.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:26.614 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:29:27.087 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:29:27.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:27.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:27.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:27.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:27.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:27.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:27.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:27.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:27.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:27.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:27.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:27.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:27.136 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:27.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:27.136 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:27.136 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:27.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:27.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:27.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:27.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:27.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:27.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:27.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:27.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:27.558 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:29:28.031 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:29:28.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:28.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:28.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:28.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:28.504 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:29:28.976 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:29:29.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:29.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:29.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:29.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:29.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:29.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:29.303 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:29.303 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:29.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:29.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:29.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:29.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:29.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:29.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:29.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:29.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:29.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:29.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:29.328 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:29.328 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:29.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:29.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:29.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:29.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:29.447 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:29:29.918 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:29:30.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:30.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:30.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:30.197 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:30.391 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:29:30.863 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:29:31.336 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:29:31.809 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:29:32.282 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:29:32.754 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:29:33.225 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:29:33.698 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:29:34.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:34.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:34.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:34.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:34.170 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:29:34.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:34.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:34.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:34.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:34.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:34.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:34.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:34.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:34.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:34.179 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:34.179 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:34.179 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:34.216 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:34.216 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:34.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:34.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:34.643 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:29:35.114 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:29:35.587 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:29:36.059 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:29:36.532 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:29:37.005 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:29:37.478 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:29:37.950 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:29:38.421 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:29:38.894 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:29:39.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:39.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:39.047 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:39.047 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:39.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:39.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:39.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:39.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:39.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:39.064 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:39.064 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:39.064 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:29:39.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:39.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:39.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:39.065 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2997 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:29:39.065 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2997 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:29:39.065 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2997 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:29:39.065 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2997 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:29:39.065 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2997 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:29:39.065 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2997 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:29:44.064 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:44.064 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:44.064 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:44.064 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:44.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:44.065 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:44.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:44.073 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:44.073 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:44.074 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:44.074 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:29:44.078 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:29:44.078 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:29:44.079 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:44.079 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:44.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:44.079 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:29:44.080 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:44.080 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:29:44.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:44.081 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:29:44.081 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:29:44.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:44.082 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:44.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:44.082 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:29:44.082 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:44.082 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:29:44.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:44.084 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:29:44.084 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:29:44.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:44.084 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:44.084 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:44.084 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:29:44.084 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:44.084 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:29:44.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:29:44.087 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:29:44.087 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:29:44.087 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:29:44.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:44.088 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:44.092 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:29:44.570 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:29:44.608 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:29:44.608 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:29:44.610 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:29:44.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:44.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:44.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:44.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:44.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:44.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:44.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:44.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:44.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:44.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:44.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:44.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:44.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:44.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:44.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:44.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:44.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:45.043 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:29:45.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:45.091 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:45.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:45.091 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:45.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:45.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:45.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:45.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:45.288 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:45.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:45.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:45.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:45.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:45.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:45.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:45.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:45.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:45.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:45.296 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:45.296 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:45.322 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:45.322 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:45.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:45.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:45.513 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:29:45.984 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:29:46.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:46.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:46.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:46.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:46.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:46.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:46.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:46.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:46.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:46.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:46.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:46.270 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:46.270 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:46.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:46.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:46.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:46.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:46.271 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:46.271 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:46.271 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:46.310 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:46.310 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:46.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:46.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:46.457 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:29:46.930 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:29:47.093 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:47.093 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:47.093 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:47.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:47.402 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:29:47.873 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:29:48.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:48.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:48.094 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:48.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:48.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:48.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:48.267 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:48.267 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:48.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:48.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:48.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:48.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:48.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:48.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:48.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:48.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:48.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:48.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:48.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:48.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:48.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:48.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:48.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:48.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:48.345 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:29:48.818 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:29:49.094 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:49.096 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:49.096 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:49.096 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:49.290 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:29:49.761 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:29:50.235 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:29:50.313 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:50.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:50.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:50.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:50.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:50.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:50.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:50.329 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:50.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:50.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:50.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:50.331 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:50.331 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:50.331 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:29:50.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:55.336 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:29:55.336 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:29:55.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:55.336 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:55.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:55.336 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:55.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:29:55.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:55.352 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:55.352 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:29:55.352 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:29:55.354 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:29:55.354 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:29:55.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:55.354 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:55.354 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:29:55.354 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:29:55.354 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:29:55.354 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:29:55.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:55.355 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:29:55.355 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:29:55.355 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:55.356 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:55.356 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:29:55.356 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:29:55.356 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:29:55.356 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:29:55.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:55.356 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:29:55.356 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:29:55.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:55.357 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:29:55.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:29:55.357 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:29:55.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:29:55.357 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:29:55.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:29:55.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:29:55.359 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:29:55.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:29:55.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:29:55.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:29:55.842 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:29:55.883 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:29:55.885 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:29:55.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:55.888 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:29:55.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:55.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:55.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:55.933 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:55.933 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:55.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:55.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:55.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:55.939 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:55.939 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:55.939 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:55.939 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:55.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:55.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:55.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:55.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:56.314 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:29:56.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:56.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:56.363 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:56.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:56.785 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:29:57.256 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:29:57.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:57.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:57.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:57.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:57.727 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:29:58.200 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:29:58.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:58.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:58.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:58.366 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:58.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:58.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:58.421 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:58.421 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:58.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:58.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:58.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:58.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:29:58.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:29:58.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:29:58.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:29:58.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:58.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:58.442 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:58.442 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:29:58.442 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:29:58.477 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:29:58.477 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:29:58.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:58.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:29:58.672 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:29:59.141 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:29:59.366 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:29:59.366 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:29:59.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:29:59.366 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:29:59.604 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:30:00.072 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:30:00.367 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:00.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:00.367 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:00.367 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:00.536 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:30:01.001 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:30:01.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:01.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:01.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:01.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:01.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:01.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:01.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:01.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:01.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:01.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:01.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:01.199 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:01.199 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:01.199 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:01.199 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:01.199 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:01.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:01.230 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:01.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:01.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:01.463 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:30:01.926 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:30:02.389 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:30:02.853 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:30:03.316 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:30:03.779 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:30:04.243 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:30:04.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:04.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:04.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:04.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:04.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:04.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:04.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:04.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:04.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:04.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:04.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:04.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:04.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:04.646 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:04.646 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:04.646 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:04.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:04.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:04.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:04.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:04.706 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:30:05.169 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:30:05.632 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:30:06.094 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:30:06.557 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:30:07.020 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:30:07.483 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:30:07.946 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:30:08.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:08.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:08.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:08.025 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:08.028 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:08.028 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:08.028 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:08.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:08.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:30:08.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:30:08.029 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:30:08.029 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:30:08.029 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:30:08.029 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:30:08.029 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:30:13.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:30:13.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:30:13.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:30:13.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:30:13.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:30:13.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:30:13.036 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:30:13.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:30:13.036 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:13.036 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:30:13.036 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:30:13.038 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:30:13.038 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:30:13.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:30:13.038 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:13.038 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:30:13.038 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:30:13.038 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:30:13.038 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:30:13.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:13.040 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:30:13.040 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:30:13.040 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:30:13.040 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:13.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:30:13.041 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:30:13.041 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:30:13.041 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:30:13.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:13.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:30:13.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:30:13.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:30:13.043 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:13.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:30:13.043 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:30:13.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:30:13.043 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:30:13.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.046 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:30:13.047 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:30:13.047 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:30:13.047 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:13.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:13.051 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:30:13.515 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:30:13.568 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:30:13.569 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:30:13.569 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:30:13.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:13.579 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:13.579 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:13.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:13.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:13.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:13.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:13.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:13.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:13.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:13.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:13.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:13.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:13.605 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:13.605 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:13.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:13.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:13.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:13.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:13.810 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:13.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:13.821 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:13.821 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:13.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:13.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:13.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:13.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:13.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:13.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:13.834 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:13.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:13.834 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:13.834 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:13.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:13.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:13.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:13.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:13.980 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:30:14.050 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:14.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:14.051 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:14.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:14.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:14.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:14.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:14.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:14.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:14.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:14.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:14.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:14.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:14.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:14.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:14.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:14.197 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:14.197 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:14.211 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:14.211 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:14.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.211 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.444 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:30:14.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:14.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:14.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:14.843 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:14.843 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:14.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:14.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:14.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:14.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:14.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:14.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.854 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:14.854 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:14.854 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:14.854 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:14.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:14.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:14.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:14.908 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:30:15.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:15.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:15.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:15.056 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:15.373 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:30:15.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:15.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:15.453 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:15.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:15.456 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:15.456 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:15.456 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:15.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:15.457 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:30:15.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:30:15.458 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:30:15.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:30:15.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:30:15.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:30:15.458 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:30:20.458 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:30:20.458 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:30:20.458 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:30:20.459 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:30:20.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:30:20.459 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:30:20.464 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:30:20.464 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:30:20.464 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:20.464 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:30:20.464 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:30:20.465 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:30:20.465 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:30:20.465 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:30:20.465 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:20.465 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:30:20.466 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:30:20.466 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:30:20.466 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:30:20.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:20.467 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:30:20.467 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:30:20.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:30:20.467 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:20.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:30:20.467 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:30:20.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:30:20.467 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:30:20.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:20.468 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:30:20.468 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:30:20.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:30:20.468 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:30:20.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:30:20.468 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:30:20.468 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:30:20.468 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:30:20.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:30:20.470 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:30:20.470 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:30:20.470 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.470 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:30:20.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:30:20.475 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:30:20.939 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:30:20.983 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:30:20.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:20.984 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:30:20.984 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:30:20.991 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:20.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:20.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:20.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:20.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:20.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:20.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:20.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:21.000 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:21.000 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:21.000 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:21.000 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:21.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:21.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:21.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:21.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:21.403 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:30:21.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:21.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:21.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:21.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:21.866 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:30:22.329 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:30:22.473 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:22.473 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:22.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:22.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:22.792 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:30:23.256 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:30:23.474 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:23.474 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:23.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:23.474 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:23.721 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:30:24.186 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:30:24.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:24.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:24.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:24.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:24.651 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:30:25.118 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:30:25.475 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:30:25.475 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:30:25.475 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:30:25.475 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:30:25.587 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:30:26.052 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:30:26.516 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:30:26.979 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:30:27.443 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:30:27.907 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:30:28.370 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:30:28.834 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:30:29.297 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:30:29.761 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:30:30.225 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:30:30.689 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:30:31.154 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:30:31.618 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:30:32.082 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:30:32.547 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:30:33.011 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:30:33.475 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:30:33.941 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:30:34.406 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:30:34.871 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:30:35.336 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:30:35.800 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:30:36.265 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:30:36.797 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:30:37.261 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:30:37.726 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:30:38.190 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:30:38.654 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:30:39.119 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:30:39.584 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:30:40.048 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:30:40.512 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:30:40.977 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:30:41.441 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:30:41.906 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:30:42.370 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:30:42.834 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:30:43.299 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:30:43.762 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:30:44.227 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:30:44.690 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:30:45.154 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:30:45.618 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:30:46.082 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:30:46.547 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:30:47.011 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:30:47.476 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:30:47.941 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:30:48.405 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:30:48.871 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:30:49.335 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:30:49.799 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:30:50.263 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:30:50.727 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:30:51.191 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:30:51.655 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:30:52.119 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:30:52.583 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:30:53.046 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:30:53.510 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:30:53.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:53.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:53.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:53.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:53.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:53.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:53.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:53.974 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:30:53.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:30:53.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:30:53.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:30:53.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:30:53.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:53.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:53.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:53.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:30:53.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:30:54.015 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:30:54.015 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:30:54.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:54.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:30:54.438 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:30:54.902 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:30:55.367 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:30:55.832 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:30:56.297 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:30:56.760 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:30:57.224 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:30:57.688 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:30:58.154 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:30:58.621 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:30:59.088 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:30:59.554 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:31:00.021 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:31:00.487 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:31:00.951 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:31:01.415 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:31:01.881 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:31:02.348 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:31:02.813 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:31:03.278 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:31:03.742 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:31:04.206 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:31:04.670 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:31:05.134 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:31:05.598 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:31:06.062 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:31:06.527 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:31:06.991 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:31:07.454 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 02:31:07.918 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 02:31:08.382 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 02:31:08.845 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 02:31:09.309 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 02:31:09.772 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 02:31:10.235 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 02:31:10.699 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 02:31:11.163 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 02:31:11.628 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 02:31:12.092 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 02:31:12.556 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 02:31:13.020 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 02:31:13.484 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 02:31:13.948 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 02:31:14.412 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 02:31:14.876 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 02:31:15.339 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 02:31:15.803 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 02:31:16.266 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 02:31:16.730 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 02:31:17.194 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 02:31:17.657 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 02:31:18.121 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 02:31:18.585 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 02:31:19.048 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 02:31:19.511 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 02:31:19.975 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 02:31:20.439 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 02:31:20.902 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 02:31:21.365 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 02:31:21.829 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 02:31:22.293 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 02:31:22.757 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 02:31:23.219 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 02:31:23.682 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 02:31:24.145 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 02:31:24.608 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 02:31:25.072 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 02:31:25.536 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 02:31:25.999 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 02:31:26.463 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 02:31:26.927 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 02:31:27.392 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 02:31:27.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:31:27.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:31:27.562 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:31:27.562 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:31:27.576 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:31:27.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:31:27.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:31:27.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:31:27.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:31:27.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:31:27.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:31:27.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:31:27.593 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:31:27.593 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:31:27.593 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:31:27.593 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:31:27.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:31:27.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:31:27.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:31:27.624 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:31:27.857 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 02:31:28.321 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 02:31:28.785 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 02:31:29.250 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 02:31:29.714 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 02:31:30.178 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 02:31:30.642 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 02:31:31.106 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 02:31:31.570 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 02:31:32.032 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 02:31:32.498 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 02:31:32.961 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 02:31:33.424 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 02:31:33.888 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 02:31:34.351 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 02:31:34.815 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 02:31:35.278 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 02:31:35.741 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 02:31:36.205 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 02:31:36.668 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 02:31:37.132 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 02:31:37.595 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 02:31:38.060 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 02:31:38.524 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 02:31:38.989 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 02:31:39.453 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 02:31:39.918 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 02:31:40.382 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 02:31:40.845 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 02:31:41.308 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 02:31:41.772 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 02:31:42.235 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 02:31:42.699 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 02:31:43.163 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 02:31:43.626 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 02:31:44.090 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 02:31:44.553 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 02:31:45.017 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-01 02:31:45.480 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-01 02:31:45.944 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-01 02:31:46.408 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-01 02:31:46.872 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-01 02:31:47.337 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-01 02:31:47.801 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-01 02:31:48.264 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-01 02:31:48.727 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-01 02:31:49.191 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-01 02:31:49.654 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-01 02:31:50.118 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-01 02:31:50.581 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-01 02:31:51.044 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-01 02:31:51.508 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-01 02:31:51.971 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-01 02:31:52.435 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-01 02:31:52.899 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-01 02:31:53.362 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-01 02:31:53.826 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-01 02:31:54.290 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-01 02:31:54.755 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-01 02:31:55.219 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-01 02:31:55.683 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-01 02:31:56.146 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-01 02:31:56.610 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-01 02:31:57.074 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-01 02:31:57.538 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-01 02:31:58.001 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-01 02:31:58.465 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-01 02:31:58.929 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-01 02:31:59.392 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-01 02:31:59.856 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-01 02:32:00.320 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-01 02:32:00.784 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-01 02:32:01.247 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-01 02:32:01.711 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-01 02:32:02.177 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-01 02:32:02.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:02.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:02.573 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:02.573 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:02.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:02.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:02.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:02.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:02.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:02.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:02.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:02.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:02.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:02.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:02.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:32:02.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:32:02.641 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:02.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:02.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:02.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:02.642 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-01 02:32:03.106 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-01 02:32:03.571 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-01 02:32:04.034 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-01 02:32:04.499 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-01 02:32:04.965 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-01 02:32:05.430 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-01 02:32:05.895 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-01 02:32:06.359 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-01 02:32:06.824 [DEBUG] clck_gen.py:113 IND CLOCK 23358
2026-03-01 02:32:07.401 [DEBUG] clck_gen.py:113 IND CLOCK 23460
2026-03-01 02:32:07.866 [DEBUG] clck_gen.py:113 IND CLOCK 23562
2026-03-01 02:32:08.330 [DEBUG] clck_gen.py:113 IND CLOCK 23664
2026-03-01 02:32:08.793 [DEBUG] clck_gen.py:113 IND CLOCK 23766
2026-03-01 02:32:09.256 [DEBUG] clck_gen.py:113 IND CLOCK 23868
2026-03-01 02:32:09.720 [DEBUG] clck_gen.py:113 IND CLOCK 23970
2026-03-01 02:32:10.183 [DEBUG] clck_gen.py:113 IND CLOCK 24072
2026-03-01 02:32:10.645 [DEBUG] clck_gen.py:113 IND CLOCK 24174
2026-03-01 02:32:11.110 [DEBUG] clck_gen.py:113 IND CLOCK 24276
2026-03-01 02:32:11.573 [DEBUG] clck_gen.py:113 IND CLOCK 24378
2026-03-01 02:32:12.036 [DEBUG] clck_gen.py:113 IND CLOCK 24480
2026-03-01 02:32:12.500 [DEBUG] clck_gen.py:113 IND CLOCK 24582
2026-03-01 02:32:12.963 [DEBUG] clck_gen.py:113 IND CLOCK 24684
2026-03-01 02:32:13.427 [DEBUG] clck_gen.py:113 IND CLOCK 24786
2026-03-01 02:32:13.891 [DEBUG] clck_gen.py:113 IND CLOCK 24888
2026-03-01 02:32:14.354 [DEBUG] clck_gen.py:113 IND CLOCK 24990
2026-03-01 02:32:14.819 [DEBUG] clck_gen.py:113 IND CLOCK 25092
2026-03-01 02:32:15.283 [DEBUG] clck_gen.py:113 IND CLOCK 25194
2026-03-01 02:32:15.747 [DEBUG] clck_gen.py:113 IND CLOCK 25296
2026-03-01 02:32:16.218 [DEBUG] clck_gen.py:113 IND CLOCK 25398
2026-03-01 02:32:16.681 [DEBUG] clck_gen.py:113 IND CLOCK 25500
2026-03-01 02:32:17.146 [DEBUG] clck_gen.py:113 IND CLOCK 25602
2026-03-01 02:32:17.612 [DEBUG] clck_gen.py:113 IND CLOCK 25704
2026-03-01 02:32:18.082 [DEBUG] clck_gen.py:113 IND CLOCK 25806
2026-03-01 02:32:18.550 [DEBUG] clck_gen.py:113 IND CLOCK 25908
2026-03-01 02:32:19.014 [DEBUG] clck_gen.py:113 IND CLOCK 26010
2026-03-01 02:32:19.477 [DEBUG] clck_gen.py:113 IND CLOCK 26112
2026-03-01 02:32:19.940 [DEBUG] clck_gen.py:113 IND CLOCK 26214
2026-03-01 02:32:20.403 [DEBUG] clck_gen.py:113 IND CLOCK 26316
2026-03-01 02:32:20.867 [DEBUG] clck_gen.py:113 IND CLOCK 26418
2026-03-01 02:32:21.330 [DEBUG] clck_gen.py:113 IND CLOCK 26520
2026-03-01 02:32:21.796 [DEBUG] clck_gen.py:113 IND CLOCK 26622
2026-03-01 02:32:22.261 [DEBUG] clck_gen.py:113 IND CLOCK 26724
2026-03-01 02:32:22.724 [DEBUG] clck_gen.py:113 IND CLOCK 26826
2026-03-01 02:32:23.192 [DEBUG] clck_gen.py:113 IND CLOCK 26928
2026-03-01 02:32:23.663 [DEBUG] clck_gen.py:113 IND CLOCK 27030
2026-03-01 02:32:24.134 [DEBUG] clck_gen.py:113 IND CLOCK 27132
2026-03-01 02:32:24.598 [DEBUG] clck_gen.py:113 IND CLOCK 27234
2026-03-01 02:32:25.065 [DEBUG] clck_gen.py:113 IND CLOCK 27336
2026-03-01 02:32:25.532 [DEBUG] clck_gen.py:113 IND CLOCK 27438
2026-03-01 02:32:25.999 [DEBUG] clck_gen.py:113 IND CLOCK 27540
2026-03-01 02:32:26.470 [DEBUG] clck_gen.py:113 IND CLOCK 27642
2026-03-01 02:32:26.939 [DEBUG] clck_gen.py:113 IND CLOCK 27744
2026-03-01 02:32:27.410 [DEBUG] clck_gen.py:113 IND CLOCK 27846
2026-03-01 02:32:27.881 [DEBUG] clck_gen.py:113 IND CLOCK 27948
2026-03-01 02:32:28.350 [DEBUG] clck_gen.py:113 IND CLOCK 28050
2026-03-01 02:32:28.815 [DEBUG] clck_gen.py:113 IND CLOCK 28152
2026-03-01 02:32:29.281 [DEBUG] clck_gen.py:113 IND CLOCK 28254
2026-03-01 02:32:29.747 [DEBUG] clck_gen.py:113 IND CLOCK 28356
2026-03-01 02:32:30.213 [DEBUG] clck_gen.py:113 IND CLOCK 28458
2026-03-01 02:32:30.679 [DEBUG] clck_gen.py:113 IND CLOCK 28560
2026-03-01 02:32:31.144 [DEBUG] clck_gen.py:113 IND CLOCK 28662
2026-03-01 02:32:31.614 [DEBUG] clck_gen.py:113 IND CLOCK 28764
2026-03-01 02:32:32.084 [DEBUG] clck_gen.py:113 IND CLOCK 28866
2026-03-01 02:32:32.557 [DEBUG] clck_gen.py:113 IND CLOCK 28968
2026-03-01 02:32:33.029 [DEBUG] clck_gen.py:113 IND CLOCK 29070
2026-03-01 02:32:33.502 [DEBUG] clck_gen.py:113 IND CLOCK 29172
2026-03-01 02:32:33.975 [DEBUG] clck_gen.py:113 IND CLOCK 29274
2026-03-01 02:32:34.447 [DEBUG] clck_gen.py:113 IND CLOCK 29376
2026-03-01 02:32:34.920 [DEBUG] clck_gen.py:113 IND CLOCK 29478
2026-03-01 02:32:35.393 [DEBUG] clck_gen.py:113 IND CLOCK 29580
2026-03-01 02:32:35.865 [DEBUG] clck_gen.py:113 IND CLOCK 29682
2026-03-01 02:32:36.336 [DEBUG] clck_gen.py:113 IND CLOCK 29784
2026-03-01 02:32:36.809 [DEBUG] clck_gen.py:113 IND CLOCK 29886
2026-03-01 02:32:37.282 [DEBUG] clck_gen.py:113 IND CLOCK 29988
2026-03-01 02:32:37.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:37.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:37.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:37.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:37.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:37.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:37.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:37.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:37.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:32:37.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:32:37.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:32:37.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:32:37.676 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:32:37.676 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:32:37.676 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:32:37.676 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=30075 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:32:37.677 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=30075 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:32:37.677 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=30075 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:32:37.677 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=30075 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:32:37.677 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=30075 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:32:42.682 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:32:42.682 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:32:42.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:32:42.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:32:42.682 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:32:42.682 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:32:42.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:32:42.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:32:42.692 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:42.693 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:32:42.693 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:32:42.697 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:32:42.697 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:32:42.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:32:42.698 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:42.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:32:42.699 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:32:42.699 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:32:42.699 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:32:42.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:42.701 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:32:42.701 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:32:42.702 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:32:42.702 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:42.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:32:42.702 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:32:42.702 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:32:42.702 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:32:42.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:42.704 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:32:42.704 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:32:42.704 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:32:42.704 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:42.704 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:32:42.704 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:32:42.704 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:32:42.704 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:32:42.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:42.707 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:32:42.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:32:42.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:32:42.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:32:42.707 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:32:42.708 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:32:42.708 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:32:42.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:32:42.710 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:32:42.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:32:47.717 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:32:47.717 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:32:47.717 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:32:47.717 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:32:47.717 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:32:47.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:32:47.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:32:47.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:32:47.735 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:47.736 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:32:47.736 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:32:47.740 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:32:47.740 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:32:47.741 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:32:47.741 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:47.741 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:32:47.741 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:32:47.742 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:32:47.742 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:32:47.742 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:47.744 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:32:47.744 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:32:47.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:32:47.745 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:47.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:32:47.745 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:32:47.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:32:47.745 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:32:47.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:47.747 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:32:47.747 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:32:47.747 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:32:47.747 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:32:47.747 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:32:47.747 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:32:47.747 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:32:47.747 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:32:47.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:47.750 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:32:47.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:32:47.750 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:32:47.750 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:32:47.750 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:32:47.750 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:32:47.751 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:32:47.751 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:32:47.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:32:47.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:32:47.756 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:32:48.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:32:48.277 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:32:48.278 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:32:48.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:48.280 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:32:48.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:48.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:48.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:48.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:48.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:48.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:48.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:48.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:48.331 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:48.331 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:48.332 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:32:48.332 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:32:48.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:48.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:48.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:48.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:48.703 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:32:48.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:48.755 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:48.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:48.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:49.177 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:32:49.649 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:32:49.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:49.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:49.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:49.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:49.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:49.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:49.818 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:49.818 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:49.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:49.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:49.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:49.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:49.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:49.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:49.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:49.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:49.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:49.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:49.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:32:49.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:32:49.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:49.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:49.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:49.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:50.119 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:32:50.590 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:32:50.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:50.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:50.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:50.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:51.064 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:32:51.536 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:32:51.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:51.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:51.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:51.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:52.006 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:32:52.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:52.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:52.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:52.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:52.214 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:52.214 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:52.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:52.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:52.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:52.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:52.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:52.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:52.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:52.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:52.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:32:52.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:32:52.235 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:52.235 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:52.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:52.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:52.478 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:32:52.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:52.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:52.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:52.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:52.950 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:32:53.421 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:32:53.892 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:32:54.363 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:32:54.833 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:32:55.304 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:32:55.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:55.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:55.698 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:55.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:55.716 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:55.716 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:55.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:55.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:55.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:55.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:32:55.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:55.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:55.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:55.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:55.724 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:32:55.724 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:32:55.773 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:32:55.773 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:32:55.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:55.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:55.774 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:32:56.246 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:32:56.719 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:32:57.192 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:32:57.664 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:32:58.135 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:32:58.609 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:32:59.081 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:32:59.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:32:59.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:32:59.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:32:59.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:32:59.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:32:59.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:32:59.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:32:59.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:32:59.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:32:59.181 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:32:59.181 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:32:59.181 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:32:59.181 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:32:59.181 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:32:59.181 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:33:04.187 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:33:04.187 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:33:04.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:33:04.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:33:04.187 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:33:04.187 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:33:04.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:33:04.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:33:04.196 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:33:04.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:33:04.196 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:33:04.201 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:33:04.201 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:33:04.201 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:33:04.201 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:33:04.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:33:04.201 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:33:04.202 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:33:04.202 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:33:04.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:33:04.205 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:33:04.206 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:33:04.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:33:04.206 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:33:04.206 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:33:04.206 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:33:04.206 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:33:04.206 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:33:04.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:33:04.210 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:33:04.210 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:33:04.210 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:33:04.210 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:33:04.210 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:33:04.210 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:33:04.210 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:33:04.211 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:33:04.211 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.216 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:33:04.217 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:33:04.217 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:33:04.217 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.218 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:33:04.219 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:33:04.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:33:04.222 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:33:04.701 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:33:04.747 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:33:04.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:04.750 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:33:04.753 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:33:04.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:04.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:04.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:04.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:04.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:04.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:04.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:04.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:04.805 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:04.805 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:04.806 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:33:04.806 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:33:04.839 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:04.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:04.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:04.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:05.171 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:33:05.220 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:33:05.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:33:05.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:33:05.221 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:33:05.644 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:33:06.117 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:33:06.222 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:33:06.222 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:33:06.222 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:33:06.222 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:33:06.588 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:33:07.061 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:33:07.224 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:33:07.224 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:33:07.224 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:33:07.224 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:33:07.533 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:33:08.006 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:33:08.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:33:08.226 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:33:08.226 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:33:08.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:33:08.477 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:33:08.950 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:33:09.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:33:09.227 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:33:09.227 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:33:09.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:33:09.423 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:33:09.895 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:33:10.369 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:33:10.841 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:33:11.314 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:33:11.787 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:33:12.260 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:33:12.732 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:33:13.206 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:33:13.678 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:33:14.151 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:33:14.622 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:33:15.095 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:33:15.568 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:33:16.040 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:33:16.513 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:33:16.986 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:33:17.458 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:33:17.929 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:33:18.400 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:33:18.873 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:33:19.346 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:33:19.818 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:33:20.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:20.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:20.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:20.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:20.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:20.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:20.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:20.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:20.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:20.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:20.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:20.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:20.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:20.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:20.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:33:20.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:33:20.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:20.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:20.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:20.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:20.289 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:33:20.760 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:33:21.231 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:33:21.702 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:33:22.175 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:33:22.648 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:33:23.120 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:33:23.591 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:33:24.064 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:33:24.537 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:33:25.009 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:33:25.483 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:33:25.955 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:33:26.427 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:33:26.898 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:33:27.369 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:33:27.840 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:33:28.310 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:33:28.784 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:33:29.257 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:33:29.728 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:33:30.200 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:33:30.673 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:33:31.146 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:33:31.618 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:33:32.092 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:33:32.564 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:33:33.036 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:33:33.507 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:33:33.978 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:33:34.449 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:33:34.919 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:33:35.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:35.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:35.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:35.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:35.289 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:35.289 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:35.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:35.295 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:35.295 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:35.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:35.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:35.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:35.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:35.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:35.297 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:33:35.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:33:35.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:35.337 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:35.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:35.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:35.390 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:33:35.861 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:33:36.334 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:33:36.806 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:33:37.279 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:33:37.749 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:33:38.220 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:33:38.694 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:33:39.166 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:33:39.638 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:33:40.112 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:33:40.584 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:33:41.056 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:33:41.527 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:33:41.998 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:33:42.469 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:33:42.942 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:33:43.415 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:33:43.887 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:33:44.358 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:33:44.828 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:33:45.302 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:33:45.774 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:33:46.246 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:33:46.717 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:33:47.188 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:33:47.661 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:33:48.134 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:33:48.606 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:33:49.077 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:33:49.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:49.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:49.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:49.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:49.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:49.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:49.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:49.533 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:33:49.533 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:33:49.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:33:49.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:33:49.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:49.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:49.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:49.534 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:33:49.534 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:33:49.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:33:49.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:33:49.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:49.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:33:49.547 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:33:50.018 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:33:50.489 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:33:50.963 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:33:51.435 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:33:51.907 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 02:33:52.378 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 02:33:52.851 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 02:33:53.324 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 02:33:53.796 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 02:33:54.267 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 02:33:54.740 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 02:33:55.213 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 02:33:55.685 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 02:33:56.156 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 02:33:56.629 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 02:33:57.102 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 02:33:57.574 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 02:33:58.045 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 02:33:58.515 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 02:33:58.989 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 02:33:59.461 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 02:33:59.933 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 02:34:00.404 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 02:34:00.878 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 02:34:01.350 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 02:34:01.822 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 02:34:02.293 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 02:34:02.764 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 02:34:03.237 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 02:34:03.710 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 02:34:04.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:04.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:04.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:04.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:04.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:04.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:04.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:04.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:04.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:04.123 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:34:04.123 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:34:04.123 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:34:04.124 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:04.124 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:04.124 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:04.124 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=12943 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:04.124 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=12943 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:04.124 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=12943 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:04.124 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=12943 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:04.124 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=12943 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:04.124 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=12943 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:09.126 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:34:09.126 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:34:09.126 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:09.126 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:09.126 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:09.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:09.133 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:09.135 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:34:09.135 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:09.135 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:34:09.135 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:34:09.139 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:34:09.139 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:34:09.140 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:34:09.140 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:09.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:09.140 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:34:09.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:34:09.141 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:34:09.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:09.142 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:34:09.142 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:34:09.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:34:09.142 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:09.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:09.142 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:34:09.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:34:09.142 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:34:09.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:09.144 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:34:09.145 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:34:09.145 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:34:09.145 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:09.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:09.145 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:34:09.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:34:09.146 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:34:09.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:34:09.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:34:09.150 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:34:09.150 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:34:09.150 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:09.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:09.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:09.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:09.152 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:34:09.152 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:34:09.152 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:34:09.152 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:09.152 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:14.160 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:34:14.160 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:34:14.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:14.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:14.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:14.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:14.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:14.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:34:14.173 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:14.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:34:14.173 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:34:14.176 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:34:14.177 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:34:14.177 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:34:14.177 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:14.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:14.178 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:34:14.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:34:14.178 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:34:14.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:14.180 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:34:14.180 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:34:14.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:34:14.180 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:14.180 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:14.181 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:34:14.181 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:34:14.181 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:34:14.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:14.182 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:34:14.182 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:34:14.182 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:34:14.182 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:14.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:14.183 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:34:14.183 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:34:14.183 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:34:14.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:14.185 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:34:14.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:34:14.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:34:14.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:34:14.185 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:34:14.186 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:34:14.186 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:34:14.186 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:14.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:14.191 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:34:14.669 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:34:14.711 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:34:14.712 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:34:14.713 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:34:14.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:14.730 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:14.730 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:14.730 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:14.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:14.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:14.752 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:14.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:14.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:14.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:14.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:14.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:14.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:14.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:14.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:14.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:14.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:15.141 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:34:15.189 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:15.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:15.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:15.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:15.612 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:34:16.086 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:34:16.191 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:16.191 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:16.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:16.191 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:16.558 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:34:17.031 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:34:17.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:17.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:17.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:17.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:17.502 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:34:17.975 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:34:18.193 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:18.193 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:18.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:18.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:18.447 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:34:18.920 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:34:19.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:19.195 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:19.195 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:19.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:19.391 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:34:19.864 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:34:20.337 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:34:20.809 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:34:21.280 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:34:21.753 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:34:22.226 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:34:22.698 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:34:23.169 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:34:23.642 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:34:24.115 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:34:24.587 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:34:25.061 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:34:25.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:25.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:25.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:25.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:25.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:25.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:25.282 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:25.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:25.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:25.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:25.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:25.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:25.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:25.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:25.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:25.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:25.337 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:25.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:25.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:25.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:25.533 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:34:26.005 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:34:26.476 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:34:26.946 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:34:27.417 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:34:27.891 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:34:28.363 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:34:28.835 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:34:29.309 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:34:29.781 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:34:30.253 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:34:30.724 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:34:31.195 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:34:31.666 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:34:32.137 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:34:32.610 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:34:33.083 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:34:33.555 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:34:34.026 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:34:34.499 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:34:34.972 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:34:35.444 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:34:35.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:35.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:35.616 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:35.616 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:35.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:35.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:35.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:35.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:35.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:35.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:35.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:35.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:35.639 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:35.639 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:35.639 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:35.639 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:35.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:35.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:35.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:35.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:35.915 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:34:36.386 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:34:36.859 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:34:37.331 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:34:37.804 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:34:38.275 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:34:38.748 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:34:39.220 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:34:39.692 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:34:40.163 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:34:40.637 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:34:41.109 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:34:41.581 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:34:42.054 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:34:42.527 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:34:42.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:42.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:42.567 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:42.567 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:42.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:42.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:42.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:42.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:42.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:42.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:42.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:42.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:42.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:42.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:42.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:42.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:42.618 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:42.618 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:42.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:42.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:42.998 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:34:43.470 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:34:43.941 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:34:44.414 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:34:44.887 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:34:45.359 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:34:45.830 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:34:46.303 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:34:46.775 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:34:47.248 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:34:47.721 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:34:48.194 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:34:48.666 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:34:49.137 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:34:49.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:49.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:49.605 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:49.605 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:49.610 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:34:49.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:49.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:49.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:49.620 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:49.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:49.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:49.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:49.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:49.624 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:34:49.624 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:34:49.625 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:34:49.625 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:49.625 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:49.625 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:49.625 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:49.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:49.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:49.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:49.626 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7656 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:34:54.627 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:34:54.627 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:34:54.627 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:54.627 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:54.627 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:54.627 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:54.637 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:54.639 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:34:54.639 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:54.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:34:54.640 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:34:54.647 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:34:54.647 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:34:54.648 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:34:54.648 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:54.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:54.649 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:34:54.650 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:34:54.650 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:34:54.650 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:54.654 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:34:54.654 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:34:54.655 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:34:54.655 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:54.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:54.656 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:34:54.656 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:34:54.656 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:34:54.656 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:54.658 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:34:54.658 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:34:54.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:34:54.659 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:34:54.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:54.659 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:34:54.659 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:34:54.659 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:34:54.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:54.663 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:34:54.663 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.664 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:34:54.664 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:34:54.664 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:34:54.664 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.665 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:34:54.669 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:34:55.146 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:34:55.192 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:34:55.194 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:34:55.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:55.196 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:34:55.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:55.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:55.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:55.239 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:55.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:55.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:55.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:55.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:55.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:55.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:55.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:55.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:55.284 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:55.285 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:55.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:55.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:55.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:55.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:55.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:55.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:55.616 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:34:55.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:55.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:55.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:55.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:55.624 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:55.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:55.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:55.626 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:55.626 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:55.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:55.627 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:55.627 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:55.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:55.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:55.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:55.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:55.667 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:55.667 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:55.668 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:55.668 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:56.085 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:34:56.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:56.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:56.141 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:56.141 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:56.156 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:56.156 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:56.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:56.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:56.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:56.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:56.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:56.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:56.162 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:56.162 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:56.162 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:56.162 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:56.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:56.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:56.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:56.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:56.556 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:34:56.668 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:56.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:56.669 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:56.670 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:56.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:56.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:56.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:56.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:56.969 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:56.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:56.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:56.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:56.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:56.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:34:56.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:56.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:56.977 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:56.977 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:56.977 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:34:56.977 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:34:57.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:34:57.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:34:57.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:57.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:57.028 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:34:57.500 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:34:57.669 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:57.669 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:57.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:57.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:57.813 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:34:57.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:34:57.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:34:57.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:34:57.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:34:57.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:34:57.829 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:34:57.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:34:57.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:34:57.831 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:34:57.831 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:34:57.831 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:34:57.831 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:34:57.831 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:34:57.831 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:35:02.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:35:02.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:35:02.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:02.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:02.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:02.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:02.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:02.850 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:02.850 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:02.850 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:02.851 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:35:02.853 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:35:02.853 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:35:02.854 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:02.854 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:02.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:02.854 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:35:02.855 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:02.855 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:35:02.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:02.856 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:35:02.856 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:35:02.856 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:02.856 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:02.857 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:02.857 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:35:02.857 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:02.857 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:35:02.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:02.859 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:35:02.859 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:35:02.859 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:02.859 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:02.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:02.860 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:35:02.860 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:02.860 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:35:02.860 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:02.863 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:35:02.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:35:02.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:35:02.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:35:02.863 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:35:02.864 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:35:02.864 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:35:02.864 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.864 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:02.866 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:02.869 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:35:03.347 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:35:03.391 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:35:03.393 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:35:03.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:03.394 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:35:03.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:03.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:03.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:03.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:03.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:03.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:03.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:03.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:03.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:03.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:03.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:03.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:03.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:03.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:03.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:03.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:03.818 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:35:03.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:03.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:03.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:03.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:04.290 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:35:04.761 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:35:04.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:04.870 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:04.870 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:04.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:05.234 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:35:05.707 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:35:05.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:05.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:05.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:05.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:06.179 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:35:06.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:06.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:06.650 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:35:06.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:06.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:06.671 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:06.671 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:06.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:06.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:06.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:06.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:06.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:06.679 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:06.679 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:06.679 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:06.679 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:06.679 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:06.692 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:06.692 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:06.692 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:06.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:06.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:06.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:06.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:06.872 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:07.121 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:35:07.594 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:35:07.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:07.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:07.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:07.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:08.067 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:35:08.539 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:35:09.010 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:35:09.481 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:35:09.953 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:35:10.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:10.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:10.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:10.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:10.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:10.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:10.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:10.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:10.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:10.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:10.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:10.063 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:10.063 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:10.063 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:10.063 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:10.063 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:10.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:10.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:10.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:10.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:10.425 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:35:10.898 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:35:11.369 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:35:11.839 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:35:12.313 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:35:12.785 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:35:13.257 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:35:13.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:13.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:13.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:13.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:13.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:13.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:13.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:13.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:13.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:13.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:13.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:13.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:13.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:13.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:13.677 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:13.677 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:13.728 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:35:13.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:13.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:13.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:13.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:14.199 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:35:14.672 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:35:15.145 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:35:15.617 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:35:16.088 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:35:16.559 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:35:17.033 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:35:17.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:17.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:17.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:17.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:17.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:17.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:17.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:17.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:17.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:17.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:35:17.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:35:17.370 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:35:17.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:17.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:17.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:17.370 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3135 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:17.370 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3135 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:17.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3135 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:17.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3135 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:17.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3135 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:17.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3135 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:17.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3135 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:22.372 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:35:22.372 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:35:22.372 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:22.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:22.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:22.372 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:22.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:22.381 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:22.381 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:22.381 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:22.382 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:35:22.385 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:35:22.386 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:35:22.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:22.386 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:22.387 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:22.387 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:35:22.387 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:22.387 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:35:22.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:22.389 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:35:22.389 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:35:22.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:22.389 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:22.389 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:22.390 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:35:22.390 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:22.390 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:35:22.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:22.392 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:35:22.392 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:35:22.392 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:22.392 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:22.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:22.392 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:35:22.393 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:22.393 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:35:22.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:35:22.396 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:35:22.396 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:35:22.396 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:22.397 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:22.401 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:35:22.880 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:35:22.923 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:35:22.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:22.927 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:35:22.929 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:35:22.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:22.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:22.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:22.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:22.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:22.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:22.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:22.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:22.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:22.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:22.989 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:22.989 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:23.018 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:23.018 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:23.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:23.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:23.352 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:35:23.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:23.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:23.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:23.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:23.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:23.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:23.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:23.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:23.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:23.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:23.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:23.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:23.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:23.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:23.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:23.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:23.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:23.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:23.426 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:23.426 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:23.444 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:23.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:23.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:23.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:23.826 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:35:24.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:24.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:24.042 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:24.042 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:24.056 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:24.056 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:24.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:24.062 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:24.062 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:24.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:24.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:24.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:24.064 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:24.064 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:24.064 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:24.064 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:24.102 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:24.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:24.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:24.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:24.298 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:35:24.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:24.400 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:24.400 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:24.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:24.770 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:35:25.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:25.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:25.164 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:25.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:25.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:25.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:25.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:25.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:25.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:25.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:25.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:25.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:25.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:25.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:25.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:25.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:25.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:25.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:25.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:25.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:25.240 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:35:25.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:25.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:25.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:25.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:25.712 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:35:26.185 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:35:26.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:26.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:26.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:26.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:26.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:26.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:26.280 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:26.280 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:26.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:26.284 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:35:26.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:35:26.285 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:35:26.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:26.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:26.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:26.285 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=840 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:26.285 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=840 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:26.286 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=840 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:26.286 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=840 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:26.286 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=840 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:26.286 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=840 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:26.286 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=840 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:35:31.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:35:31.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:35:31.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:31.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:31.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:31.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:31.296 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:31.296 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:31.296 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:31.297 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:31.297 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:35:31.300 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:35:31.300 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:35:31.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:31.301 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:31.301 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:31.301 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:35:31.302 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:31.302 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:35:31.302 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:31.304 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:35:31.304 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:35:31.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:31.304 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:31.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:31.305 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:35:31.305 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:31.305 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:35:31.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:31.308 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:35:31.309 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:35:31.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:31.309 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:31.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:31.309 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:35:31.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:31.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:35:31.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:31.314 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:35:31.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:35:31.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:35:31.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.316 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:35:31.316 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:35:31.316 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:35:31.316 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:35:31.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:35:31.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:31.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:31.321 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:35:31.799 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:35:31.847 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:35:31.849 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:35:31.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:31.851 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:35:31.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:31.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:31.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:31.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:31.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:31.896 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:31.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:31.902 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:31.902 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:31.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:31.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:31.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:31.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:31.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:31.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:31.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:32.269 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:35:32.320 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:32.320 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:32.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:32.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:32.742 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:35:33.215 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:35:33.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:33.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:33.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:33.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:33.685 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:35:34.159 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:35:34.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:34.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:34.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:34.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:34.631 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:35:34.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:34.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:34.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:34.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:34.806 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:34.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:34.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:34.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:34.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:34.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:34.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:34.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:34.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:34.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:34.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:34.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:34.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:34.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:34.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:34.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:35.104 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:35:35.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:35.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:35.575 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:35:36.048 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:35:36.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:36.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:36.325 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:36.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:36.521 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:35:36.993 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:35:37.464 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:35:37.934 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:35:38.405 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:35:38.879 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:35:39.351 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:35:39.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:39.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:39.378 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:39.378 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:39.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:39.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:39.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:39.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:39.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:39.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:39.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:39.406 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:39.406 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:39.406 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:39.406 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:39.406 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:39.443 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:39.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:39.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:39.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:39.823 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:35:40.294 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:35:40.767 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:35:41.240 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:35:41.712 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:35:42.186 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:35:42.658 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:35:43.130 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:35:43.601 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:35:44.072 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:35:44.546 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:35:45.018 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:35:45.490 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:35:45.961 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:35:46.115 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:46.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:46.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:46.120 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:46.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:46.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:46.139 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:46.146 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:46.146 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:46.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:46.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:46.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:46.148 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:46.148 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:46.148 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:46.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:46.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:46.195 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:46.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:46.195 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:46.432 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:35:46.905 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:35:47.378 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:35:47.850 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:35:48.321 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:35:48.794 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:35:49.266 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:35:49.738 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:35:50.209 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:35:50.683 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:35:51.155 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:35:51.627 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:35:52.098 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:35:52.571 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:35:52.886 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:52.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:52.889 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:52.889 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:52.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:35:52.896 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:35:52.896 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:35:52.896 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:57.903 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:35:57.904 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:35:57.904 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:57.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:57.904 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:57.904 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:57.911 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:35:57.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:57.911 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:57.912 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:35:57.912 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:35:57.914 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:35:57.914 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:35:57.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:57.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:57.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:35:57.916 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:35:57.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:35:57.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:35:57.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:57.917 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:35:57.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:35:57.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:57.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:57.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:35:57.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:35:57.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:35:57.918 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:35:57.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:57.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:35:57.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:35:57.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:57.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:35:57.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:35:57.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:35:57.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:35:57.920 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:35:57.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:35:57.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:35:57.924 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:35:57.924 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:35:57.924 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:35:57.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:35:57.928 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:35:58.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:35:58.443 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:35:58.445 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:35:58.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:58.446 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:35:58.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:58.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:58.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:58.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:35:58.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:35:58.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:35:58.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:35:58.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:58.488 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:58.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:58.489 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:35:58.489 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:35:58.497 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:35:58.497 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:35:58.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:58.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:35:58.878 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:35:58.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:58.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:58.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:58.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:35:59.349 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:35:59.822 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:35:59.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:35:59.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:35:59.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:35:59.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:00.223 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:00.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:00.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:00.228 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:00.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:00.246 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:00.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:36:00.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:00.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:00.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:36:00.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:00.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:00.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:36:00.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:36:00.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:36:00.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:36:00.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:36:00.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:36:00.288 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:00.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:00.294 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:36:00.766 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:36:00.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:00.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:00.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:00.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:01.237 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:36:01.708 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:36:01.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:01.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:01.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:01.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:02.182 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:36:02.654 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:36:02.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:02.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:02.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:02.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:03.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:03.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:03.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:03.060 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:03.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:03.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:03.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:36:03.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:03.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:03.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:36:03.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:03.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:03.088 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:36:03.088 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:36:03.088 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:36:03.088 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:36:03.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:36:03.126 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:36:03.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:36:03.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:03.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:03.597 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:36:04.068 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:36:04.539 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:36:05.010 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:36:05.483 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:36:05.955 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:36:06.428 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:36:06.898 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:36:07.372 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:36:07.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:07.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:07.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:07.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:07.548 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:07.548 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:07.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:36:07.555 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:07.555 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:07.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:36:07.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:07.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:07.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:36:07.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:36:07.557 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:36:07.557 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:36:07.603 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:36:07.603 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:36:07.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:07.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:07.845 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:36:08.317 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:36:08.788 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:36:09.261 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:36:09.733 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:36:10.206 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:36:10.679 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:36:11.151 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:36:11.623 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:36:11.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:36:11.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:11.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:36:11.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:36:11.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:11.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:11.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:11.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:11.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:11.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:11.954 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:11.954 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:11.954 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:36:11.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:11.954 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:16.960 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:16.960 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:16.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:16.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:16.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:16.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:16.968 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:16.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:16.969 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:16.969 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:16.969 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:36:16.972 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:36:16.972 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:36:16.973 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:16.973 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:16.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:16.974 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:36:16.974 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:16.974 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:36:16.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:16.976 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:36:16.976 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:36:16.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:16.976 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:16.977 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:16.977 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:36:16.977 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:16.977 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:36:16.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:16.979 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:36:16.979 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:36:16.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:16.979 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:16.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:16.979 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:36:16.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:16.979 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:36:16.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:16.982 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:36:16.982 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:36:16.982 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:36:16.982 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:36:16.982 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:36:16.983 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:36:16.983 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:36:16.983 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:16.988 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:36:17.466 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:36:17.507 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:36:17.509 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:36:17.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:17.511 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:36:17.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:17.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:17.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:17.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:17.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:17.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:17.938 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:36:17.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:17.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:17.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:17.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:18.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.410 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:36:18.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:18.804 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:18.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:18.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:18.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:18.805 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:18.805 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:18.805 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:18.805 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:36:18.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:18.805 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:18.805 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:18.805 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=394 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:18.805 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=394 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:18.805 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=394 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:18.805 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=394 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:18.805 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=394 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:18.805 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=394 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:23.812 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:23.812 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:23.812 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:23.812 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:23.812 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:23.812 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:23.819 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:23.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:23.820 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:23.820 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:23.820 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:36:23.822 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:36:23.823 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:36:23.823 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:23.823 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:23.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:23.824 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:36:23.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:23.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:36:23.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:23.825 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:36:23.825 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:36:23.825 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:23.825 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:23.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:23.825 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:36:23.826 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:23.826 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:36:23.826 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:23.827 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:36:23.827 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:36:23.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:23.827 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:23.827 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:23.827 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:36:23.827 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:23.827 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:36:23.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:36:23.830 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:36:23.830 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:36:23.830 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:36:23.830 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:23.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:23.835 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:36:24.314 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:36:24.354 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:36:24.356 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:36:24.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.357 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:36:24.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:24.783 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:36:24.833 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:24.833 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:24.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:24.834 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:25.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.251 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:36:25.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:25.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:25.712 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:25.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:25.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:25.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:25.714 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:25.714 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:25.714 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:25.714 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:25.714 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:25.714 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:36:25.714 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=408 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:25.714 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=408 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:25.714 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=408 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:25.714 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=408 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:25.714 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=408 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:25.714 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=408 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:25.714 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=408 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:30.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:30.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:30.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:30.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:30.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:30.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:30.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:30.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:30.728 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:30.728 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:30.728 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:36:30.731 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:36:30.731 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:36:30.732 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:30.732 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:30.732 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:30.732 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:36:30.732 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:30.733 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:36:30.733 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:30.734 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:36:30.734 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:36:30.734 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:30.734 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:30.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:30.734 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:36:30.734 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:30.734 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:36:30.735 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:30.736 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:36:30.736 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:36:30.736 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:30.736 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:30.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:30.737 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:36:30.737 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:30.737 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:36:30.737 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:36:30.740 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:36:30.740 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:36:30.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:30.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:30.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:30.744 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:36:31.222 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:36:31.266 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:36:31.268 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:36:31.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.270 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:36:31.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.690 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:36:31.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:31.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:31.743 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:31.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:31.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:31.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.161 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:36:32.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.597 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:32.617 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:32.617 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:32.617 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:32.617 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:32.620 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:32.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:32.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:32.620 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:32.620 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:32.620 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:32.620 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:36:37.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:37.624 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:37.624 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:37.624 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:37.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:37.624 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:37.631 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:37.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:37.632 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:37.632 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:37.632 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:36:37.635 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:36:37.635 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:36:37.635 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:37.635 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:37.635 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:37.636 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:36:37.636 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:37.636 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:36:37.636 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:37.637 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:36:37.637 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:36:37.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:37.638 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:37.638 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:37.638 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:36:37.638 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:37.638 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:36:37.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:37.639 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:36:37.640 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:36:37.640 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:37.640 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:37.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:37.640 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:36:37.640 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:37.640 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:36:37.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:37.642 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:36:37.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:36:37.642 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:36:37.642 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:36:37.642 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:36:37.642 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:36:37.643 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:36:37.643 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:36:37.643 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.643 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:37.648 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:36:38.127 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:36:38.164 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:36:38.165 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:36:38.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.167 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:36:38.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.207 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.598 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:36:38.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:38.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:38.645 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:38.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:38.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:38.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:39.070 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:36:39.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:39.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:39.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:39.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:39.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:39.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:39.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:39.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:39.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:39.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:39.510 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:39.510 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:39.510 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:39.510 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:36:39.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:39.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:39.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:39.511 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:39.511 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:39.511 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:39.511 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:39.511 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:39.511 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:39.511 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:44.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:44.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:44.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:44.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:44.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:44.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:44.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:44.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:44.522 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:44.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:44.523 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:36:44.526 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:36:44.526 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:36:44.526 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:44.526 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:44.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:44.527 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:36:44.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:44.528 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:36:44.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:44.529 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:36:44.529 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:36:44.529 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:44.529 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:44.529 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:44.530 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:36:44.530 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:44.530 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:36:44.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:44.531 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:36:44.531 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:36:44.531 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:44.531 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:44.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:44.531 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:36:44.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:44.532 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:36:44.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.534 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:36:44.535 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:36:44.535 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:36:44.535 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:44.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:44.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:44.539 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:36:45.018 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:36:45.060 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:36:45.062 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:36:45.063 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:36:45.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:45.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.490 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:36:45.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:45.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:45.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:45.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:45.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:45.960 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:36:46.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:46.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:46.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:46.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:46.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:46.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:46.386 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:46.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:46.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:46.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:46.390 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:46.391 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:46.391 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:46.391 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:36:46.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:46.391 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:46.392 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:46.392 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=401 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:46.392 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=401 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:46.392 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=401 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:46.392 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=401 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:46.392 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=401 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:46.392 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=401 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:46.392 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=401 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:51.394 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:51.394 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:51.394 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:51.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:51.394 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:51.394 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:51.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:51.403 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:51.403 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:51.403 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:51.403 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:36:51.406 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:36:51.407 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:36:51.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:51.407 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:51.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:51.407 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:36:51.407 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:51.408 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:36:51.408 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:51.409 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:36:51.410 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:36:51.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:51.410 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:51.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:51.410 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:36:51.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:51.410 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:36:51.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:51.412 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:36:51.412 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:36:51.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:51.412 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:51.412 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:51.412 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:36:51.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:51.412 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:36:51.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:36:51.415 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:36:51.415 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:36:51.415 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.415 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.420 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:36:51.897 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:36:51.937 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:36:51.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:51.940 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:36:51.942 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:36:51.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:51.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:51.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:51.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.277 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.366 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:36:52.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:52.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:52.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:52.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:52.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.838 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:36:52.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:52.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:53.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:53.261 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:53.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:53.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:53.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:53.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:53.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:53.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:53.286 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:53.287 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:53.287 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:53.287 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:36:53.287 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:53.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:53.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:53.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=406 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:53.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=406 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:53.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=406 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:53.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=406 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:53.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=406 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:53.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=406 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:53.289 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=406 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:36:58.290 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:36:58.290 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:36:58.290 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:58.290 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:58.290 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:58.290 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:58.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:36:58.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:58.300 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:58.300 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:36:58.300 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:36:58.306 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:36:58.306 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:36:58.307 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:58.307 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:58.307 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:36:58.308 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:36:58.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:36:58.309 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:36:58.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:58.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:36:58.311 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:36:58.312 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:58.312 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:58.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:36:58.313 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:36:58.313 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:36:58.313 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:36:58.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:58.316 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:36:58.316 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:36:58.316 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:58.316 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:36:58.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:36:58.317 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:36:58.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:36:58.317 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:36:58.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:58.322 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:36:58.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:36:58.322 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:36:58.322 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:36:58.322 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:36:58.322 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:36:58.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:36:58.323 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:36:58.323 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:36:58.323 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.328 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:36:58.805 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:36:58.855 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:36:58.856 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:36:58.857 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:36:58.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:58.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:36:58.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:58.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:58.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.277 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:36:59.328 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:36:59.328 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:36:59.328 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:36:59.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:36:59.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.531 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.747 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:36:59.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.849 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:36:59.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:00.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:00.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:00.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:00.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:00.164 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:00.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:00.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:00.165 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:00.165 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:00.165 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:00.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:00.165 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:00.165 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:00.165 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:05.171 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:05.171 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:05.171 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:05.171 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:05.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:05.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:05.179 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:05.181 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:05.181 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:05.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:05.182 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:05.186 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:05.187 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:05.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:05.188 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:05.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:05.189 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:05.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:05.189 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:05.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:05.191 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:05.192 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:05.192 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:05.192 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:05.192 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:05.193 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:05.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:05.193 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:05.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:05.195 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:05.195 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:05.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:05.195 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:05.195 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:05.195 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:05.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:05.195 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:05.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:05.200 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:05.200 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:05.200 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:05.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:05.204 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:05.681 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:05.728 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:05.730 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:05.731 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.732 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:05.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.803 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:05.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:05.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:05.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:05.811 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:10.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:10.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:10.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:10.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:10.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:10.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:10.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:10.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:10.823 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:10.823 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:10.824 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:10.827 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:10.828 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:10.828 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:10.828 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:10.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:10.828 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:10.829 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:10.829 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:10.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:10.833 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:10.833 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:10.833 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:10.833 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:10.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:10.833 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:10.834 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:10.834 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:10.834 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:10.837 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:10.837 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:10.837 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:10.837 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:10.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:10.838 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:10.838 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:10.838 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:10.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:10.843 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:10.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:10.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:10.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:10.843 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.844 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:10.844 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:10.844 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:10.845 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.845 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:10.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:10.849 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:11.327 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:11.382 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:11.384 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:11.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.386 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:11.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.470 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.477 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.495 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:11.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:11.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:11.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:11.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:11.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:11.501 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:11.501 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:11.501 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:11.501 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:11.501 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:11.501 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:16.512 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:16.512 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:16.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:16.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:16.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:16.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:16.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:16.522 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:16.523 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:16.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:16.523 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:16.526 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:16.526 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:16.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:16.527 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:16.527 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:16.527 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:16.527 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:16.527 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:16.528 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:16.529 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:16.529 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:16.530 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:16.530 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:16.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:16.530 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:16.530 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:16.530 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:16.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:16.532 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:16.532 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:16.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:16.532 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:16.532 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:16.532 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:16.532 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:16.532 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:16.532 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:16.536 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:16.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:16.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:16.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:16.536 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:16.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:16.537 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:16.537 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:16.537 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:16.542 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:17.020 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:17.063 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:17.065 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:17.067 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:17.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.103 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.124 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:17.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:17.166 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:17.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:17.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:17.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:17.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:17.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:17.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:17.167 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:17.167 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:17.167 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:22.175 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:22.175 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:22.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:22.175 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:22.175 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:22.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:22.181 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:22.182 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:22.182 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:22.183 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:22.183 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:22.186 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:22.186 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:22.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:22.187 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:22.187 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:22.187 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:22.187 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:22.187 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:22.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:22.189 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:22.190 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:22.190 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:22.190 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:22.190 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:22.190 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:22.190 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:22.190 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:22.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:22.192 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:22.192 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:22.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:22.192 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:22.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:22.192 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:22.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:22.192 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:22.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:22.195 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:22.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:22.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:22.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:22.195 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:22.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:22.196 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:22.196 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:22.196 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:22.201 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:22.679 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:22.721 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:22.723 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:22.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.726 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:22.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.766 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.792 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:22.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:22.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:22.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:22.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:22.809 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:22.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:22.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:22.810 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:22.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:22.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:22.810 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:22.810 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:22.810 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:22.810 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:22.810 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:22.810 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:22.810 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:27.816 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:27.816 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:27.816 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:27.816 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:27.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:27.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:27.823 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:27.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:27.824 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:27.824 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:27.824 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:27.827 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:27.827 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:27.827 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:27.827 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:27.827 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:27.828 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:27.828 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:27.828 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:27.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:27.829 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:27.829 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:27.829 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:27.829 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:27.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:27.830 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:27.830 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:27.830 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:27.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:27.832 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:27.832 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:27.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:27.832 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:27.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:27.832 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:27.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:27.832 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:27.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:27.835 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:27.835 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:27.835 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:27.840 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:28.318 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:28.358 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:28.360 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:28.362 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:28.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:28.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:28.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:28.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:28.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:28.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:28.441 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:28.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:28.441 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:28.441 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:28.441 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:28.441 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:28.441 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:33.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:33.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:33.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:33.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:33.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:33.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:33.452 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:33.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:33.453 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:33.453 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:33.453 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:33.456 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:33.456 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:33.457 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:33.457 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:33.457 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:33.457 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:33.458 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:33.458 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:33.458 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:33.459 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:33.459 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:33.459 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:33.459 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:33.459 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:33.459 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:33.459 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:33.459 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:33.459 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:33.461 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:33.461 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:33.461 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:33.461 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:33.461 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:33.461 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:33.461 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:33.461 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:33.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:33.464 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:33.465 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:33.465 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:33.465 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:33.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:33.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:33.469 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:33.947 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:33.991 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:33.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:33.995 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:33.998 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:34.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:34.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.055 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.073 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.091 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.093 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.094 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:34.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:34.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:34.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:34.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:34.105 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:34.105 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:34.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:34.105 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:34.105 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:34.105 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:34.105 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:34.106 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=138 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:34.106 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=138 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:34.106 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=138 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:34.106 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=138 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:37:39.113 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:39.113 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:39.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:39.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:39.113 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:39.113 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:39.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:39.121 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:39.121 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:39.122 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:39.122 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:39.124 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:39.124 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:39.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:39.125 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:39.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:39.125 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:39.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:39.126 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:39.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:39.127 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:39.127 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:39.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:39.127 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:39.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:39.127 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:39.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:39.127 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:39.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:39.129 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:39.129 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:39.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:39.129 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:39.129 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:39.129 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:39.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:39.129 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:39.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:39.132 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:39.132 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:39.132 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.137 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:39.615 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:39.659 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:39.660 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:39.662 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:39.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:39.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.700 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.724 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.736 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:39.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:39.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:39.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:39.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:39.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:39.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:39.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:39.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:39.763 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:39.763 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:39.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:44.770 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:44.770 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:44.770 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:44.770 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:44.770 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:44.770 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:44.777 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:44.778 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:44.778 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:44.778 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:44.778 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:44.780 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:44.781 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:44.781 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:44.781 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:44.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:44.782 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:44.783 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:44.783 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:44.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:44.785 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:44.785 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:44.785 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:44.785 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:44.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:44.786 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:44.786 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:44.786 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:44.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:44.789 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:44.789 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:44.789 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:44.789 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:44.789 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:44.789 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:44.790 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:44.790 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:44.790 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.795 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:44.796 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:44.796 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:44.796 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.796 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:44.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:44.801 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:45.279 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:45.325 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:45.327 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:45.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:45.330 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:45.333 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:37:45.333 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:37:45.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:37:45.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:37:45.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:37:45.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:37:45.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:37:45.334 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:37:45.751 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:37:45.799 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:45.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:45.800 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:45.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:46.223 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:37:46.694 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:37:46.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:46.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:46.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:46.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:47.167 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:37:47.639 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:37:47.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:47.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:47.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:47.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:48.112 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:37:48.585 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:37:48.790 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:37:48.790 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:37:48.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:48.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:48.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:48.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:48.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:48.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:48.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:48.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:48.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:48.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:48.794 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:53.799 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:53.800 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:53.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:53.800 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:53.800 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:53.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:53.807 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:53.808 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:53.808 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:53.809 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:53.809 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:53.812 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:53.812 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:53.813 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:53.813 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:53.813 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:53.814 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:53.814 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:53.815 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:53.815 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:53.817 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:53.817 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:53.817 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:53.817 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:53.818 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:53.818 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:53.818 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:53.818 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:53.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:53.821 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:53.821 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:53.821 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:53.821 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:53.821 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:53.821 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:53.822 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:53.822 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:53.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:53.827 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:53.828 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:53.828 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:53.828 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.829 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:53.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:53.833 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:37:54.311 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:37:54.362 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:37:54.364 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:37:54.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:54.366 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:37:54.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:37:54.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:37:54.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:37:54.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:37:54.393 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:37:54.394 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:37:54.394 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:37:54.394 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:37:54.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:37:54.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:37:54.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:37:54.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:37:54.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:37:54.784 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:37:54.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:54.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:54.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:54.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:54.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:37:54.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:37:54.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:37:54.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:37:54.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:37:54.906 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:37:54.906 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:37:54.906 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:37:54.906 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:37:54.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:37:54.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:37:54.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:37:54.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:54.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:54.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:54.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:54.933 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:54.933 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:54.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:54.933 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:54.933 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:54.933 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:54.933 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:37:59.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:37:59.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:37:59.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:59.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:59.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:59.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:59.946 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:37:59.948 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:59.948 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:59.948 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:37:59.948 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:37:59.951 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:37:59.951 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:37:59.952 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:59.952 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:59.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:37:59.952 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:37:59.953 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:37:59.953 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:37:59.953 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:37:59.954 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:37:59.954 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:37:59.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:59.954 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:59.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:37:59.954 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:37:59.954 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:37:59.954 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:37:59.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:37:59.956 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:37:59.956 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:37:59.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:59.956 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:37:59.956 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:37:59.956 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:37:59.956 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:37:59.956 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:37:59.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.959 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:37:59.959 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:37:59.959 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:37:59.959 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:37:59.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:37:59.964 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:38:00.441 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:38:00.472 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:38:00.473 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:38:00.473 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:38:00.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:00.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:00.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:00.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:38:00.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:00.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:00.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:00.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:38:00.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:38:00.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:38:00.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:00.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:00.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:00.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:00.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:00.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:00.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:00.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:00.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:38:00.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:00.658 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:00.658 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:00.658 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:38:00.658 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:38:00.914 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:38:00.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:00.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:00.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:00.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:01.385 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:38:01.858 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:38:01.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:01.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:01.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:01.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:02.331 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:38:02.803 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:38:02.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:02.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:02.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:02.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:03.274 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:38:03.747 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:38:03.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:03.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:03.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:03.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:04.220 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:38:04.692 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:38:04.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:04.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:04.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:04.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:05.163 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:38:05.633 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:38:06.104 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:38:06.578 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:38:07.051 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:38:07.522 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:38:07.993 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:38:08.466 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:38:08.938 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:38:09.411 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:38:09.881 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:38:10.355 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:38:10.828 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:38:11.300 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:38:11.771 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:38:12.244 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:38:12.717 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:38:13.189 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:38:13.660 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:38:14.131 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:38:14.602 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:38:15.075 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:38:15.548 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:38:15.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:15.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:15.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:15.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:38:15.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:15.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:15.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:15.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:38:15.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:38:15.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:15.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:15.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:15.881 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:15.882 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:15.882 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:15.882 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:15.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:15.886 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:15.886 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:15.886 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:38:15.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:15.887 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:15.887 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:15.887 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3441 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:15.887 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3441 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:15.887 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3441 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:15.887 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3441 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:15.888 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3441 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:15.888 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3441 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:20.890 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:20.890 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:20.890 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:20.890 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:20.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:20.890 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:20.896 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:20.897 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:20.897 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:20.897 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:20.897 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:38:20.900 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:38:20.901 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:38:20.901 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:20.901 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:20.901 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:20.902 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:38:20.902 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:20.902 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:38:20.902 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:20.903 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:38:20.904 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:38:20.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:20.904 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:20.904 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:20.904 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:38:20.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:20.904 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:38:20.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:20.906 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:38:20.906 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:38:20.906 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:20.906 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:20.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:20.907 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:38:20.907 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:20.907 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:38:20.907 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:20.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:38:20.910 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:38:20.910 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:38:20.910 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:20.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.911 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:20.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:20.914 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:38:21.392 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:38:21.436 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:38:21.437 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:38:21.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:21.439 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:38:21.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:21.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:21.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:38:21.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:21.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:21.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:21.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:38:21.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:38:21.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:38:21.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:21.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:21.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:21.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:21.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:21.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:38:21.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:21.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:21.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:21.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:38:21.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:21.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:21.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:21.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:38:21.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:38:21.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:21.814 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:21.814 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:21.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:21.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:21.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:21.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:21.822 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:21.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:21.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:21.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:21.822 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:38:21.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:21.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:21.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=197 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:21.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=197 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:21.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=197 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:21.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=197 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:21.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=197 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:21.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=197 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:38:26.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:26.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:26.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:26.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:26.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:26.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:26.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:26.837 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:26.838 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:26.838 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:26.838 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:38:26.842 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:38:26.842 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:38:26.843 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:26.843 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:26.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:26.844 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:38:26.844 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:26.844 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:38:26.845 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:26.847 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:38:26.847 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:38:26.848 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:26.848 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:26.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:26.849 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:38:26.849 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:26.850 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:38:26.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:26.851 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:38:26.852 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:38:26.852 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:26.852 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:26.852 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:26.852 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:38:26.852 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:26.852 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:38:26.853 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:38:26.858 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:38:26.858 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:38:26.858 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:26.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:26.863 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:38:27.340 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:38:27.385 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:38:27.386 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:38:27.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:27.387 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:38:27.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:27.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:27.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:38:27.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:27.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:27.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:27.410 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:38:27.410 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:38:27.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:38:27.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:27.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:27.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:27.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:27.811 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:38:27.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:27.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:27.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:27.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:28.283 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:38:28.755 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:38:28.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:28.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:28.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:28.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:29.229 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:38:29.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:29.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:29.448 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:29.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:38:29.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:38:29.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:38:29.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:38:29.468 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:38:29.468 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:38:29.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:38:29.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:38:29.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:38:29.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:29.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:29.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:29.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:29.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:29.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:29.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:29.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:29.519 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:29.519 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:29.519 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:38:34.526 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:34.526 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:34.526 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:34.527 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:34.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:34.527 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:34.534 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:34.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:34.535 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:34.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:34.535 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:38:34.537 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:38:34.537 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:38:34.537 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:34.537 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:34.537 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:34.538 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:38:34.538 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:34.538 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:38:34.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:34.539 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:38:34.540 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:38:34.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:34.540 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:34.540 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:34.540 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:38:34.540 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:34.540 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:38:34.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:34.541 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:38:34.541 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:38:34.541 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:34.541 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:34.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:34.541 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:38:34.542 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:34.542 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:38:34.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:34.543 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:38:34.543 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:38:34.543 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:38:34.543 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:38:34.543 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:38:34.544 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:38:34.544 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:38:34.544 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.544 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:34.545 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:34.545 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:38:34.545 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:39.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:39.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:39.547 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:39.547 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:39.547 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:39.547 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:39.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:39.550 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:39.551 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:39.551 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:38:39.551 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:38:39.551 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:38:39.551 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:39.552 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:38:39.552 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:39.552 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:38:39.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:38:39.553 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:38:39.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:38:39.553 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:38:39.553 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:38:39.553 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:39.553 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:38:39.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:39.553 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:38:39.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:38:39.554 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:38:39.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:38:39.555 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:38:39.555 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:38:39.555 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:39.556 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:39.556 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:39.556 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:44.251 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.36.20:5700'
2026-03-01 02:38:44.251 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.36.20:5802)
2026-03-01 02:38:44.251 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.36.20:5801)
2026-03-01 02:38:44.251 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.36.22:6700'
2026-03-01 02:38:44.251 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.36.22:6802)
2026-03-01 02:38:44.251 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.36.22:6801)
2026-03-01 02:38:44.251 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.36.20:5700/1'
2026-03-01 02:38:44.251 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.36.20:5804)
2026-03-01 02:38:44.251 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.36.20:5803)
2026-03-01 02:38:44.251 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.36.20:5700/2'
2026-03-01 02:38:44.251 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.36.20:5806)
2026-03-01 02:38:44.251 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.36.20:5805)
2026-03-01 02:38:44.251 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.36.20:5700/3'
2026-03-01 02:38:44.251 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.36.20:5808)
2026-03-01 02:38:44.251 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.36.20:5807)
2026-03-01 02:38:44.251 [INFO] fake_trx.py:429 Init complete
2026-03-01 02:38:44.251 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-01 02:38:44.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:38:44.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:38:44.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:38:44.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:38:44.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:38:44.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:01.828 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:01.828 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:01.828 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:01.828 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:01.828 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:01.828 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:06.851 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:06.851 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:06.852 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:06.852 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:06.852 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:06.852 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:11.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:11.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:11.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:11.889 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:11.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:11.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:16.912 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:16.912 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:16.912 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:16.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:16.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:16.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:21.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:21.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:21.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:21.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:21.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:21.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:26.981 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:26.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:26.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:26.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:26.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:26.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:32.016 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:32.016 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:32.016 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:32.016 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:32.016 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:32.016 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:37.050 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:37.050 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:37.051 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:37.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:37.051 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:37.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:42.086 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:42.086 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:42.086 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:42.086 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:42.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:42.086 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:47.119 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:47.119 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:47.119 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:47.120 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:47.120 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:47.120 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:39:47.133 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:39:47.133 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:39:47.133 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:39:47.133 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:39:47.133 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 0 -> 1
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:39:47.133 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 0 -> 1
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:39:47.133 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:39:47.133 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 0 -> 1
2026-03-01 02:39:47.134 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:39:47.134 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 0 -> 1
2026-03-01 02:39:47.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:39:52.150 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:52.150 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:52.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:52.150 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:52.150 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:52.150 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:57.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:39:57.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:39:57.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:39:57.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:39:57.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:39:57.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:39:57.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:39:57.173 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:39:57.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:39:57.174 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:40:02.239 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:02.239 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:02.239 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:02.239 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:07.276 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:07.276 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:07.276 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:07.276 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:07.276 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:07.276 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:12.300 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:12.300 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:12.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:12.300 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:12.300 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:12.301 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:17.331 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:17.331 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:17.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:17.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:17.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:17.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:23.445 [INFO] transceiver.py:125 Init transceiver 'BTS@172.18.36.20:5700'
2026-03-01 02:40:23.445 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5702 <-> R:172.18.36.20:5802)
2026-03-01 02:40:23.445 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5701 <-> R:172.18.36.20:5801)
2026-03-01 02:40:23.445 [INFO] transceiver.py:125 Init transceiver 'MS@172.18.36.22:6700'
2026-03-01 02:40:23.445 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:6702 <-> R:172.18.36.22:6802)
2026-03-01 02:40:23.445 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:6701 <-> R:172.18.36.22:6801)
2026-03-01 02:40:23.446 [INFO] transceiver.py:125 Init transceiver 'TRX1@172.18.36.20:5700/1'
2026-03-01 02:40:23.446 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5704 <-> R:172.18.36.20:5804)
2026-03-01 02:40:23.446 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5703 <-> R:172.18.36.20:5803)
2026-03-01 02:40:23.446 [INFO] transceiver.py:125 Init transceiver 'TRX2@172.18.36.20:5700/2'
2026-03-01 02:40:23.446 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5706 <-> R:172.18.36.20:5806)
2026-03-01 02:40:23.446 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5705 <-> R:172.18.36.20:5805)
2026-03-01 02:40:23.446 [INFO] transceiver.py:125 Init transceiver 'TRX3@172.18.36.20:5700/3'
2026-03-01 02:40:23.446 [DEBUG] data_if.py:31 Init TRXD interface (L:0.0.0.0:5708 <-> R:172.18.36.20:5808)
2026-03-01 02:40:23.446 [DEBUG] ctrl_if.py:29 Init TRXC interface (L:0.0.0.0:5707 <-> R:172.18.36.20:5807)
2026-03-01 02:40:23.446 [INFO] fake_trx.py:429 Init complete
2026-03-01 02:40:23.446 [INFO] fake_trx.py:460 Setting real time process scheduler to SCHED_RR, priority 30
2026-03-01 02:40:24.003 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:24.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:24.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:24.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:24.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:24.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:28.018 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:28.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:28.020 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:28.020 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:28.020 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 0 -> 1
2026-03-01 02:40:28.028 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:40:28.029 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:40:28.029 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:28.029 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:28.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:28.030 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:40:28.031 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:28.031 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 0 -> 1
2026-03-01 02:40:28.032 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:28.035 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:40:28.035 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:40:28.035 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:28.035 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:28.035 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:28.036 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:40:28.036 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:28.036 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 0 -> 1
2026-03-01 02:40:28.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:28.039 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:40:28.040 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:40:28.040 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:28.040 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:28.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:28.041 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:40:28.041 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:28.041 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 0 -> 1
2026-03-01 02:40:28.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.043 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:40:28.043 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:40:28.043 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:40:28.044 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:28.045 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:28.048 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:40:28.526 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:40:28.573 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:28.573 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:40:28.575 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:40:28.576 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:40:28.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:28.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:28.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:28.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:28.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:28.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:28.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:28.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:28.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:28.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:28.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:28.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:28.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:28.998 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:40:29.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:29.048 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:29.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:29.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:29.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:29.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:29.202 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:29.202 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:29.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:29.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:29.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:29.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:29.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:29.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:29.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:29.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:29.247 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:29.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:29.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:29.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:29.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:29.469 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:40:29.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:29.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:29.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:29.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:29.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:29.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:29.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:29.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:29.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:29.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:29.701 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:29.701 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:29.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:29.940 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:40:29.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:29.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:29.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:29.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:30.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:30.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:30.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:30.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:30.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:30.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:30.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:30.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:30.398 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:30.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:30.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:30.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:30.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:30.400 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:30.400 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:30.400 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:30.413 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:40:30.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:30.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:30.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:30.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:30.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:30.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:30.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:30.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:30.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:30.885 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:40:30.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:30.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:30.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:30.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:30.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:30.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:30.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:30.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:30.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:31.051 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:31.051 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:31.052 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:31.052 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:31.156 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:31.157 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:31.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:31.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:31.358 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:40:31.831 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:40:31.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:31.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:31.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:31.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:31.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:31.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:31.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:31.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:31.915 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:31.915 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:31.915 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:31.915 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:31.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:32.053 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:32.053 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:32.053 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:32.053 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:32.099 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:32.099 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:40:32.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:32.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:32.304 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:40:32.776 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:40:32.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:32.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:32.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:32.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:32.920 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:32.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:32.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:32.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:32.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:32.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:32.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:32.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:32.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:32.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:33.047 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:33.047 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:40:33.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:33.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:33.250 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:40:33.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:33.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:33.460 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:33.460 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:33.460 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:33.478 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:33.478 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:33.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:33.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:33.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:33.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:33.479 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:33.479 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:33.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:33.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:33.722 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:40:33.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:33.758 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:33.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:33.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:34.194 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:40:34.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:34.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:34.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:34.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:34.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:34.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:34.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:34.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:34.505 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:34.505 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:34.505 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:34.505 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:34.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:34.667 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:40:34.700 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:34.700 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:34.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:34.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:35.140 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:40:35.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:35.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:35.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:35.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:35.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:35.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:35.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:35.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:35.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:35.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:35.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:35.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:35.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:35.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:35.613 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:40:35.648 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:35.648 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:35.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:35.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:36.084 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:40:36.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:36.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:36.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:36.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:36.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:36.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:36.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:36.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:36.430 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:36.430 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:36.430 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:36.430 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:36.464 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:36.557 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:40:36.589 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:36.589 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:40:36.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:36.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:37.030 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:40:37.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:37.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:37.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:37.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:37.379 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:37.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:37.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:37.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:37.399 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:37.399 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:37.399 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:37.399 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:37.399 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:37.406 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:37.502 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:40:37.537 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:37.538 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:40:37.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:37.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:37.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:37.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:37.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:37.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:37.920 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:37.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:37.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:37.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:37.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:37.940 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:37.940 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:37.940 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:37.940 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:37.975 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:40:37.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:38.036 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:38.036 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:38.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:38.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:38.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:38.131 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:38.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:38.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:38.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:38.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:38.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:38.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:38.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:38.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:38.244 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:38.244 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:38.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.448 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:40:38.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:38.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:38.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:38.627 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:38.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:38.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:38.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:38.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.637 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:38.637 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:38.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:38.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:38.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:38.747 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:38.747 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:38.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:38.920 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:40:39.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:39.114 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:39.115 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:39.115 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:39.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:39.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:39.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:39.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:39.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:39.133 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:39.133 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:39.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:39.218 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:39.218 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:39.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.393 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:40:39.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.601 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:39.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:39.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:39.604 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:39.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:39.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:39.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:39.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.614 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:39.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:39.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:39.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:39.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:39.688 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:39.689 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:39.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:39.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:39.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:39.784 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:39.802 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:39.802 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:39.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:39.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:39.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:39.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:39.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:39.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:39.863 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:40:39.896 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:39.897 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:39.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:39.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:40.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:40.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:40.274 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:40.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:40.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:40.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:40.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:40.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:40.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:40.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:40.335 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:40:40.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:40.400 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:40.400 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:40.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:40.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:40.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:40.768 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:40.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:40.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:40.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:40.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:40:40.777 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:40:40.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:40:40.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:40:40.808 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:40:40.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:40.871 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:40:40.871 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:40:40.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:40.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:41.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:40:41.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:41.257 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:41.257 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:41.257 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:40:41.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:41.270 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:41.270 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:41.270 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:41.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:41.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:41.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:41.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:41.273 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:41.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:41.273 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:40:41.273 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2857 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:41.273 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2857 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:41.274 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2857 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:41.274 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2857 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:41.274 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2857 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:41.274 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2857 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:46.273 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:46.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:46.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:46.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:46.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:46.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:46.281 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:46.283 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:46.283 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:46.284 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:46.284 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:40:46.287 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:40:46.287 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:40:46.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:46.288 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:46.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:46.288 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:40:46.289 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:46.289 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:40:46.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:46.290 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:40:46.290 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:40:46.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:46.291 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:46.291 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:46.291 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:40:46.291 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:46.291 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:40:46.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:46.293 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:40:46.293 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:40:46.293 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:46.293 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:46.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:46.294 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:40:46.294 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:46.294 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:40:46.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.297 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:40:46.297 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:40:46.297 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:40:46.297 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:46.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:46.302 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:40:46.780 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:40:46.823 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:40:46.825 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:40:46.828 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:40:46.830 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:46.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:46.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:46.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.874 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.878 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.881 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.883 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.890 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.941 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.943 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:46.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:47.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.245 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:40:47.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:47.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:47.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:47.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:47.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:47.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:47.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:47.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:47.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:47.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:47.710 [DEBUG] clck_gen.py:113 IND CLOCK 306
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2026-03-01 02:40:48.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.113 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.157 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.175 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:40:48.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.180 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:48.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.225 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.249 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:48.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:48.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:48.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:48.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:48.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:48.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:48.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
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2026-03-01 02:40:48.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.407 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.409 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.422 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.441 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.448 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:48.464 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:48.464 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:48.464 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:48.464 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:48.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:48.467 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:48.467 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:48.467 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:40:48.467 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:48.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:48.467 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:48.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=473 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:48.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:48.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:48.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:48.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:48.467 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:53.475 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:53.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:53.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:53.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:53.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:53.476 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:53.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:53.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:53.485 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:53.485 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:53.485 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:40:53.488 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:40:53.488 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:40:53.488 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:53.488 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:53.489 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:53.489 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:40:53.489 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:53.490 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:40:53.490 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:53.491 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:40:53.491 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:40:53.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:53.491 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:53.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:53.492 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:40:53.492 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:53.492 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:40:53.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:53.493 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:40:53.493 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:40:53.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:53.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:53.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:53.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:40:53.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:53.494 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:40:53.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:40:53.497 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:40:53.497 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:40:53.497 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:53.501 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:40:53.978 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:40:54.019 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:40:54.020 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:40:54.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:54.021 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:40:54.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:54.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:54.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:54.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:54.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:54.059 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:54.059 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:54.059 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:54.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:54.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:54.062 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:54.062 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:54.062 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:40:54.062 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:54.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:54.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:54.062 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:59.067 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:59.067 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:59.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:59.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:59.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:59.067 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:59.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:59.075 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:59.075 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:59.076 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:40:59.076 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:40:59.078 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:40:59.078 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:40:59.079 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:59.079 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:59.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:59.079 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:40:59.080 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:40:59.080 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:40:59.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:59.081 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:40:59.081 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:40:59.081 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:59.081 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:59.081 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:59.081 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:40:59.081 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:40:59.081 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:40:59.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:59.083 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:40:59.083 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:40:59.083 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:59.083 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:40:59.083 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:59.083 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:40:59.083 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:40:59.083 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:40:59.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:40:59.086 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:40:59.086 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:40:59.086 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:40:59.091 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:40:59.568 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:40:59.615 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:40:59.618 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:40:59.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:40:59.618 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:40:59.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:40:59.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:40:59.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:40:59.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:40:59.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:40:59.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:40:59.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:40:59.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:40:59.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:40:59.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:40:59.662 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:40:59.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:40:59.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:40:59.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:40:59.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:59.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:59.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:59.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:59.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:40:59.662 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:41:04.673 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:41:04.673 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:41:04.673 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:41:04.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:41:04.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:41:04.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:41:04.681 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:41:04.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:41:04.681 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:04.681 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:41:04.681 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:41:04.683 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:41:04.683 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:41:04.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:41:04.683 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:04.683 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:41:04.684 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:41:04.684 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:41:04.684 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:41:04.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:04.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:41:04.684 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:41:04.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:41:04.685 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:04.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:41:04.685 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:41:04.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:41:04.685 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:41:04.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:04.686 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:41:04.686 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:41:04.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:41:04.686 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:04.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:41:04.686 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:41:04.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:41:04.686 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:41:04.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.688 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:41:04.688 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:41:04.688 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:41:04.689 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:04.693 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:41:05.172 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:41:05.208 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:41:05.210 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:41:05.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:05.212 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:41:05.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.265 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.265 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.272 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.272 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.272 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.294 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:05.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:05.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:05.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:05.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:05.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:05.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:05.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:41:05.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:41:05.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:41:05.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:41:05.337 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:41:05.337 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:41:05.337 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:41:10.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:41:10.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:41:10.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:41:10.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:41:10.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:41:10.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:41:10.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:41:10.358 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:41:10.358 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:10.359 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:41:10.359 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:41:10.362 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:41:10.362 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:41:10.362 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:41:10.363 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:10.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:41:10.363 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:41:10.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:41:10.363 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:41:10.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:10.365 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:41:10.365 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:41:10.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:41:10.366 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:10.366 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:41:10.366 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:41:10.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:41:10.366 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:41:10.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:10.367 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:41:10.367 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:41:10.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:41:10.368 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:41:10.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:41:10.368 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:41:10.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:41:10.368 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:41:10.368 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:41:10.370 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:41:10.371 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:41:10.371 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:41:10.371 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:41:10.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:41:10.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:10.375 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:41:10.854 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:41:10.896 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:41:10.898 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:41:10.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:10.900 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:41:10.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:10.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:10.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:10.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:10.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:10.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:10.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:10.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:10.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:10.959 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:10.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:10.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:11.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:11.327 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:41:11.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:11.373 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:11.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:11.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:11.798 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:41:12.271 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:41:12.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:12.374 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:12.374 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:12.374 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:12.744 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:41:13.216 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:41:13.374 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:13.375 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:13.375 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:13.375 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:13.689 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:41:14.162 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:41:14.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:14.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:14.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:14.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:14.634 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:41:15.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:15.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:15.060 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:15.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:15.078 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:15.078 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:15.078 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:15.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:15.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:15.080 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:15.080 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:15.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:15.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:15.105 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:41:15.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:15.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:15.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:15.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:15.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:15.376 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:41:15.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:41:15.377 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:41:15.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:41:15.576 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:41:16.049 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:41:16.522 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:41:16.994 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:41:17.465 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:41:17.938 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:41:18.411 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:41:18.883 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:41:19.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:19.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:19.328 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:19.328 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:19.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:19.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:19.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:19.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:19.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:19.338 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:19.338 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:19.338 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:19.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:19.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:19.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:19.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:19.354 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:41:19.354 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:19.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:19.825 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:41:20.298 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:41:20.770 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:41:21.243 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:41:21.713 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:41:22.186 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:41:22.660 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:41:23.132 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:41:23.603 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:41:23.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:23.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:23.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:23.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:23.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:23.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:23.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:23.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:23.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:23.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:23.814 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:23.814 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:23.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:23.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:23.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:23.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:23.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:24.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:24.073 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:41:24.547 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:41:25.019 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:41:25.491 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:41:25.962 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:41:26.436 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:41:26.908 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:41:27.380 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:41:27.851 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:41:28.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:28.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:28.061 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:28.061 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:28.079 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:28.079 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:28.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:28.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:28.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:28.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:28.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:28.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:28.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:28.134 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:28.134 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:28.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:28.134 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:28.324 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:41:28.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:28.797 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:41:29.270 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:41:29.744 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:41:30.216 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:41:30.688 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:41:31.159 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:41:31.632 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:41:32.105 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:41:32.578 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:41:32.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:32.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:32.680 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:32.680 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:32.699 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:32.699 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:32.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:32.700 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:32.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:32.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:32.701 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:32.701 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:32.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:32.715 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:41:32.715 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:41:32.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:32.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:33.049 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:41:33.522 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:41:33.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:33.995 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:41:34.467 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:41:34.941 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:41:35.413 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:41:35.886 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:41:36.359 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:41:36.832 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:41:37.304 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:41:37.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:37.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:37.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:37.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:37.547 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:41:37.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:37.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:37.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:37.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:37.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:37.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:37.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:37.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:37.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:37.590 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:41:37.590 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:41:37.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:37.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:37.776 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:41:38.250 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:41:38.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:38.721 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:41:39.194 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:41:39.667 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:41:40.139 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:41:40.612 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:41:41.084 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:41:41.556 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:41:42.028 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:41:42.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:42.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:42.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:42.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:42.431 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:41:42.450 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:42.450 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:42.450 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:42.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:42.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:42.452 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:42.452 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:42.452 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:42.500 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:41:42.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:42.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:42.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:42.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:42.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:42.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:42.974 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:41:43.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:43.446 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:41:43.917 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:41:44.387 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:41:44.858 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:41:45.329 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:41:45.800 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:41:46.273 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:41:46.744 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:41:47.217 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:41:47.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:47.306 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:47.306 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:47.306 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:47.325 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:47.325 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:47.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:47.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:47.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:47.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:47.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:47.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:47.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:47.365 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:47.365 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:47.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:47.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:47.690 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:41:48.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:48.172 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:41:48.644 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:41:49.115 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:41:49.589 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:41:50.061 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:41:50.534 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:41:51.007 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:41:51.479 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:41:51.952 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:41:52.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:52.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:52.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:52.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:52.190 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:52.190 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:52.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:52.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:52.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:52.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:52.192 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:52.192 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:52.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:41:52.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:52.244 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:52.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:52.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:52.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:52.423 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:41:52.896 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:41:52.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:53.369 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:41:53.841 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:41:54.312 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:41:54.786 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:41:55.258 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:41:55.729 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:41:56.203 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:41:56.675 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:41:56.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:56.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:56.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:56.939 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:56.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:41:56.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:41:56.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:41:56.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:56.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:41:56.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:41:56.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:41:56.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:41:57.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:57.005 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:41:57.005 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:41:57.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:57.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:41:57.147 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:41:57.621 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:41:57.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:41:58.093 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 02:41:58.567 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 02:41:59.039 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 02:41:59.513 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 02:41:59.985 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 02:42:00.458 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 02:42:00.933 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 02:42:01.405 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 02:42:01.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:01.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:01.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:01.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:01.759 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:01.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:01.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:01.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:01.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:01.780 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:01.780 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:01.780 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:01.780 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:01.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:01.835 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:01.835 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:42:01.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:01.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:01.879 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 02:42:02.352 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 02:42:02.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:02.825 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 02:42:03.298 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 02:42:03.770 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 02:42:04.243 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 02:42:04.717 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 02:42:05.190 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 02:42:05.664 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 02:42:06.136 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 02:42:06.609 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 02:42:06.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:06.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:06.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:06.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:06.645 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:06.664 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:06.664 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:06.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:06.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:06.665 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:06.665 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:06.665 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:06.665 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:06.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:06.709 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:06.709 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:06.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:06.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:06.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:07.082 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 02:42:07.555 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 02:42:08.029 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 02:42:08.501 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 02:42:08.975 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 02:42:09.447 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 02:42:09.919 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 02:42:10.393 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 02:42:10.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:10.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:10.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:10.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:10.766 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:10.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:10.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:10.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:10.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:10.781 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:10.781 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:10.781 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:10.781 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:10.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:10.815 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:10.815 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:10.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:10.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:10.864 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 02:42:11.038 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:11.336 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 02:42:11.808 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 02:42:12.282 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 02:42:12.754 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 02:42:13.232 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 02:42:13.704 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 02:42:14.178 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 02:42:14.650 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 02:42:15.040 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:15.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:15.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:15.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:15.043 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:15.052 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:15.052 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:15.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:15.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:15.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:15.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:15.053 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:15.053 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:15.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:15.075 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:15.075 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:15.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:15.075 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:15.123 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 02:42:15.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:15.596 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 02:42:16.068 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 02:42:16.541 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 02:42:17.014 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 02:42:17.487 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 02:42:17.959 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 02:42:18.430 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 02:42:18.904 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 02:42:19.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:19.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:19.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:19.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:19.319 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:19.327 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:19.327 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:19.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:19.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:19.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:19.329 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:19.329 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:19.329 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:19.376 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 02:42:19.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:19.386 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:19.387 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:19.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:19.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:19.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:19.847 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 02:42:20.321 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 02:42:20.793 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 02:42:21.265 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 02:42:21.739 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 02:42:22.212 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 02:42:22.686 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 02:42:23.158 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 02:42:23.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:23.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:23.591 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:23.591 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:23.592 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:23.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:23.600 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:23.600 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:23.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:23.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:23.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:23.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:23.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:23.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:23.631 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 02:42:23.634 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:23.635 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:23.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:23.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:24.019 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:24.104 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 02:42:24.575 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 02:42:25.047 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 02:42:25.520 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 02:42:25.992 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 02:42:26.464 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 02:42:26.938 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 02:42:27.411 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 02:42:27.882 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 02:42:28.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:28.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:28.024 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:28.024 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:28.024 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:28.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:28.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:28.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:28.047 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:28.047 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:28.047 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:28.048 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:28.048 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:28.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:28.074 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:28.074 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:28.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:28.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:28.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:28.355 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 02:42:28.828 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 02:42:29.300 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 02:42:29.772 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 02:42:30.245 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 02:42:30.718 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 02:42:31.192 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 02:42:31.664 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 02:42:32.136 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 02:42:32.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:32.295 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:32.296 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:32.296 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:32.296 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:32.315 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:32.315 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:32.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:32.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:32.316 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:32.316 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:32.316 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:32.316 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:32.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:32.374 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:32.374 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:32.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:32.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:32.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:32.607 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 02:42:33.081 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 02:42:33.553 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 02:42:34.025 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 02:42:34.496 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 02:42:34.969 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 02:42:35.442 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 02:42:35.914 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 02:42:36.385 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-01 02:42:36.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:36.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:36.569 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:36.569 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:36.569 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:36.569 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=18606 tn=1 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:42:36.590 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:36.590 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:36.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:36.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:36.591 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:36.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:36.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:36.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:36.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:36.629 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:36.629 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:36.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:36.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:36.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:36.858 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-01 02:42:37.330 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-01 02:42:37.802 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-01 02:42:38.274 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-01 02:42:38.747 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-01 02:42:39.220 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-01 02:42:39.692 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-01 02:42:40.165 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-01 02:42:40.637 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-01 02:42:40.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:40.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:40.840 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:40.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:40.841 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:40.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:40.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:40.848 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:40.848 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:40.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:42:40.849 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:42:40.849 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:42:40.849 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:42:40.849 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:42:40.849 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:42:40.849 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:42:45.856 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:42:45.856 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:42:45.856 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:42:45.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:42:45.856 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:42:45.856 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:42:45.865 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:42:45.867 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:42:45.868 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:45.868 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:42:45.868 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:42:45.874 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:42:45.874 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:42:45.875 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:42:45.875 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:45.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:42:45.876 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:42:45.876 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:42:45.876 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:42:45.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:45.879 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:42:45.879 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:42:45.880 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:42:45.880 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:45.880 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:42:45.881 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:42:45.881 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:42:45.881 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:42:45.881 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:45.883 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:42:45.883 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:42:45.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:42:45.883 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:45.884 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:42:45.884 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:42:45.884 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:42:45.884 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:42:45.884 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:45.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:45.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:45.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:45.890 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:42:45.890 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:42:45.890 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:42:45.890 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:42:45.890 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:45.890 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:45.890 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:42:45.891 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:42:45.891 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:45.891 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.898 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:42:50.898 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:42:50.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:42:50.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:42:50.898 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:42:50.898 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:42:50.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:42:50.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:42:50.909 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:50.909 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:42:50.910 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:42:50.914 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:42:50.914 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:42:50.915 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:42:50.915 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:50.915 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:42:50.915 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:42:50.916 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:42:50.916 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:42:50.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:50.918 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:42:50.918 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:42:50.918 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:42:50.918 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:50.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:42:50.918 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:42:50.919 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:42:50.919 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:42:50.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:50.921 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:42:50.921 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:42:50.921 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:42:50.921 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:42:50.921 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:42:50.921 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:42:50.922 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:42:50.922 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:42:50.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:42:50.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:42:50.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:42:50.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:42:50.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:42:50.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:42:51.408 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:42:51.446 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:42:51.446 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:42:51.447 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:42:51.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:51.470 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:51.470 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:51.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:51.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:51.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:51.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:51.479 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:51.479 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:51.503 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:51.511 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:51.511 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:51.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:51.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:51.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:51.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:51.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:51.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:51.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:51.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:51.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:51.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:51.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:51.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:51.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:51.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:51.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:51.683 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:51.683 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:51.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:51.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:51.881 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:42:51.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:51.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:51.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:51.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:52.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:52.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:52.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:52.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:52.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:52.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:52.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.125 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:52.125 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:52.125 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:52.125 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:52.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:52.179 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:52.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:52.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:52.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:52.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:52.320 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=301 tn=3 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:42:52.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:52.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:52.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:52.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.340 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:52.340 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:52.340 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:52.340 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:52.351 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:42:52.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:52.392 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:52.393 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:52.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.393 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:52.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:52.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:52.822 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:42:52.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:52.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:52.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:52.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:52.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:52.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:52.828 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:52.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:52.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:52.881 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:52.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:52.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:52.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:52.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:52.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:53.294 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:42:53.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:53.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:53.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:53.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:53.347 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:53.348 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:53.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:53.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:53.350 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:53.350 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:53.350 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:53.350 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:53.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:53.401 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:53.401 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:42:53.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:53.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:53.766 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:42:53.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:53.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:53.871 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:53.871 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:53.871 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:53.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:53.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:53.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:53.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:53.890 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:53.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:53.890 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:53.890 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:53.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:53.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:53.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:53.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:53.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:53.936 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:53.937 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:42:53.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:53.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:54.239 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:42:54.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:54.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:54.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:54.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:54.416 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:54.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:54.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:54.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:54.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:54.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:54.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:54.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:54.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:54.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:54.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:54.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:54.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:54.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:54.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:54.712 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:42:54.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:54.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:54.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:54.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:54.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:54.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:54.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:54.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:54.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:54.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:54.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:54.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:54.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:54.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:54.976 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:54.976 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:55.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:55.028 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:55.028 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:55.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:55.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:55.184 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:42:55.494 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:55.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:55.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:55.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:55.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:55.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:55.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:55.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:55.514 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:55.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:55.514 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:55.514 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:55.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:42:55.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:55.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:55.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:55.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:55.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:55.657 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:42:55.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:42:55.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:42:55.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:42:55.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:42:56.130 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:42:56.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:56.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:56.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:56.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:56.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:56.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:56.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:56.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:56.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:56.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:56.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:56.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:56.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:56.475 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:56.475 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:42:56.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:56.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:56.603 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:42:56.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:56.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:56.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:56.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:56.883 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:56.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:56.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:56.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:56.903 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:56.903 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:56.903 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:56.903 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:56.903 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:56.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:56.938 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:56.938 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:42:56.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:56.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.075 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:42:57.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:57.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:57.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:57.428 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:57.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:57.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:57.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:57.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:57.445 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:57.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:57.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:57.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:57.503 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:57.503 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:57.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.504 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.547 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:42:57.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:57.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:57.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:57.706 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:57.723 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:57.723 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:57.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:57.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.726 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:57.726 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:57.726 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:57.726 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:57.772 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:57.779 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:57.779 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:57.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:57.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.018 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:42:58.192 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:58.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.195 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:58.195 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:58.195 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:58.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:58.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:58.204 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:58.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:58.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:58.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:58.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:58.253 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:58.255 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:58.255 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:58.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.491 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:42:58.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:58.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:58.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:58.685 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:58.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:58.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:58.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:58.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.696 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:58.696 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:58.696 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:58.696 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:58.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:58.747 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:58.747 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:58.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:58.962 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:42:59.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:59.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:59.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:59.173 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:59.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:59.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:59.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:59.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:59.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:59.191 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:59.191 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:59.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:59.243 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:59.243 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:59.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:59.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:59.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:59.353 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:59.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:59.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:59.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:59.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:59.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:59.373 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:59.373 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:59.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:59.424 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:59.424 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:59.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.434 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:42:59.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:59.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.849 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:59.849 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:59.849 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:42:59.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:42:59.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:42:59.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:42:59.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.867 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:42:59.867 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:42:59.867 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:42:59.867 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:42:59.906 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:42:59.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:42:59.915 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:42:59.915 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:42:59.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:42:59.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:00.333 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:00.336 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:00.336 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:00.336 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:00.337 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:00.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:00.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:00.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:00.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:00.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:00.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:00.348 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:00.348 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:00.377 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:43:00.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:00.399 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:00.400 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:00.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:00.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:00.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:00.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:00.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:00.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:00.826 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:00.832 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:00.832 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:00.832 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:00.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:00.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:43:00.832 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:43:00.832 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:43:00.832 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:43:00.832 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:43:00.833 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:43:00.833 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:43:00.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2141 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:00.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2141 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:00.833 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2141 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:05.838 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:43:05.838 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:43:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:43:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:43:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:43:05.838 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:43:05.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:43:05.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:43:05.847 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:05.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:43:05.847 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:43:05.849 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:43:05.850 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:43:05.850 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:43:05.850 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:05.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:43:05.850 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:43:05.850 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:43:05.850 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:43:05.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:05.852 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:43:05.852 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:43:05.852 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:43:05.852 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:05.853 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:43:05.853 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:43:05.853 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:43:05.853 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:43:05.853 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:05.854 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:43:05.855 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:43:05.855 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:43:05.855 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:05.855 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:43:05.855 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:43:05.855 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:43:05.855 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:43:05.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:05.857 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:43:05.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:43:05.857 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:43:05.857 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:43:05.857 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:43:05.857 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:43:05.858 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:43:05.858 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:43:05.858 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.858 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.859 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:05.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.859 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:05.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:05.862 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:43:06.339 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:43:06.383 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:43:06.385 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:43:06.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:06.388 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:43:06.410 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:06.410 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:06.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:06.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:06.418 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:06.418 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:06.418 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:06.418 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:06.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:06.442 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:06.443 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:06.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:06.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:06.812 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:43:06.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:06.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:06.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:06.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:07.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:07.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:07.283 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:43:07.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:07.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:07.487 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:07.487 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:07.497 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:07.497 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:07.497 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:07.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:07.499 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:07.499 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:07.499 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:07.499 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:07.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:07.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:07.555 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:07.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:07.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:07.755 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:43:07.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:07.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:07.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:07.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:08.228 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:43:08.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:08.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:08.700 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:43:08.863 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:08.863 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:08.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:08.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:08.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:08.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:08.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:08.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:08.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:08.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:08.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:08.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:08.944 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:08.944 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:08.944 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:08.944 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:08.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:08.997 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:08.997 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:08.997 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:08.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:09.171 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:43:09.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:09.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:09.644 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:43:09.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:09.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:09.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:09.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:10.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:10.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:10.081 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:10.081 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:10.092 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:10.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:10.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:10.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:10.094 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:10.094 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:10.094 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:10.094 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:10.116 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:43:10.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:10.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:10.144 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:10.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:10.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:10.588 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:43:10.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:10.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:10.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:10.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:11.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:11.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:11.062 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:43:11.514 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:11.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:11.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:11.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:11.534 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:43:11.536 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:11.536 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:11.536 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:11.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:11.538 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:11.538 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:11.538 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:11.538 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:11.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:11.589 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:11.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:11.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:11.591 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:12.006 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:43:12.477 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:43:12.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:12.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:12.951 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:43:13.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:13.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:13.077 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:13.077 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:13.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:13.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:13.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:13.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:13.099 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:13.099 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:13.099 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:13.099 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:13.140 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:13.148 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:13.148 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:43:13.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:13.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:13.424 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:43:13.897 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:43:14.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:14.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:14.370 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:43:14.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:14.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:14.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:14.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:14.589 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:14.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:14.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:14.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:14.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:14.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:14.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:14.611 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:14.611 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:14.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:14.660 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:14.661 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:43:14.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:14.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:14.842 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:43:15.315 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:43:15.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:15.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:15.788 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:43:16.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:16.094 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:16.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:16.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:16.095 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:16.113 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:16.113 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:16.114 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:16.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:16.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:16.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:16.116 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:16.116 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:16.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:16.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:16.170 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:16.170 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:16.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:16.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:16.260 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:43:16.732 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:43:17.112 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:17.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:17.205 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:43:17.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:17.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:17.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:17.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:17.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:17.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:17.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:17.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:17.608 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:17.608 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:17.608 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:17.608 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:17.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:17.660 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:17.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:17.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:17.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:17.677 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:43:18.149 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:43:18.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:18.620 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:43:18.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:19.091 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:43:19.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:19.100 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:19.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:19.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:19.119 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:19.119 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:19.120 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:19.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:19.122 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:19.122 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:19.122 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:19.122 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:19.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:19.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:19.173 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:19.173 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:19.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:19.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:19.562 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:43:20.035 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:43:20.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:20.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:20.508 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:43:20.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:20.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:20.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:20.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:20.980 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:43:20.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:20.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:20.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:20.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:20.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:20.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:20.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:20.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:21.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:21.039 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:21.039 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:43:21.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:21.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:21.453 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:43:21.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:21.927 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:43:21.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:22.400 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:43:22.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:22.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:22.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:22.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:22.415 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:22.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:22.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:22.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:22.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:22.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:22.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:22.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:22.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:22.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:22.487 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:22.488 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:43:22.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:22.488 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:22.873 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:43:23.345 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:43:23.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:23.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:23.817 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:43:23.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:23.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:23.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:23.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:23.920 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:23.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:23.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:23.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:23.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:23.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:23.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:23.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:23.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:23.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:23.992 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:23.992 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:23.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:23.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:24.288 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:43:24.760 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:43:24.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:24.919 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:25.234 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:43:25.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:25.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:25.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:25.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:25.413 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:25.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:25.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:25.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:25.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:25.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:25.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:25.424 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:25.424 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:25.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:25.479 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:25.480 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:25.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:25.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:25.706 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:43:26.179 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:43:26.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:26.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:26.652 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:43:26.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:26.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:26.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:26.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:26.829 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:26.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:26.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:26.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:26.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:26.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:26.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:26.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:26.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:26.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:26.891 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:26.891 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:26.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:26.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:27.123 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:43:27.595 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:43:27.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:27.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:28.069 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:43:28.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:28.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:28.264 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:28.264 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:28.264 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:28.274 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:28.274 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:28.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:28.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:28.276 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:28.276 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:28.276 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:28.276 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:28.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:28.325 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:28.325 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:28.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:28.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:28.540 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:43:29.012 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:43:29.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:29.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:29.486 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:43:29.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:29.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:29.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:29.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:29.695 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:29.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:29.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:29.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:29.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:29.707 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:29.707 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:29.707 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:29.707 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:29.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:29.759 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:29.759 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:29.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:29.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:29.957 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:43:30.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:30.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:30.429 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:43:30.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:30.822 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:30.822 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:30.822 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:30.822 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:30.822 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=5391 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:30.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:30.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:30.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:30.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:30.844 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:30.844 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:30.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:30.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:30.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:30.902 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:43:30.910 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:30.910 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:30.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:30.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:31.375 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:43:31.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:31.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:31.848 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:43:32.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:32.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:32.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:32.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:32.259 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:32.268 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:32.268 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:32.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:32.270 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:32.270 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:32.270 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:32.270 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:32.270 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:32.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:32.321 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:43:32.325 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:32.325 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:32.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:32.326 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:32.793 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:43:33.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:33.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:33.265 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:43:33.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:33.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:33.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:33.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:33.694 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:33.695 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6011 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:33.714 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:33.714 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:33.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:33.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:33.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:33.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:33.717 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:33.717 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:33.739 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:43:33.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:33.769 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:43:33.769 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:43:33.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:33.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:34.211 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:43:34.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:34.662 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:34.684 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:43:35.130 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:35.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:35.133 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:35.133 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:35.133 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:43:35.139 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:35.139 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:35.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:35.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:35.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:43:35.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:43:35.140 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:43:35.140 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:43:35.140 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:43:35.140 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:43:35.140 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:43:35.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:35.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:35.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:35.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:35.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:35.140 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:43:40.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:43:40.148 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:43:40.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:43:40.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:43:40.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:43:40.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:43:40.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:43:40.156 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:43:40.156 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:40.157 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:43:40.157 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:43:40.159 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:43:40.160 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:43:40.160 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:43:40.160 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:40.160 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:43:40.161 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:43:40.161 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:43:40.161 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:43:40.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:40.162 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:43:40.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:43:40.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:43:40.162 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:40.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:43:40.163 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:43:40.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:43:40.163 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:43:40.163 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:40.164 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:43:40.165 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:43:40.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:43:40.165 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:43:40.165 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:43:40.165 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:43:40.165 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:43:40.165 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:43:40.165 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:40.167 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:43:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:43:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:43:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:43:40.167 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:43:40.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:43:40.167 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:43:40.168 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:43:40.168 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:43:40.168 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:43:40.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:43:40.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.169 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:43:40.172 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:43:40.651 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:43:40.689 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:43:40.691 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:43:40.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:40.693 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:43:40.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:40.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:40.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:40.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:40.721 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:40.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:40.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:40.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:40.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:40.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:40.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:40.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:40.754 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:41.123 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:43:41.169 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:41.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:41.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:41.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:41.594 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:43:42.067 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:43:42.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:42.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:42.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:42.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:42.540 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:43:43.012 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:43:43.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:43.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:43.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:43.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:43.485 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:43:43.958 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:43:44.172 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:44.172 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:44.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:44.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:44.430 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:43:44.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:44.633 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:44.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:44.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:44.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:44.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:44.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:44.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:44.655 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:44.655 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:44.655 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:44.655 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:44.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:44.703 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:44.703 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:44.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:44.704 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:44.903 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:43:45.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:43:45.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:43:45.174 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:43:45.174 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:43:45.375 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:43:45.847 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:43:46.318 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:43:46.792 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:43:47.264 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:43:47.737 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:43:48.210 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:43:48.683 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:43:48.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:48.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:48.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:48.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:48.925 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:48.925 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:48.925 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:48.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:48.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:48.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:48.928 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:48.928 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:48.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:48.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:48.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:48.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:48.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:49.155 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:43:49.626 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:43:50.097 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:43:50.567 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:43:51.041 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:43:51.513 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:43:51.986 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:43:52.459 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:43:52.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:52.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:52.896 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:52.896 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:52.913 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:52.913 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:52.913 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:52.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:52.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:52.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:52.916 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:52.916 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:52.931 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:43:52.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:52.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:52.969 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:52.969 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:52.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:53.403 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:43:53.874 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:43:54.348 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:43:54.820 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:43:55.292 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:43:55.763 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:43:56.237 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:43:56.709 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:43:57.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:57.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:57.168 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:57.168 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:57.181 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:43:57.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:43:57.186 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:43:57.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:43:57.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:57.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:57.188 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:57.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:43:57.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:43:57.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:43:57.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:43:57.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:43:57.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:57.240 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:43:57.653 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:43:58.126 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:43:58.599 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:43:59.071 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:43:59.545 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:44:00.018 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:44:00.490 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:44:00.964 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:44:01.436 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:44:01.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:01.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:01.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:01.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:01.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:01.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:01.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:01.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:01.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:01.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:01.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:01.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:01.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:01.909 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:44:01.915 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:01.915 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:44:01.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:01.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:02.380 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:44:02.854 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:44:03.327 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:44:03.800 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:44:04.273 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:44:04.745 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:44:05.219 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:44:05.692 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:44:06.166 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:44:06.244 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:06.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:06.246 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:06.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:06.247 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:06.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:06.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:06.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:06.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:06.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:06.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:06.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:06.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:06.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:06.314 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:06.314 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:44:06.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:06.315 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:06.638 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:44:07.111 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:44:07.584 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:44:08.057 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:44:08.529 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:44:09.002 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:44:09.475 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:44:09.948 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:44:10.421 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:44:10.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:10.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:10.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:10.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:10.644 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:10.644 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6578 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:44:10.662 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:10.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:10.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:10.664 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:10.664 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:10.664 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:10.664 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:10.664 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:10.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:44:10.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:10.716 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:10.716 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:10.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:10.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:10.893 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:44:11.364 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:44:11.838 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:44:12.310 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:44:12.782 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:44:13.253 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:44:13.724 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:44:14.194 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:44:14.665 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:44:15.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:15.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:15.030 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:15.030 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:15.049 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:15.049 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:15.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:15.052 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:15.052 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:15.052 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:15.052 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:15.052 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:15.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:15.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:15.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:15.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:15.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:15.136 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:44:15.607 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:44:16.077 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:44:16.548 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:44:17.019 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:44:17.490 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:44:17.961 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:44:18.434 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:44:18.907 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:44:19.379 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:44:19.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:19.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:19.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:19.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:19.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:19.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:19.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:19.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:19.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:19.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:19.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:19.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:19.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:44:19.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:19.489 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:19.489 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:19.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:19.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:19.850 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:44:20.323 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:44:20.796 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:44:21.269 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:44:21.739 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:44:22.210 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:44:22.684 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:44:23.156 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:44:23.628 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:44:23.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:23.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:23.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:23.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:23.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:23.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:23.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:23.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:23.698 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:23.698 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:23.698 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:23.698 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:23.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:23.748 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:23.748 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:44:23.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:23.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:24.101 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:44:24.574 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:44:25.046 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:44:25.520 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:44:25.993 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:44:26.465 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:44:26.939 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:44:27.411 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:44:27.883 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 02:44:28.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:28.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:28.028 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:28.028 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:28.028 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:28.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:28.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:28.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:28.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:28.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:28.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:28.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:28.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:28.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:28.095 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:28.095 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:44:28.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:28.096 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:28.356 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 02:44:28.830 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 02:44:29.303 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 02:44:29.777 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 02:44:30.249 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 02:44:30.723 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 02:44:31.196 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 02:44:31.669 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 02:44:32.151 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 02:44:32.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:32.440 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:32.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:32.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:32.440 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:32.458 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:32.458 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:32.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:32.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:32.461 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:32.461 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:32.461 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:32.461 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:32.504 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:32.513 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:32.513 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:44:32.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:32.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:32.624 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 02:44:33.097 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 02:44:33.570 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 02:44:34.042 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 02:44:34.515 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 02:44:34.988 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 02:44:35.461 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 02:44:35.934 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 02:44:36.406 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 02:44:36.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:36.564 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:36.565 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:36.565 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:36.565 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:36.584 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:36.584 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:36.584 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:36.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:36.587 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:36.587 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:36.587 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:36.587 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:36.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:36.652 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:36.652 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:44:36.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:36.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:36.878 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 02:44:37.349 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 02:44:37.823 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 02:44:38.295 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 02:44:38.766 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 02:44:39.239 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 02:44:39.712 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 02:44:40.184 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 02:44:40.655 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 02:44:40.828 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:40.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:40.831 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:40.831 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:40.831 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:40.850 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:40.850 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:40.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:40.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:40.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:40.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:40.853 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:40.853 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:40.920 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:40.927 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:40.927 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:44:40.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:40.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:41.128 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 02:44:41.601 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 02:44:42.074 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 02:44:42.547 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 02:44:43.020 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 02:44:43.492 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 02:44:43.965 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 02:44:44.438 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 02:44:44.910 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 02:44:45.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:45.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:45.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:45.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:45.105 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:45.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:45.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:45.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:45.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:45.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:45.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:45.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:45.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:45.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:45.176 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:45.176 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:44:45.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:45.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:45.383 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 02:44:45.856 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 02:44:46.328 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 02:44:46.800 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 02:44:47.274 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 02:44:47.746 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 02:44:48.217 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 02:44:48.691 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 02:44:49.163 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 02:44:49.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:49.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:49.376 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:49.376 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:49.377 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:49.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:49.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:49.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:49.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:49.398 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:49.398 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:49.398 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:49.398 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:49.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:49.447 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:49.447 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:44:49.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:49.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:49.636 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 02:44:50.108 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 02:44:50.581 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 02:44:51.054 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 02:44:51.527 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 02:44:51.999 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 02:44:52.471 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 02:44:52.944 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 02:44:53.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:53.338 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:53.338 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:53.338 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:53.338 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:53.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:53.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:53.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:53.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:53.359 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:53.359 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:53.359 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:53.359 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:53.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:53.411 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:53.411 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:44:53.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:53.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:53.416 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 02:44:53.889 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 02:44:54.362 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 02:44:54.835 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 02:44:55.308 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 02:44:55.780 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 02:44:56.253 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 02:44:56.726 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 02:44:57.199 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 02:44:57.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:57.612 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:57.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:57.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:57.612 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:44:57.627 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:44:57.627 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:44:57.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:44:57.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:57.630 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:44:57.630 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:44:57.630 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:44:57.630 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:44:57.670 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 02:44:57.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:44:57.679 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:44:57.680 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:44:57.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:57.680 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:44:58.142 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 02:44:58.615 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 02:44:59.088 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 02:44:59.560 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 02:45:00.033 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 02:45:00.506 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 02:45:00.978 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 02:45:01.451 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 02:45:01.876 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:01.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:01.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:01.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:01.899 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:45:01.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:01.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:01.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:01.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:01.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:01.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:01.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:01.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:01.923 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 02:45:01.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:01.972 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:45:01.972 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:45:01.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:01.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:02.395 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 02:45:02.867 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 02:45:03.340 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 02:45:03.812 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 02:45:04.285 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 02:45:04.758 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 02:45:05.230 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 02:45:05.703 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 02:45:06.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:06.151 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:06.152 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:06.152 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:06.152 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:45:06.165 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:06.165 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:06.166 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:06.166 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:06.168 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:45:06.168 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:45:06.168 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:45:06.168 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:45:06.168 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:45:06.168 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:45:06.168 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:45:06.168 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:45:06.168 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:45:06.168 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:45:06.168 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:45:06.168 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:45:06.168 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=18565 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:45:11.172 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:45:11.172 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:45:11.172 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:45:11.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:45:11.172 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:45:11.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:45:11.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:45:11.186 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:45:11.186 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:11.186 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:45:11.186 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:45:11.188 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:45:11.188 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:45:11.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:45:11.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:11.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:45:11.189 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:45:11.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:45:11.189 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:45:11.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:11.190 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:45:11.191 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:45:11.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:45:11.191 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:11.191 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:45:11.191 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:45:11.191 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:45:11.191 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:45:11.191 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:11.192 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:45:11.192 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:45:11.192 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:45:11.192 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:11.192 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:45:11.193 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:45:11.193 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:45:11.193 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:45:11.193 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:11.194 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:45:11.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:45:11.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:45:11.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:45:11.194 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:45:11.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:45:11.195 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:45:11.195 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:45:11.195 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:11.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:11.196 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:45:11.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:45:11.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:45:11.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:45:11.196 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:45:11.196 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:45:11.196 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:45:16.203 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:45:16.203 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:45:16.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:45:16.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:45:16.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:45:16.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:45:16.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:45:16.213 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:45:16.213 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:16.213 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:45:16.214 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:45:16.218 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:45:16.219 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:45:16.219 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:45:16.219 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:16.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:45:16.220 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:45:16.221 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:45:16.221 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:45:16.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:16.223 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:45:16.223 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:45:16.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:45:16.224 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:16.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:45:16.224 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:45:16.224 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:45:16.224 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:45:16.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:16.226 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:45:16.226 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:45:16.226 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:45:16.227 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:45:16.227 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:45:16.227 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:45:16.227 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:45:16.227 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:45:16.227 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:16.230 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:45:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:45:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:45:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:45:16.230 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:45:16.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:45:16.231 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:45:16.231 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:45:16.231 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:16.236 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:45:16.714 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:45:16.755 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:45:16.756 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:45:16.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:16.757 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:45:16.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:16.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:16.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:16.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:16.783 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:16.784 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:16.784 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:16.784 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:16.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:16.818 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:16.818 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:16.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:16.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:17.182 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:45:17.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:17.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:17.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:17.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:17.655 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:45:18.128 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:45:18.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:18.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:18.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:18.236 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:18.599 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:45:19.071 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:45:19.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:19.236 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:19.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:19.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:19.544 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:45:20.016 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:45:20.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:20.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:20.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:20.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:20.488 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:45:20.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:20.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:20.856 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:20.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:20.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:20.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:20.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:20.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:20.874 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:20.874 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:20.874 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:20.874 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:20.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:20.923 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:20.923 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:20.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:20.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:20.959 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:45:21.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:45:21.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:45:21.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:45:21.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:45:21.430 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:45:21.903 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:45:22.376 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:45:22.848 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:45:23.319 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:45:23.792 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:45:24.265 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:45:24.737 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:45:25.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:25.122 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:25.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:25.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:25.140 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:25.140 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:25.140 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:25.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:25.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:25.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:25.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:25.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:25.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:25.191 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:25.191 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:25.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:25.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:25.208 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:45:25.679 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:45:26.149 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:45:26.622 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:45:27.087 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:45:27.560 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:45:28.032 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:45:28.504 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:45:28.975 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:45:29.449 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:45:29.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:29.588 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:29.588 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:29.588 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:29.607 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:29.607 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:29.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:29.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:29.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:29.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:29.609 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:29.609 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:29.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:29.661 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:29.661 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:29.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:29.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:29.921 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:45:30.393 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:45:30.867 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:45:31.339 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:45:31.811 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:45:32.282 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:45:32.756 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:45:33.228 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:45:33.700 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:45:33.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:33.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:33.851 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:33.851 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:33.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:33.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:33.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:33.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:33.869 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:33.869 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:33.870 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:33.870 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:33.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:33.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:33.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:33.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:33.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:34.171 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:45:34.642 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:45:35.113 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:45:35.584 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:45:36.057 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:45:36.530 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:45:37.003 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:45:37.476 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:45:37.948 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:45:38.421 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:45:38.471 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:38.474 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:38.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:38.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:38.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:38.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:38.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:38.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:38.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:38.494 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:38.494 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:38.494 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:38.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:38.543 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:45:38.543 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:45:38.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:38.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:38.892 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:45:39.365 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:45:39.838 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:45:40.311 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:45:40.784 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:45:41.257 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:45:41.729 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:45:42.203 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:45:42.675 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:45:43.149 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:45:43.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:43.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:43.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:43.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:43.353 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:45:43.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:43.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:43.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:43.372 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:43.372 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:43.372 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:43.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:43.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:43.416 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:43.425 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:45:43.425 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:45:43.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:43.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:43.621 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:45:44.093 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:45:44.566 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:45:45.039 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:45:45.511 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:45:45.984 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:45:46.457 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:45:46.929 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:45:47.402 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:45:47.875 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:45:48.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:48.235 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:48.236 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:48.236 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:48.236 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:45:48.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:48.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:48.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:48.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:48.256 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:48.256 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:48.256 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:48.256 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:48.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:48.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:48.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:48.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:48.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:48.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:48.347 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:45:48.818 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:45:49.289 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:45:49.760 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:45:50.231 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:45:50.701 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:45:51.175 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:45:51.648 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:45:52.120 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:45:52.593 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:45:53.066 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:45:53.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:53.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:53.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:53.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:53.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:53.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:53.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:53.127 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:53.127 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:53.127 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:53.127 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:53.127 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:53.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:53.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:53.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:53.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:53.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:53.538 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:45:54.009 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:45:54.483 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:45:54.953 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:45:55.423 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:45:55.897 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:45:56.369 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:45:56.839 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:45:57.310 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:45:57.784 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:45:57.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:57.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:57.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:57.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:57.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:45:57.986 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:45:57.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:45:57.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:57.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:57.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:57.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:45:57.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:45:58.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:45:58.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:45:58.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:45:58.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:45:58.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:58.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:45:58.256 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:45:58.729 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:45:59.202 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:45:59.675 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:46:00.147 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:46:00.621 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:46:01.093 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:46:01.566 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:46:02.039 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:46:02.512 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:46:02.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:02.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:02.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:02.738 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:02.755 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:02.755 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:02.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:02.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:02.757 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:02.757 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:02.757 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:02.757 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:02.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:02.811 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:02.811 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:46:02.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:02.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:02.984 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:46:03.457 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:46:03.930 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 02:46:04.403 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 02:46:04.876 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 02:46:05.349 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 02:46:05.820 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 02:46:06.293 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 02:46:06.767 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 02:46:07.240 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 02:46:07.553 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:07.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:07.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:07.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:07.556 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:07.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:07.574 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:07.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:07.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:07.576 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:07.576 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:07.576 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:07.576 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:07.624 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:07.631 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:07.631 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:46:07.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:07.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:07.713 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 02:46:08.186 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 02:46:08.658 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 02:46:09.131 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 02:46:09.604 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 02:46:10.076 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 02:46:10.549 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 02:46:11.023 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 02:46:11.496 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 02:46:11.970 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 02:46:12.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:12.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:12.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:12.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:12.436 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:12.443 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 02:46:12.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:12.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:12.456 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:12.458 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:12.458 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:12.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:12.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:12.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:12.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:12.507 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:12.508 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:12.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:12.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:12.916 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 02:46:13.388 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 02:46:13.859 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 02:46:14.332 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 02:46:14.806 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 02:46:15.278 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 02:46:15.751 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 02:46:16.223 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 02:46:16.544 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:16.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:16.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:16.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:16.547 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:16.566 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:16.566 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:16.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:16.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:16.568 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:16.568 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:16.568 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:16.568 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:16.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:16.620 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:16.620 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:16.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:16.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:16.695 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 02:46:17.167 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 02:46:17.641 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 02:46:18.113 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 02:46:18.586 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 02:46:19.058 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 02:46:19.531 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 02:46:20.004 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 02:46:20.476 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 02:46:20.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:20.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:20.819 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:20.819 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:20.819 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:20.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:20.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:20.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:20.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:20.840 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:20.840 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:20.841 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:20.841 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:20.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:20.894 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:20.894 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:20.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:20.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:20.948 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 02:46:21.421 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 02:46:21.894 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 02:46:22.367 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 02:46:22.840 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 02:46:23.312 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 02:46:23.784 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 02:46:24.257 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 02:46:24.730 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 02:46:25.087 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:25.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:25.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:25.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:25.091 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:25.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:25.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:25.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:25.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:25.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:25.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:25.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:25.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:25.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:25.164 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:25.164 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:25.164 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:25.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:25.201 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 02:46:25.673 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 02:46:26.146 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 02:46:26.619 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 02:46:27.091 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 02:46:27.565 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 02:46:28.038 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 02:46:28.511 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 02:46:28.984 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 02:46:29.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:29.358 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:29.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:29.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:29.359 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:29.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:29.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:29.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:29.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:29.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:29.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:29.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:29.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:29.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:29.427 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:29.427 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:29.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:29.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:29.456 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 02:46:29.928 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 02:46:30.401 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 02:46:30.874 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 02:46:31.347 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 02:46:31.820 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 02:46:32.293 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 02:46:32.766 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 02:46:33.238 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 02:46:33.712 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 02:46:33.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:33.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:33.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:33.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:33.797 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:33.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:33.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:33.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:33.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:33.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:33.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:33.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:33.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:33.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:33.867 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:33.867 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:33.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:33.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:34.184 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 02:46:34.656 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 02:46:35.130 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 02:46:35.602 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 02:46:36.074 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 02:46:36.547 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 02:46:37.020 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 02:46:37.492 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 02:46:37.966 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 02:46:38.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:38.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:38.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:38.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:38.069 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:38.087 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:38.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:38.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:38.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:38.090 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:38.090 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:38.090 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:38.090 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:38.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:38.143 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:38.143 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:38.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:38.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:38.438 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 02:46:38.911 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 02:46:39.385 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 02:46:39.857 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 02:46:40.330 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 02:46:40.803 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 02:46:41.275 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 02:46:41.746 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 02:46:42.219 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-01 02:46:42.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:42.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:42.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:42.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:42.342 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:42.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:42.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:42.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:42.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:42.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:42.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:42.363 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:42.363 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:42.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:42.411 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:46:42.411 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:46:42.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:42.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:42.691 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-01 02:46:43.164 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-01 02:46:43.638 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-01 02:46:44.109 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-01 02:46:44.583 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-01 02:46:45.056 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-01 02:46:45.528 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-01 02:46:46.001 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-01 02:46:46.473 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-01 02:46:46.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:46.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:46.613 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:46.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:46.613 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:46:46.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:46:46.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:46:46.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:46:46.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:46:46.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:46:46.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:46:46.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:46:46.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:46:46.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:46:46.623 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:46:46.623 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:46:51.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:46:51.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:46:51.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:46:51.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:46:51.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:46:51.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:46:51.639 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:46:51.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:46:51.641 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:51.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:46:51.642 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:46:51.646 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:46:51.646 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:46:51.647 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:46:51.647 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:51.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:46:51.648 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:46:51.648 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:46:51.648 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:46:51.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:46:51.650 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:46:51.651 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:46:51.651 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:46:51.651 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:51.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:46:51.652 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:46:51.653 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:46:51.653 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:46:51.653 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:46:51.654 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:46:51.654 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:46:51.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:46:51.655 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:51.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:46:51.655 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:46:51.655 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:46:51.655 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:46:51.655 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:51.659 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:46:51.659 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:46:51.659 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:46:51.660 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:46:51.660 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:51.660 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:51.660 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:46:51.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:46:51.661 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:51.661 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.668 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:46:56.668 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:46:56.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:46:56.668 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:46:56.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:46:56.668 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:46:56.676 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:46:56.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:46:56.677 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:56.677 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:46:56.677 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:46:56.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:46:56.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:46:56.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:46:56.681 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:56.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:46:56.682 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:46:56.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:46:56.683 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:46:56.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:46:56.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:46:56.685 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:46:56.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:46:56.685 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:56.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:46:56.685 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:46:56.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:46:56.685 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:46:56.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:46:56.688 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:46:56.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:46:56.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:46:56.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:46:56.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:46:56.688 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:46:56.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:46:56.688 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:46:56.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:46:56.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:46:56.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:46:56.692 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:46:56.692 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:46:56.697 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:46:57.174 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:46:57.218 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:46:57.219 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:46:57.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:57.220 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:46:57.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:57.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:57.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:57.242 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:57.243 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:57.243 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:57.243 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:57.243 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:57.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:57.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:57.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:57.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:57.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:57.645 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:46:57.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:46:57.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:46:57.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:46:57.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:46:58.117 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:46:58.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:58.322 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:58.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:58.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:58.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:58.331 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:58.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:58.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:58.332 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:58.332 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:58.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:58.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:58.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:58.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:58.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:58.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:58.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:58.590 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:46:58.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:46:58.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:46:58.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:46:58.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:46:59.063 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:46:59.536 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:46:59.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:46:59.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:46:59.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:46:59.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:46:59.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:59.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:59.761 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:59.761 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:59.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:46:59.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:46:59.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:46:59.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:59.772 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:59.772 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:59.772 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:46:59.772 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:46:59.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:46:59.827 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:46:59.827 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:46:59.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:46:59.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:00.008 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:47:00.479 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:47:00.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:00.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:00.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:00.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:00.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:00.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:00.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:00.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:00.935 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:00.935 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:00.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:00.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:00.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:00.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:00.938 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:00.938 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:00.949 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:47:00.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:00.987 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:00.987 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:00.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:00.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:01.420 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:47:01.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:01.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:01.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:01.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:01.894 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:47:02.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:02.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:02.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:02.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:02.366 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:47:02.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:02.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:02.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:02.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:02.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:02.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:02.370 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:02.370 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:02.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:02.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:02.423 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:02.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:02.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:02.838 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:47:03.309 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:47:03.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:03.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:03.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:03.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:03.445 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:03.445 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:03.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:03.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:03.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:03.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:03.448 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:03.448 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:03.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:03.502 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:03.502 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:47:03.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:03.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:03.782 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:47:04.255 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:47:04.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:04.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:04.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:04.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:04.456 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:04.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:04.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:04.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:04.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:04.476 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:04.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:04.476 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:04.476 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:04.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:04.529 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:04.529 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:47:04.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:04.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:04.727 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:47:05.200 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:47:05.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:05.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:05.476 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:05.476 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:05.476 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:05.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:05.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:05.494 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:05.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:05.496 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:05.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:05.497 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:05.497 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:05.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:05.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:05.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:05.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:05.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:05.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:05.673 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:47:06.145 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:47:06.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:06.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:06.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:06.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:06.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:06.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:06.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:06.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:06.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:06.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:06.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:06.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:06.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:06.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:06.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:06.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:06.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:06.616 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:47:07.087 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:47:07.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:07.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:07.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:07.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:07.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:07.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:07.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:07.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:07.540 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:07.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:07.541 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:07.541 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:07.559 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:47:07.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:07.589 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:07.597 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:07.597 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:07.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:07.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:08.031 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:47:08.503 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:47:08.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:08.907 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:08.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:08.907 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:08.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:08.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:08.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:08.926 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:08.926 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:08.926 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:08.926 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:08.926 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:08.975 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:47:08.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:08.982 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:08.983 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:47:08.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:08.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:09.448 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:47:09.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:09.868 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:09.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:09.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:09.868 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:09.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:09.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:09.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:09.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:09.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:09.890 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:09.890 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:09.890 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:09.921 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:47:09.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:09.940 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:09.940 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:47:09.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:09.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:10.394 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:47:10.867 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:47:10.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:10.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:10.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:10.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:10.899 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:10.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:10.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:10.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:10.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:10.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:10.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:10.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:10.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:10.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:10.972 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:10.972 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:10.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:10.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:11.340 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:47:11.813 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:47:11.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:11.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:11.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:11.969 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:11.969 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:11.978 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:11.978 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:11.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:11.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:11.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:11.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:11.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:11.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:12.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:12.035 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:12.035 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:12.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:12.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:12.285 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:47:12.757 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:47:13.231 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:47:13.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:13.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:13.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:13.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:13.405 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:13.422 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:13.422 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:13.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:13.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:13.425 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:13.425 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:13.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:13.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:13.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:13.475 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:13.475 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:13.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:13.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:13.702 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:47:14.175 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:47:14.649 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:47:14.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:14.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:14.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:14.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:14.845 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:14.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:14.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:14.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:14.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:14.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:14.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:14.865 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:14.865 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:14.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:14.915 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:14.915 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:14.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:14.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:15.121 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:47:15.593 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:47:16.066 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:47:16.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:16.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:16.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:16.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:16.281 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:16.290 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:16.290 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:16.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:16.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:16.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:16.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:16.292 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:16.292 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:16.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:16.344 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:16.344 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:16.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:16.345 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:16.538 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:47:17.010 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:47:17.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:17.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:17.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:17.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:17.403 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:17.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:17.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:17.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:17.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:17.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:17.414 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:17.414 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:17.414 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:17.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:17.465 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:17.465 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:17.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:17.466 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:17.483 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:47:17.955 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:47:18.427 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:47:18.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:18.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:18.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:18.840 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:18.840 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:18.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:18.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:18.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:18.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:18.861 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:18.861 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:18.861 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:18.861 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:18.900 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:47:18.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:18.911 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:18.911 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:18.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:18.911 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:19.373 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:47:19.845 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:47:20.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:20.274 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:20.275 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:20.275 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:20.275 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:20.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:20.294 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:20.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:20.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:20.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:20.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:20.296 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:20.297 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:20.318 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:47:20.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:20.347 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:20.347 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:20.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:20.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:20.791 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:47:21.263 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:47:21.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:21.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:21.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:21.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:21.712 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:21.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:21.717 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:21.717 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:21.717 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:21.718 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:47:21.718 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:47:21.718 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:47:21.718 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:47:21.718 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:47:21.718 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:47:21.718 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:47:26.724 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:47:26.724 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:47:26.725 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:47:26.725 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:47:26.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:47:26.725 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:47:26.732 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:47:26.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:47:26.734 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:47:26.734 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:47:26.734 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:47:26.737 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:47:26.737 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:47:26.738 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:47:26.738 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:47:26.738 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:47:26.738 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:47:26.739 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:47:26.739 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:47:26.739 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:26.740 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:47:26.740 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:47:26.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:47:26.740 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:47:26.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:47:26.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:47:26.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:47:26.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:47:26.741 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:26.742 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:47:26.742 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:47:26.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:47:26.743 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:47:26.743 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:47:26.743 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:47:26.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:47:26.743 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:47:26.743 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:26.745 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:47:26.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:47:26.745 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:47:26.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:47:26.745 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:47:26.745 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:47:26.746 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:47:26.746 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:47:26.746 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:47:26.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:47:26.751 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:47:27.229 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:47:27.267 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:47:27.268 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:47:27.270 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:47:27.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:27.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:27.287 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:27.287 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:27.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:27.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:27.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:27.292 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:27.292 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:27.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:27.330 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:27.330 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:27.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:27.331 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:27.702 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:47:27.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:27.748 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:27.749 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:27.749 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:28.175 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:47:28.648 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:47:28.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:28.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:28.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:28.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:29.121 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:47:29.594 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:47:29.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:29.751 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:29.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:29.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:30.066 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:47:30.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:30.539 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:47:30.751 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:30.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:30.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:30.752 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:31.010 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:47:31.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:31.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:31.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:31.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:31.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:31.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:31.085 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:31.085 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:31.085 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:31.085 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:31.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:31.103 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:31.103 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:31.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:31.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:31.483 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:47:31.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:31.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:31.753 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:31.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:31.956 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:47:32.428 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:47:32.902 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:47:33.374 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:47:33.847 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:47:34.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:34.320 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:47:34.793 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:47:34.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:34.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:34.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:34.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:34.959 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:34.959 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:34.959 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:34.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:34.961 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:34.961 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:34.961 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:34.961 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:35.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:35.009 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:35.010 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:47:35.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:35.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:35.266 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:47:35.740 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:47:36.213 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:47:36.687 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:47:37.160 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:47:37.634 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:47:38.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:38.106 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:47:38.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:38.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:38.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:38.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:38.560 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:38.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:38.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:38.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:38.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:38.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:38.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:38.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:38.579 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:38.579 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:47:38.579 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:38.579 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:47:38.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:39.052 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:47:39.524 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:47:39.998 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:47:40.471 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:47:40.943 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:47:41.417 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:47:41.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:41.889 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:47:42.361 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:47:42.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:42.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:42.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:42.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:42.418 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:42.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:42.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:42.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:42.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:42.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:42.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:42.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:42.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:42.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:42.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:42.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:42.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:42.832 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:47:43.305 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:47:43.778 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:47:44.250 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:47:44.721 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:47:45.194 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:47:45.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:45.667 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:47:46.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:46.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:46.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:46.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:46.107 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=4177 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:47:46.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:46.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:46.108 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:46.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:46.108 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:46.108 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:46.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:46.139 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:47:46.140 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:46.140 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:46.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:46.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:46.610 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:47:47.083 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:47:47.556 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:47:48.028 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:47:48.499 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:47:48.969 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:47:49.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:49.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:49.408 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:49.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:49.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:49.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:49.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:49.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:49.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:49.429 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:49.429 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:49.429 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:49.429 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:49.442 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:47:49.472 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:49.476 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:49.476 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:49.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:49.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:49.915 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:47:50.387 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:47:50.861 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:47:51.333 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:47:51.805 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:47:52.279 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:47:52.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:52.751 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:47:53.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:53.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:53.147 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:53.147 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:53.147 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:53.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:47:53.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:53.147 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:47:53.147 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:47:53.147 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:47:53.148 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:47:53.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:47:53.169 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:47:53.169 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:47:53.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:53.169 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:53.223 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:47:53.695 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:47:54.168 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:47:54.641 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:47:55.114 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:47:55.587 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:47:56.059 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:47:56.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:56.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:47:56.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:47:56.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:47:56.453 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:47:56.453 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:47:56.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:47:56.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:47:56.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:47:56.466 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:47:56.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:47:56.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:47:56.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:47:56.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:47:56.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:47:56.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:47:56.468 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:48:01.474 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:48:01.474 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:48:01.474 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:48:01.475 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:48:01.475 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:48:01.475 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:48:01.482 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:48:01.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:48:01.483 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:01.483 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:48:01.483 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:48:01.486 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:48:01.486 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:48:01.486 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:48:01.486 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:01.486 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:48:01.486 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:48:01.487 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:48:01.487 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:48:01.487 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:01.489 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:48:01.489 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:48:01.489 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:48:01.489 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:01.489 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:48:01.489 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:48:01.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:48:01.490 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:48:01.490 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:01.492 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:48:01.492 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:48:01.492 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:48:01.492 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:01.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:48:01.492 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:48:01.492 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:48:01.492 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:48:01.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.496 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:48:01.496 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:48:01.496 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:48:01.496 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:01.497 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:01.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:01.501 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:48:01.980 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:48:02.023 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:48:02.024 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:48:02.026 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:48:02.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:02.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:02.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:02.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:02.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:02.053 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:02.053 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:02.054 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:02.054 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:02.075 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:02.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:02.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:02.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:02.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:02.452 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:48:02.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:02.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:02.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:02.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:02.923 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:48:03.397 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:48:03.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:03.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:03.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:03.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:03.869 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:48:04.342 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:48:04.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:04.502 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:04.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:04.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:04.815 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:48:05.085 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:05.288 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:48:05.503 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:05.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:05.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:05.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:05.760 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:48:05.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:05.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:05.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:05.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:05.835 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=936 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:05.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:05.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:05.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:05.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:05.835 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:05.835 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:05.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:05.853 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:05.853 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:05.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:05.854 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:06.234 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:48:06.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:06.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:06.505 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:06.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:06.707 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:48:07.179 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:48:07.650 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:48:08.123 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:48:08.596 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:48:08.856 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:09.068 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:48:09.542 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:48:09.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:09.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:09.686 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:09.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:09.687 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=1768 tn=2 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:09.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:09.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:09.687 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:09.687 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:09.688 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:09.688 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:09.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:09.724 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:09.724 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:09.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:09.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:10.015 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:48:10.487 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:48:10.958 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:48:11.431 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:48:11.903 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:48:12.376 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:48:12.726 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:12.849 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:48:13.322 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:48:13.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:13.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:13.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:13.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:13.544 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=2600 tn=4 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:13.544 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=2600 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:13.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:13.544 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=2600 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:13.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:13.545 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:13.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:13.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:13.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:13.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:13.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:13.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:13.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:13.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:13.793 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:48:14.024 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:14.267 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:48:14.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:14.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:14.504 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:14.504 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:14.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:14.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:14.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:14.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:14.524 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:14.524 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:14.524 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:14.524 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:14.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:14.573 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:14.573 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:48:14.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:14.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:14.739 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:48:15.211 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:48:15.685 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:48:16.157 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:48:16.629 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:48:17.103 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:48:17.576 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:48:17.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:18.048 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:48:18.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:18.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:18.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:18.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:18.124 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:18.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:18.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:18.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:18.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:18.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:18.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:18.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:18.142 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:18.143 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:48:18.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:18.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:18.522 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:48:18.994 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:48:19.467 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:48:19.942 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:48:20.415 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:48:20.888 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:48:21.153 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:21.361 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:48:21.831 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:48:21.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:21.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:21.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:21.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:21.980 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:21.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:21.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:21.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:21.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:21.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:21.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:22.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:22.017 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:22.017 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:48:22.017 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:22.018 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:22.304 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:48:22.777 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:48:23.249 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:48:23.722 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:48:24.194 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:48:24.667 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:48:25.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:25.140 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:48:25.613 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:48:25.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:25.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:25.836 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:25.836 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:25.836 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:25.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:25.837 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:25.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:25.839 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:25.839 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:25.839 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:25.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:25.850 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:25.850 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:48:25.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:25.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:26.085 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:48:26.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:26.558 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:48:26.793 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:26.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:26.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:26.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:26.797 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:26.817 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:26.817 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:26.817 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:26.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:26.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:26.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:26.820 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:26.820 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:26.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:26.868 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:26.868 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:26.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:26.869 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:27.030 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:48:27.502 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:48:27.974 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:48:28.447 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:48:28.919 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:48:29.391 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:48:29.862 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:48:30.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:30.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:30.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:30.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:30.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:30.301 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6217 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:30.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:30.302 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:30.302 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:30.302 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:30.302 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:30.302 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:30.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:30.334 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:30.334 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:30.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:30.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:30.336 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:48:30.809 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:48:31.281 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:48:31.754 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:48:32.227 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:48:32.699 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:48:33.170 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:48:33.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:33.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:33.608 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:33.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:33.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:33.609 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6931 tn=5 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:33.609 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=6931 tn=6 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:48:33.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:33.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:33.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:33.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:33.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:33.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:33.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:33.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:33.641 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:48:33.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:33.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:33.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:34.114 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:48:34.586 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:48:35.059 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:48:35.529 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:48:36.003 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:48:36.475 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:48:36.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:36.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:36.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:36.916 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:36.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:36.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:36.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:36.917 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:36.917 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:36.917 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:36.918 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:36.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:36.947 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:48:36.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:36.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:36.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:36.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:37.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:37.418 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:48:37.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:37.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:37.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:37.857 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:37.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:37.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:37.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:37.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:37.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:37.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:37.877 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:37.877 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:37.889 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:48:37.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:37.928 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:37.928 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:48:37.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:37.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:38.360 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:48:38.833 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:48:39.305 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:48:39.777 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:48:40.248 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:48:40.722 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:48:41.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:41.194 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:48:41.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:41.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:41.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:41.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:41.589 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:41.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:41.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:41.590 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:41.590 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:41.590 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:41.590 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:41.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:41.616 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:41.616 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:48:41.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:41.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:41.666 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:48:42.139 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:48:42.611 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:48:43.083 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:48:43.555 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:48:44.029 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:48:44.501 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:48:44.640 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:44.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:44.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:44.894 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:44.894 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:44.894 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:44.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:44.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:44.895 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:44.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:44.895 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:44.895 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:44.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:44.921 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:44.921 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:48:44.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:44.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:44.974 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:48:45.447 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:48:45.919 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:48:46.392 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:48:46.865 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:48:47.337 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:48:47.811 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:48:47.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:48.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:48.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:48.201 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:48.201 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:48.202 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:48.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:48.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:48.202 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:48.202 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:48.202 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:48.203 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:48.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:48:48.229 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:48:48.229 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:48:48.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:48.229 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:48.283 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:48:48.755 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:48:48.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:49.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:49.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:49.149 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:49.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:49.149 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:48:49.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:49.161 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:49.161 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:49.161 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:49.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:48:49.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:48:49.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:48:49.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:48:49.163 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:48:49.163 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:48:49.164 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:48:54.168 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:48:54.168 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:48:54.169 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:48:54.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:48:54.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:48:54.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:48:54.175 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:48:54.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:48:54.177 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:54.177 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:48:54.177 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:48:54.182 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:48:54.182 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:48:54.182 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:48:54.183 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:54.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:48:54.183 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:48:54.184 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:48:54.184 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:48:54.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:54.186 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:48:54.186 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:48:54.186 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:48:54.186 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:54.187 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:48:54.187 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:48:54.187 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:48:54.187 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:48:54.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:54.189 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:48:54.189 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:48:54.189 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:48:54.189 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:48:54.189 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:48:54.189 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:48:54.190 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:48:54.190 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:48:54.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.193 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:48:54.194 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:48:54.194 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:48:54.194 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:48:54.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:48:54.199 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:48:54.676 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:48:54.718 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:48:54.720 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:48:54.721 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:48:54.721 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:48:54.726 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:48:54.726 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:48:54.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:48:54.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:48:54.728 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:48:54.728 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:48:54.729 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:48:54.729 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:48:55.148 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:48:55.196 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:55.196 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:55.196 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:55.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:55.618 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:48:56.090 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:48:56.197 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:56.197 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:56.197 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:56.198 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:56.560 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:48:57.031 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:48:57.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:57.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:57.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:57.199 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:57.502 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:48:57.973 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:48:58.199 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:58.199 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:58.199 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:58.200 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:58.444 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:48:58.914 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:48:59.200 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:48:59.200 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:48:59.201 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:48:59.201 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:48:59.385 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:48:59.858 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:49:00.328 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:49:00.797 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:49:01.267 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:49:01.739 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:49:02.210 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:49:02.680 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:49:03.151 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:49:03.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:03.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:03.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:03.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:03.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:03.513 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:03.515 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:03.515 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:03.515 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:03.515 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:49:03.515 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:03.515 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:03.515 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:03.515 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:03.515 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:03.515 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:03.515 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:03.515 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:03.515 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2019 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:08.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:08.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:08.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:08.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:08.520 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:08.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:08.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:08.532 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:08.533 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:08.533 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:08.533 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:49:08.538 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:49:08.539 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:49:08.539 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:08.539 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:08.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:08.540 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:49:08.541 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:08.541 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:49:08.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:08.544 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:49:08.544 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:49:08.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:08.545 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:08.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:08.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:49:08.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:08.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:49:08.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:08.548 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:49:08.548 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:49:08.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:08.549 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:08.549 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:08.549 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:49:08.549 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:08.549 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:49:08.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:08.553 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:49:08.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:49:08.553 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:49:08.553 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:49:08.553 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:49:08.553 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:49:08.554 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:49:08.554 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:49:08.554 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.554 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.555 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:08.559 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:49:09.037 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:49:09.086 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:09.088 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:49:09.088 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:09.089 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:49:09.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:09.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:09.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:09.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:09.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:09.093 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:09.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:09.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:49:09.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:09.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:09.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:09.558 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:09.970 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:49:10.441 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:49:10.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:10.558 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:10.559 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:10.559 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:10.909 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:49:11.378 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:49:11.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:11.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:11.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:11.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:11.849 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:49:12.320 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:49:12.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:12.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:12.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:12.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:12.791 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:49:13.262 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:49:13.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:13.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:13.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:13.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:13.732 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:49:14.203 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:49:14.674 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:49:15.145 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:49:15.615 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:49:16.086 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:49:16.557 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:49:17.027 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:49:17.498 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:49:17.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:17.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:17.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:17.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:17.872 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:17.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:17.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:17.877 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:17.877 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:17.877 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:17.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:17.877 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:17.878 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:49:17.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2022 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:17.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2022 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:17.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2022 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:17.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2022 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:17.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2022 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:17.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2022 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:17.879 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2022 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:49:22.880 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:22.880 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:22.880 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:22.880 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:22.880 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:22.880 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:22.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:22.890 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:22.890 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:22.891 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:22.891 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:49:22.896 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:49:22.897 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:49:22.897 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:22.897 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:22.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:22.898 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:49:22.898 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:22.898 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:49:22.899 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:22.903 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:49:22.903 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:49:22.903 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:22.903 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:22.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:22.903 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:49:22.904 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:22.904 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:49:22.904 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:22.908 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:49:22.909 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:49:22.909 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:22.909 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:22.909 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:22.910 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:49:22.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:22.910 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:49:22.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.913 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:49:22.913 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:49:22.913 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:49:22.913 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:22.918 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:49:23.396 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:49:23.441 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:23.443 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:49:23.445 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:49:23.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:23.446 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:23.446 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:23.446 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:23.868 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:49:23.917 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:23.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:23.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:23.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:24.344 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:49:24.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:24.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:24.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:24.450 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:24.450 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:24.816 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:49:24.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:24.918 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:25.287 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:49:25.758 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:49:25.918 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:25.919 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:25.919 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:25.919 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:26.228 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:49:26.699 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:49:26.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:26.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:26.920 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:26.920 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:27.170 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:49:27.641 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:49:27.922 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:27.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:27.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:27.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:28.111 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:49:28.582 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:49:29.053 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:49:29.523 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:49:29.993 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:49:30.461 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:49:30.932 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:49:31.402 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:49:31.873 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:49:32.344 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:49:32.815 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:49:33.285 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:49:33.756 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:49:34.230 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:49:34.702 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:49:35.174 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:49:35.647 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:49:36.119 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:49:36.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:36.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:36.241 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:36.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:36.241 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:36.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:36.242 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:36.242 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:36.242 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:36.242 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:36.242 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:36.242 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:36.242 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:49:41.248 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:41.248 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:41.248 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:41.248 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:41.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:41.248 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:41.262 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:41.264 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:41.264 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:41.265 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:41.265 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:49:41.270 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:49:41.271 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:49:41.271 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:41.271 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:41.272 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:41.272 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:49:41.273 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:41.273 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:49:41.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:41.276 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:49:41.277 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:49:41.277 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:41.277 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:41.278 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:41.278 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:49:41.278 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:41.279 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:49:41.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:41.280 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:49:41.281 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:49:41.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:41.281 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:41.281 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:41.281 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:49:41.281 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:41.281 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:49:41.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:41.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:49:41.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:49:41.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:49:41.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:49:41.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:49:41.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:49:41.286 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:49:41.286 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:49:41.286 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:41.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:41.291 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:49:41.769 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:49:41.818 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:41.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:41.822 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:49:41.824 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:49:41.827 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:41.827 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:41.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:41.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:41.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:41.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:41.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:41.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:42.240 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:49:42.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:42.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:42.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:42.289 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:42.712 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:49:42.859 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:43.183 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:49:43.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:43.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:43.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:43.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:43.384 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:43.657 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:49:43.905 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:44.129 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:49:44.291 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:44.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:44.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:44.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:44.600 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:49:45.071 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:49:45.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:45.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:45.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:45.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:45.544 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:49:45.920 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:46.017 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:49:46.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:46.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:46.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:46.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:46.454 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:46.489 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:49:46.963 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:49:46.971 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:47.435 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:49:47.494 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:47.907 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:49:48.378 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:49:48.851 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:49:49.324 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:49:49.500 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:49.796 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:49:50.267 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:49:50.740 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:49:51.212 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:49:51.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:51.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:51.549 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:51.550 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:51.550 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:51.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:56.557 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:49:56.557 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:49:56.557 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:56.557 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:56.557 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:56.557 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:56.564 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:49:56.564 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:56.564 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:56.565 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:49:56.565 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:49:56.568 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:49:56.569 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:49:56.569 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:56.569 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:56.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:49:56.570 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:49:56.571 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:49:56.571 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:49:56.571 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:56.573 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:49:56.573 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:49:56.573 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:56.573 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:56.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:49:56.574 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:49:56.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:49:56.574 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:49:56.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:56.576 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:49:56.576 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:49:56.576 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:56.576 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:49:56.577 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:49:56.577 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:49:56.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:49:56.577 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:49:56.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:56.580 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:49:56.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:49:56.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:49:56.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:49:56.580 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:49:56.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:49:56.581 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:49:56.581 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:49:56.581 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:56.586 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:49:57.064 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:49:57.107 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:49:57.109 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:49:57.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.112 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:49:57.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:57.137 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:57.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:57.142 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.142 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.142 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.143 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:57.143 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:57.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:57.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.234 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.234 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:57.234 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:57.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:57.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:57.253 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:57.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.254 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:57.254 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:57.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:57.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.488 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:57.488 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:57.496 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:57.496 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:57.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:57.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.498 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.498 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:57.498 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:57.535 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:49:57.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:57.541 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.541 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:57.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:57.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:57.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:57.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:57.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:57.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:57.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:57.766 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:57.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.768 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.768 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.768 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:57.768 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:57.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:57.820 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:57.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:57.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.821 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:57.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:57.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.007 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:49:58.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.020 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.020 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.020 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.020 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.062 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.062 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.086 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.086 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.086 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.086 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.097 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.098 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:58.098 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:49:58.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.103 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:58.115 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.149 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:58.149 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:49:58.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.163 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:58.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.181 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.181 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.181 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.181 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:58.209 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.213 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.213 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.239 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.239 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.239 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.292 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.292 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.292 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.300 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.308 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.323 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.324 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.325 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.325 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:49:58.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.347 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.347 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.347 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.347 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.347 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.389 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:58.389 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:49:58.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.404 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.404 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.404 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:58.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.417 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.419 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.419 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.420 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.420 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.425 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:58.426 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:49:58.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.427 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.429 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:58.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.473 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:49:58.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.482 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:58.482 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:49:58.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.534 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.538 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.538 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.538 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:58.556 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.556 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.557 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:58.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:58.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:58.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:58.611 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.615 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:58.615 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:49:58.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.616 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:58.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.792 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:58.798 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:58.798 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:58.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:58.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.800 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:58.800 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:58.800 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:58.800 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:58.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:58.849 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:58.850 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:49:58.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.850 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:58.941 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:49:59.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.052 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.055 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:59.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:59.074 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.074 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:59.075 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:59.075 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:59.075 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:59.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:59.132 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:59.132 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:49:59.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.133 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.302 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.302 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.302 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:59.310 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.310 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.310 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:59.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:59.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:59.311 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:59.311 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:59.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:59.368 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:59.368 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:49:59.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.369 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.413 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:49:59.546 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.553 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.554 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.554 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.554 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:59.570 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.570 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.571 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:59.572 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.572 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:59.572 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:59.572 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:59.572 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:59.585 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:49:59.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:49:59.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:49:59.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:49:59.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:59.597 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:59.597 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:49:59.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.597 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:49:59.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.807 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:49:59.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:49:59.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:49:59.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:49:59.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.817 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:49:59.817 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:49:59.817 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:49:59.817 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:49:59.829 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:49:59.832 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:49:59.832 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:49:59.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.832 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:49:59.885 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:50:00.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:00.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:00.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:00.071 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:50:00.071 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:50:00.071 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:50:00.090 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:50:00.090 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:50:00.090 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:50:00.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:00.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:50:00.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:50:00.092 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:50:00.092 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:50:00.120 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:50:00.124 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:50:00.124 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:50:00.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:00.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:00.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:00.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:00.316 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:00.317 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:50:00.317 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:50:00.317 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:50:00.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:00.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:00.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:00.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:00.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:00.325 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:00.325 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:00.325 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:00.325 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:50:00.325 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:00.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:05.332 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:05.332 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:05.332 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:05.332 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:05.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:05.332 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:05.339 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:05.339 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:05.340 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:05.340 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:05.340 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:50:05.344 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:50:05.344 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:50:05.344 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:05.344 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:05.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:05.345 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:50:05.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:05.345 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:50:05.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:05.349 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:50:05.349 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:50:05.349 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:05.349 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:05.350 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:05.350 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:50:05.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:05.350 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:50:05.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:05.354 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:50:05.354 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:50:05.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:05.354 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:05.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:05.354 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:50:05.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:05.354 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:50:05.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:05.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:50:05.360 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:50:05.360 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:50:05.360 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:05.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:50:05.842 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:50:05.887 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:50:05.890 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:50:05.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:05.893 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:50:05.914 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:50:05.914 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:50:05.914 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:50:05.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:05.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:50:05.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:50:05.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:50:05.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:50:05.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 02:50:05.943 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:50:05.943 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:50:05.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:05.943 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:06.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:06.312 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:50:06.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:06.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:06.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:06.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:06.785 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:50:07.257 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:50:07.364 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:07.364 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:07.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:07.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:07.731 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:50:08.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:50:08.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:50:08.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:08.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:08.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:08.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:08.008 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:08.008 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:08.008 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:08.008 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:08.008 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:08.008 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:08.008 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:50:08.009 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=573 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:08.009 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=573 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:08.009 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=573 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:08.009 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=573 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:08.009 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=573 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:08.009 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=573 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:13.014 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:13.014 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:13.014 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:13.014 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:13.014 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:13.014 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:13.021 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:13.023 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:13.023 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:13.023 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:13.024 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:50:13.027 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:50:13.028 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:50:13.028 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:13.029 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:13.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:13.030 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:50:13.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:13.030 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:50:13.031 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:13.033 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:50:13.033 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:50:13.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:13.033 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:13.033 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:13.033 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:50:13.033 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:13.033 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:50:13.034 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:13.036 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:50:13.037 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:50:13.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:13.037 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:13.037 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:13.037 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:50:13.037 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:13.037 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:50:13.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:13.041 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:50:13.041 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:50:13.042 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:50:13.042 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:50:13.042 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:13.042 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:13.042 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:13.043 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:13.043 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:13.043 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.051 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:18.051 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:18.051 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:18.051 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:18.051 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:18.051 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:18.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:18.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:18.060 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:18.060 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:18.060 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:50:18.062 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:50:18.062 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:50:18.063 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:18.063 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:18.063 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:18.063 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:50:18.064 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:18.064 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:50:18.064 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:18.065 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:50:18.065 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:50:18.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:18.065 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:18.065 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:18.065 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:50:18.065 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:18.065 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:50:18.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:18.067 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:50:18.067 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:50:18.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:18.067 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:18.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:18.067 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:50:18.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:18.067 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:50:18.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:50:18.070 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:50:18.070 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:50:18.070 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:50:18.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:18.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:18.075 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:50:18.553 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:50:18.593 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:50:18.593 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:50:18.593 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:50:18.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:19.025 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:50:19.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:19.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:19.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:19.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:19.500 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:50:19.972 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:50:20.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:20.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:20.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:20.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:20.447 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:50:20.919 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:50:21.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:21.076 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:21.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:21.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:21.394 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:50:21.866 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:50:22.077 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:22.078 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:22.078 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:22.078 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:22.341 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:50:22.813 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:50:23.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:23.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:23.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:23.079 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:23.289 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:50:23.761 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:50:24.092 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:24.092 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:24.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:24.092 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:24.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:24.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:24.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:24.095 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:50:24.095 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:24.095 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:24.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:24.095 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1298 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:24.095 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1298 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:24.095 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1298 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:24.095 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1298 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:24.095 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1298 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:24.095 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1298 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:29.098 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:29.098 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:29.098 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:29.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:29.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:29.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:29.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:29.108 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:29.108 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:29.109 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:29.109 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:50:29.112 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:50:29.112 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:50:29.112 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:29.113 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:29.113 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:29.113 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:50:29.114 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:29.114 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:50:29.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:29.115 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:50:29.115 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:50:29.115 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:29.115 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:29.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:29.116 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:50:29.116 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:29.116 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:50:29.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:29.117 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:50:29.118 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:50:29.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:29.118 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:29.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:29.118 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:50:29.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:29.118 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:50:29.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:29.120 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:50:29.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:50:29.121 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:50:29.121 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:50:29.121 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:29.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:29.126 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:50:29.602 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:50:29.646 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:50:29.648 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:50:29.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:29.651 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:50:30.074 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:50:30.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:30.124 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:30.124 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:30.124 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:30.549 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:50:31.021 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:50:31.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:31.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:31.126 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:31.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:31.495 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:50:31.967 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:50:32.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:32.127 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:32.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:32.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:32.439 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:50:32.913 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:50:33.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:33.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:33.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:33.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:33.385 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:50:33.857 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:50:34.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:34.130 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:34.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:34.130 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:34.333 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:50:34.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:34.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:34.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:34.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:34.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:34.666 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:34.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:34.666 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:34.666 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:34.666 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:34.666 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:50:34.666 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1196 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:34.666 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1196 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:34.666 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1196 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:34.666 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1196 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:34.666 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1196 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:34.666 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1196 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:50:39.669 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:39.669 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:39.669 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:39.669 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:39.669 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:39.669 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:39.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:39.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:39.675 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:39.676 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:39.676 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:50:39.678 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:50:39.679 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:50:39.679 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:39.679 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:39.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:39.679 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:50:39.679 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:39.679 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:50:39.680 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:39.681 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:50:39.682 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:50:39.682 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:39.682 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:39.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:39.682 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:50:39.682 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:39.682 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:50:39.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:39.684 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:50:39.684 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:50:39.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:39.684 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:39.684 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:39.684 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:50:39.684 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:39.684 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:50:39.684 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:39.687 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:50:39.688 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:50:39.688 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:50:39.688 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:50:39.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:39.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:39.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:39.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:39.688 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:39.688 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:39.688 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:39.689 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:39.689 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:39.689 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:50:39.689 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:39.689 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:39.689 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:50:44.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:50:44.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:44.697 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:44.697 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:44.697 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:44.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:50:44.705 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:44.705 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:44.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:50:44.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:50:44.708 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:50:44.708 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:50:44.709 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:44.709 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:44.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:50:44.709 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:50:44.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:50:44.710 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:50:44.710 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:44.711 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:50:44.711 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:50:44.711 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:44.711 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:44.711 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:50:44.711 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:50:44.711 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:50:44.711 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:50:44.711 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:44.713 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:50:44.713 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:50:44.713 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:44.713 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:50:44.713 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:50:44.713 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:50:44.713 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:50:44.713 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:50:44.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:44.715 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:50:44.716 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:50:44.716 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:50:44.716 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:50:44.721 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:50:45.199 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:50:45.238 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:50:45.240 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:50:45.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:50:45.243 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:50:45.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:50:45.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:50:45.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:50:45.671 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:50:45.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:45.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:45.719 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:45.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:46.145 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:50:46.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:50:46.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:50:46.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:50:46.248 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:50:46.248 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:50:46.617 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:50:46.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:46.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:46.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:46.720 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:47.089 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:50:47.560 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:50:47.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:47.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:47.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:47.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:48.030 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:50:48.500 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:50:48.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:48.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:48.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:48.722 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:48.967 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:50:49.438 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:50:49.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:50:49.723 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:50:49.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:50:49.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:50:49.909 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:50:50.377 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:50:50.846 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:50:51.317 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:50:51.788 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:50:52.259 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:50:52.729 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:50:53.200 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:50:53.670 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:50:54.141 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:50:54.612 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:50:55.083 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:50:55.554 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:50:56.028 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:50:56.500 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:50:56.972 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:50:57.443 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:50:57.916 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:50:58.388 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:50:58.860 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:50:59.331 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:50:59.805 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:50:59.997 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:50:59.997 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:00.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:00.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:00.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:00.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:00.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:00.007 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:00.007 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:00.007 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:00.007 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:00.007 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:00.007 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:51:05.012 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:05.013 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:05.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:05.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:05.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:05.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:05.037 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:05.039 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:05.039 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:05.040 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:05.040 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:51:05.047 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:51:05.047 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:51:05.048 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:05.048 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:05.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:05.049 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:51:05.050 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:05.050 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:51:05.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:05.053 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:51:05.053 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:51:05.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:05.054 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:05.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:05.055 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:51:05.055 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:05.056 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:51:05.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:05.058 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:51:05.058 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:51:05.058 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:05.058 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:05.058 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:05.058 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:51:05.059 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:05.059 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:51:05.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:05.062 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:51:05.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:51:05.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:51:05.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:51:05.062 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:51:05.063 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:51:05.063 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:51:05.063 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:51:05.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:05.064 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:05.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:05.068 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:51:05.544 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:51:05.581 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:05.582 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:05.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:05.583 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:51:05.601 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:05.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:05.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:51:05.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:05.604 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:05.604 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:05.604 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:51:05.604 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:51:05.637 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:05.641 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:05.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:05.649 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:05.649 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:05.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:05.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:06.015 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:51:06.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:06.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:06.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:06.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:06.488 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:51:06.960 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:51:07.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:07.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:07.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:07.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:07.434 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:51:07.906 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:51:08.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:08.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:08.069 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:08.069 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:08.379 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:51:08.852 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:51:09.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:09.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:09.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:09.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:09.325 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:51:09.797 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:51:10.069 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:10.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:10.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:10.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:10.268 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:51:10.741 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:51:11.214 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:51:11.686 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:51:12.160 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:51:12.633 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:51:13.105 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:51:13.579 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:51:13.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:13.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:13.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:13.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:13.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:13.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:13.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:13.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:13.664 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:13.664 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:13.664 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:13.664 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:13.664 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:13.664 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:13.664 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:51:18.671 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:18.671 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:18.671 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:18.671 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:18.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:18.671 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:18.678 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:18.679 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:18.679 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:18.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:18.680 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:51:18.683 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:51:18.683 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:51:18.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:18.683 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:18.684 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:18.684 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:51:18.684 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:18.684 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:51:18.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:18.686 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:51:18.686 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:51:18.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:18.686 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:18.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:18.686 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:51:18.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:18.686 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:51:18.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:18.688 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:51:18.688 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:51:18.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:18.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:18.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:18.689 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:51:18.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:18.689 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:51:18.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:51:18.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:51:18.692 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:51:18.692 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:18.696 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:51:19.175 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:51:19.216 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:19.218 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:19.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:19.220 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:51:19.247 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:19.247 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:19.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:51:19.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:19.254 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:19.254 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:19.254 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:51:19.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:51:19.267 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:19.271 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:19.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:19.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:19.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:19.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:19.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:19.648 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:51:19.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:19.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:19.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:19.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:20.121 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:51:20.594 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:51:20.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:20.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:20.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:20.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:21.066 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:51:21.537 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:51:21.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:21.697 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:21.697 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:21.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:22.008 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:51:22.482 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:51:22.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:22.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:22.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:22.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:22.954 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:51:23.427 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:51:23.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:23.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:23.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:23.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:23.900 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:51:24.373 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:51:24.845 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:51:25.316 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:51:25.789 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:51:26.262 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:51:26.735 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:51:27.208 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:51:27.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:27.285 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:27.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:27.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:27.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:27.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:27.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:27.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:27.295 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:27.295 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:27.295 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:27.295 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:27.295 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:27.295 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:27.295 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:51:32.302 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:32.302 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:32.302 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:32.302 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:32.302 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:32.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:32.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:32.316 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:32.316 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:32.316 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:32.316 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:51:32.318 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:51:32.318 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:51:32.318 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:32.318 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:32.319 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:32.319 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:51:32.319 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:32.319 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:51:32.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:32.320 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:51:32.320 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:51:32.320 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:32.320 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:32.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:32.320 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:51:32.320 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:32.320 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:51:32.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:32.321 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:51:32.321 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:51:32.321 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:32.321 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:32.321 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:32.322 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:51:32.322 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:32.322 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:51:32.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:32.323 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:51:32.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:51:32.323 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:51:32.323 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:51:32.323 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:51:32.323 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:51:32.324 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:51:32.324 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:51:32.324 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:32.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:32.328 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:51:32.806 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:51:32.844 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:32.846 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:32.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:32.848 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:51:32.872 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:32.872 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:32.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:51:32.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:32.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:32.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:32.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:51:32.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:51:32.899 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:32.902 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:32.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:32.915 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:51:32.915 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:51:32.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:32.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:33.278 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:51:33.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:33.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:33.327 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:33.327 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:33.471 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:33.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:33.472 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:51:33.477 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:33.477 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:33.478 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:33.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:33.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:33.482 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:33.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:33.482 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:33.482 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:33.482 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:33.482 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:51:33.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=250 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:33.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=250 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:33.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=250 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:33.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=250 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:33.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=250 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:33.483 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=250 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:38.484 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:38.484 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:38.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:38.484 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:38.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:38.484 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:38.492 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:38.492 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:38.493 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:38.493 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:38.493 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:51:38.496 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:51:38.497 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:51:38.497 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:38.497 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:38.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:38.498 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:51:38.498 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:38.499 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:51:38.499 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:38.501 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:51:38.501 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:51:38.501 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:38.501 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:38.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:38.502 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:51:38.502 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:38.502 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:51:38.502 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:38.504 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:51:38.505 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:51:38.505 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:38.505 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:38.505 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:38.505 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:51:38.505 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:38.505 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:51:38.505 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:51:38.510 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:51:38.511 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:51:38.511 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:51:38.511 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:38.512 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:38.516 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:51:38.994 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:51:39.040 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:39.043 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:39.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:39.045 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:51:39.073 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:39.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:39.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:51:39.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:39.080 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:39.081 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:39.081 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:51:39.081 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:51:39.085 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:39.087 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:39.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:39.093 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:51:39.093 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:51:39.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:39.093 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:39.462 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:51:39.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:39.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:39.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:39.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:39.657 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:39.657 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:39.657 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:51:39.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:39.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:39.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:39.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:39.661 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:39.661 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:39.661 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:39.661 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:51:39.661 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:39.661 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:39.661 [WARNING] transceiver.py:257 (TRX3@172.18.36.20:5700/3) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:39.661 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:39.661 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:39.661 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:39.661 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:39.661 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:39.661 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:39.661 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:44.665 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:44.665 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:44.665 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:44.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:44.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:44.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:44.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:44.674 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:44.674 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:44.674 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:44.675 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:51:44.679 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:51:44.679 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:51:44.680 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:44.680 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:44.680 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:44.681 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:51:44.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:44.681 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:51:44.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:44.683 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:51:44.683 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:51:44.683 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:44.683 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:44.683 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:44.683 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:51:44.684 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:44.684 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:51:44.684 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:44.686 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:51:44.686 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:51:44.686 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:44.686 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:44.686 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:44.687 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:51:44.687 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:44.687 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:51:44.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:44.690 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:51:44.691 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:51:44.691 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:51:44.691 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:44.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:44.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:44.695 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:51:45.173 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:51:45.219 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:45.222 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:45.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:45.225 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:51:45.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:45.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:45.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:51:45.257 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:45.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:45.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:45.258 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:51:45.258 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:51:45.264 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:45.267 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:45.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:45.273 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:51:45.273 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:51:45.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:45.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:45.644 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:51:45.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:45.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:45.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:45.694 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:45.834 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:45.834 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:45.834 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:51:45.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:45.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:45.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:45.838 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:45.840 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:45.840 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:45.840 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:45.840 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:51:45.840 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:45.840 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:45.840 [WARNING] transceiver.py:257 (TRX3@172.18.36.20:5700/3) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:45.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:45.840 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:45.840 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:45.840 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:45.840 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:45.840 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:45.840 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:51:50.844 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:51:50.844 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:51:50.844 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:50.844 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:50.844 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:50.844 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:50.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:51:50.850 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:50.850 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:50.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:51:50.851 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:51:50.853 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:51:50.853 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:51:50.854 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:50.854 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:50.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:51:50.854 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:51:50.855 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:51:50.855 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:51:50.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:50.856 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:51:50.856 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:51:50.856 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:50.856 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:50.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:51:50.856 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:51:50.857 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:51:50.857 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:51:50.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:50.858 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:51:50.859 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:51:50.859 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:50.859 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:51:50.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:51:50.859 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:51:50.859 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:51:50.859 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:51:50.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:50.861 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:51:50.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:51:50.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:51:50.862 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:51:50.862 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:51:50.862 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.863 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:51:50.867 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:51:51.344 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:51:51.388 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:51.390 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:51.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:51.390 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:51:51.412 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:51.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:51.412 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:51:51.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:51.417 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:51.417 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:51.417 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:51:51.417 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:51:51.436 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:51.440 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:51.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:51.449 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:51.449 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:51.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:51.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:51.814 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:51:51.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:51.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:51.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:51.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:52.287 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:51:52.760 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:51:52.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:52.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:52.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:52.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:53.231 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:51:53.704 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:51:53.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:53.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:53.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:53.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:54.176 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:51:54.649 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:51:54.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:54.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:54.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:54.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:55.120 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:51:55.593 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:51:55.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:51:55.869 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:51:55.869 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:51:55.870 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:51:56.066 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:51:56.538 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:51:57.011 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:51:57.484 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:51:57.956 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:51:58.427 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:51:58.901 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:51:59.373 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:51:59.452 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:59.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:59.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:59.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:59.477 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:51:59.477 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:51:59.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:51:59.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:59.479 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:51:59.479 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:51:59.479 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:51:59.479 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:51:59.511 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:51:59.515 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:51:59.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:51:59.526 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:51:59.526 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:51:59.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:59.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:51:59.846 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:52:00.319 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:52:00.553 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:00.553 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:00.553 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:52:00.557 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:00.557 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:00.557 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:00.557 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:00.558 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:00.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:00.558 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:00.558 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:00.558 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:00.558 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:00.558 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:52:00.558 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2094 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:00.558 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2094 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:00.558 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2094 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:00.558 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2094 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:05.564 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:05.564 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:05.565 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:05.565 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:05.565 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:05.565 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:05.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:05.571 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:05.571 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:05.571 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:05.571 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:52:05.572 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:52:05.572 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:52:05.572 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:05.572 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:05.573 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:05.573 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:52:05.573 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:05.573 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:52:05.573 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:05.573 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:52:05.573 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:52:05.573 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:05.573 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:05.574 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:05.574 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:52:05.574 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:05.574 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:52:05.574 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:05.576 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:52:05.576 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:52:05.576 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:05.576 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:05.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:05.576 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:52:05.577 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:05.577 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:52:05.577 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:05.579 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:52:05.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:52:05.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:52:05.580 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:52:05.580 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:52:05.580 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:05.585 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:52:06.062 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:52:06.107 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:06.110 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:06.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:06.112 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:52:06.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:06.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:06.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:52:06.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:06.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:06.151 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:06.151 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:52:06.151 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:52:06.200 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:06.204 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:06.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:06.219 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:52:06.219 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:52:06.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:06.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:06.536 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:52:06.583 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:06.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:06.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:06.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:06.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:06.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:06.728 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:52:06.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:06.732 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:06.732 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:06.732 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:06.734 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:06.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:06.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:06.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:06.734 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:06.734 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:06.734 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:52:06.734 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:06.735 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:06.735 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=249 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:11.744 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:11.744 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:11.744 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:11.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:11.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:11.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:11.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:11.753 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:11.753 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:11.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:11.754 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:52:11.756 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:52:11.756 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:52:11.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:11.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:11.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:11.757 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:52:11.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:11.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:52:11.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:11.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:52:11.758 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:52:11.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:11.758 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:11.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:11.758 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:52:11.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:11.758 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:52:11.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:11.760 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:52:11.760 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:52:11.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:11.760 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:11.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:11.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:52:11.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:11.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:52:11.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:52:11.762 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:52:11.762 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:52:11.762 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:11.767 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:52:12.245 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:52:12.286 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:12.289 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:12.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:12.292 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:52:12.322 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:12.322 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:12.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:52:12.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:12.327 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:12.327 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:12.327 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:52:12.327 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:52:12.336 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:12.339 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:12.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:12.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:12.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:12.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:12.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:12.717 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:52:12.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:12.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:12.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:12.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:13.188 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:52:13.659 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:52:13.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:13.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:13.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:13.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:14.133 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:52:14.605 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:52:14.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:14.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:14.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:14.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:15.077 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:52:15.548 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:52:15.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:15.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:15.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:15.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:16.021 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:52:16.494 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:52:16.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:16.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:16.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:16.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:16.966 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:52:17.440 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:52:17.912 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:52:18.385 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:52:18.858 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:52:19.331 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:52:19.803 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:52:20.274 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:52:20.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:20.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:20.349 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:20.349 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:20.366 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:20.366 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:20.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:52:20.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:20.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:20.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:20.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:52:20.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:52:20.410 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:20.414 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:20.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:20.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:20.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:20.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:20.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:20.747 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:52:21.220 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:52:21.692 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:52:22.163 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:52:22.636 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:52:23.109 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:52:23.581 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:52:24.053 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:52:24.523 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:52:24.993 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:52:25.467 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:52:25.939 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:52:26.412 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:52:26.882 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:52:27.356 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:52:27.828 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:52:28.300 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:52:28.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:28.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:28.431 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:28.431 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:28.449 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:28.449 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:28.449 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:52:28.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:28.451 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:28.451 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:28.451 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:52:28.451 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:52:28.483 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:28.486 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:28.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:28.498 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:28.498 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:28.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:28.498 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:28.771 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:52:29.244 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:52:29.717 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:52:30.189 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:52:30.662 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:52:31.134 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:52:31.606 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:52:32.077 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:52:32.548 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:52:33.021 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:52:33.494 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:52:33.966 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:52:34.437 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:52:34.908 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:52:35.381 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:52:35.854 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:52:36.326 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:52:36.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:36.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:36.503 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:36.503 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:36.522 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:36.522 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:36.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:52:36.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:36.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:36.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:36.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:52:36.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:52:36.559 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:36.563 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:36.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:36.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:36.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:36.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:36.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:36.799 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:52:37.272 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:52:37.744 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:52:38.217 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:52:38.690 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:52:39.162 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:52:39.633 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:52:40.107 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:52:40.579 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:52:41.051 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:52:41.522 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:52:41.995 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:52:42.468 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:52:42.940 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:52:43.411 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:52:43.881 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:52:44.355 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:52:44.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:44.580 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:44.581 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:44.581 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:44.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:44.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:44.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:44.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:44.597 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:44.597 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:44.597 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:44.597 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:44.597 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:44.597 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:44.597 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:52:44.597 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7093 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:44.597 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7093 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:44.597 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7093 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:44.597 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7093 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:44.597 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7093 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:44.597 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7093 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:52:49.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:49.602 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:49.603 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:49.603 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:49.603 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:49.603 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:49.615 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:49.616 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:49.616 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:49.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:49.617 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:52:49.619 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:52:49.619 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:52:49.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:49.619 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:49.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:49.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:52:49.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:49.620 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:52:49.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:49.621 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:52:49.621 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:52:49.622 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:49.622 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:49.622 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:49.622 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:52:49.622 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:49.622 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:52:49.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:49.624 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:52:49.624 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:52:49.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:49.624 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:49.624 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:49.624 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:52:49.624 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:49.624 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:52:49.624 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:49.626 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:52:49.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:52:49.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:52:49.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:52:49.626 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:52:49.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:52:49.627 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:52:49.627 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:52:49.627 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:49.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:49.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:49.631 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:52:50.108 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:52:50.152 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:50.154 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:50.155 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:50.156 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:52:50.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:50.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:50.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:52:50.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:50.188 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:50.189 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:50.189 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:52:50.189 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:52:50.201 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:50.204 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:50.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:50.217 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:52:50.217 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:52:50.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:50.218 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:50.581 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:52:50.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:50.630 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:50.630 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:50.630 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:51.054 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:52:51.526 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:52:51.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:51.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:51.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:51.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:51.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:51.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:51.756 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:52:51.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:51.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:51.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:51.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:51.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:51.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:51.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:51.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:51.760 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:52:51.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:51.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:56.766 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:56.766 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:56.766 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:56.766 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:56.766 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:56.766 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:56.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:56.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:56.773 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:56.773 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:52:56.773 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:52:56.776 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:52:56.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:52:56.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:56.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:56.777 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:56.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:52:56.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:52:56.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:52:56.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:56.778 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:52:56.779 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:52:56.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:56.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:56.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:56.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:52:56.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:52:56.779 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:52:56.779 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:56.781 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:52:56.781 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:52:56.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:56.781 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:52:56.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:56.781 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:52:56.781 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:52:56.781 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:52:56.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.784 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:52:56.784 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:52:56.784 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:52:56.784 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:52:56.789 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:52:57.267 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:52:57.309 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:57.311 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:57.313 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:52:57.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:57.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:57.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:57.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:52:57.348 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:57.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:52:57.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:52:57.349 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:52:57.349 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:52:57.359 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:52:57.362 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:52:57.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:52:57.370 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:52:57.370 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:52:57.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:57.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:52:57.734 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:52:57.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:57.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:57.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:57.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:57.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:52:57.928 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:52:57.928 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:52:57.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:52:57.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:52:57.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:52:57.934 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:53:02.940 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:02.940 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:02.940 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:02.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:02.940 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:02.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:02.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:02.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:02.950 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:02.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:02.950 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:53:02.953 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:53:02.953 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:53:02.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:02.954 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:02.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:02.954 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:53:02.955 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:02.955 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:53:02.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:02.956 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:53:02.956 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:53:02.956 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:02.956 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:02.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:02.956 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:53:02.956 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:02.956 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:53:02.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:02.958 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:53:02.958 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:53:02.958 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:02.958 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:02.959 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:02.959 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:53:02.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:02.959 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:53:02.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:53:02.961 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:53:02.962 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:53:02.962 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:53:02.962 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:02.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:02.966 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:53:03.445 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:53:03.487 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:53:03.490 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:53:03.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:03.492 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:53:03.516 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:03.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:03.517 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:53:03.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:03.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:53:03.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:53:03.523 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:53:03.523 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:53:03.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:03.548 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:53:03.548 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:53:03.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:03.548 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:03.916 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:53:03.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:03.964 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:03.964 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:03.964 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:04.389 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:53:04.862 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:53:04.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:04.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:04.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:04.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:05.335 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:53:05.807 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:53:05.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:05.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:05.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:05.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:06.281 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:53:06.753 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:53:06.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:06.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:06.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:06.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:07.226 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:53:07.699 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:53:07.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:07.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:07.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:07.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:08.172 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:53:08.644 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:53:09.115 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:53:09.589 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:53:10.061 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:53:10.534 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:53:11.007 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:53:11.480 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:53:11.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:11.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:11.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:11.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:11.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:11.575 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:11.575 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:11.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:11.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:11.579 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:11.579 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:11.579 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:11.580 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:11.580 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:53:11.580 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:11.580 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:11.580 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:11.580 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:11.581 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:11.581 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:11.581 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1859 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:16.581 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:16.581 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:16.581 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:16.581 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:16.581 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:16.581 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:16.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:16.584 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:16.585 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:16.585 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:16.585 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:53:16.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:53:16.586 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:53:16.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:16.586 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:16.586 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:16.586 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:53:16.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:16.586 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:53:16.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:16.587 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:53:16.587 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:53:16.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:16.587 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:16.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:16.587 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:53:16.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:16.587 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:53:16.587 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:16.588 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:53:16.588 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:53:16.588 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:16.588 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:16.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:16.588 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:53:16.588 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:16.588 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:53:16.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.590 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:53:16.590 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:53:16.590 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:53:16.591 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:16.591 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:16.595 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:53:17.073 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:53:17.114 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:53:17.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:17.117 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:53:17.119 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:53:17.143 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:17.143 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:17.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:53:17.148 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:17.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:53:17.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:53:17.149 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:53:17.149 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:53:17.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:17.178 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:53:17.178 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:53:17.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:17.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:17.544 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:53:17.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:17.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:17.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:17.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:18.016 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:53:18.488 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:53:18.595 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:18.595 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:18.595 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:18.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:18.962 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:53:19.435 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:53:19.596 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:19.596 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:19.596 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:19.596 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:19.908 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:53:20.381 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:53:20.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:20.598 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:20.598 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:20.598 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:20.854 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:53:21.328 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:53:21.599 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:21.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:21.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:21.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:21.801 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:53:22.274 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:53:22.747 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:53:23.219 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:53:23.693 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:53:24.165 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:53:24.637 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:53:25.111 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:53:25.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:25.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:25.186 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:25.187 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:25.187 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:53:25.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:25.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:25.205 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:25.205 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:25.207 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:25.207 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:25.207 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:25.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:25.207 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:25.207 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:25.207 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:53:30.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:30.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:30.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:30.211 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:30.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:30.211 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:30.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:30.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:30.215 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:30.216 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:30.216 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:53:30.218 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:53:30.218 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:53:30.219 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:30.219 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:30.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:30.219 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:53:30.219 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:30.219 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:53:30.220 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:30.221 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:53:30.221 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:53:30.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:30.221 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:30.221 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:30.221 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:53:30.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:30.221 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:53:30.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:30.223 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:53:30.223 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:53:30.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:30.223 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:30.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:30.223 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:53:30.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:30.223 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:53:30.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:53:30.226 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:53:30.226 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:53:30.226 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.226 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:30.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:30.231 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:53:30.709 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:53:30.750 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:53:30.752 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:53:30.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:30.753 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:53:30.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:30.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:30.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:53:30.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:30.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:53:30.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:53:30.779 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:53:30.779 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:53:31.179 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:53:31.228 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:31.228 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:31.228 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:31.229 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:31.652 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:53:32.124 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:53:32.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:32.229 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:32.230 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:32.230 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:32.595 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:53:33.068 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:53:33.231 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:33.231 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:33.231 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:33.231 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:33.540 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:53:34.012 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:53:34.232 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:34.232 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:34.232 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:34.233 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:34.483 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:53:34.954 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:53:35.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:35.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:35.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:35.234 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:35.425 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:53:35.898 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:53:36.371 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:53:36.843 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:53:37.314 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:53:37.440 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:37.440 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:37.446 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:37.446 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:37.446 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:37.446 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:37.447 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:37.447 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:37.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:37.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:37.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:37.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:37.447 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:53:37.447 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1561 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:37.447 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1561 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:37.447 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1561 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:37.447 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1561 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:37.447 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1561 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:37.447 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1561 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:42.453 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:42.454 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:42.454 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:42.454 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:42.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:42.454 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:42.462 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:42.463 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:42.463 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:42.464 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:42.464 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:53:42.469 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:53:42.469 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:53:42.470 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:42.470 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:42.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:42.470 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:53:42.471 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:42.471 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:53:42.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:42.472 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:53:42.472 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:53:42.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:42.473 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:42.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:42.473 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:53:42.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:42.473 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:53:42.473 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:42.475 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:53:42.475 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:53:42.475 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:42.475 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:42.475 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:42.475 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:53:42.476 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:42.476 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:53:42.476 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:42.478 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:53:42.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:53:42.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:53:42.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:53:42.478 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:53:42.479 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:53:42.479 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:53:42.479 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:42.484 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:53:42.960 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:53:43.006 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:53:43.008 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:53:43.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:43.010 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:53:43.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:43.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:43.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:53:43.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:43.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:53:43.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:53:43.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:53:43.047 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:53:43.432 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:53:43.481 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:43.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:43.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:43.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:43.903 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:53:44.375 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:53:44.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:44.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:44.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:44.483 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:44.848 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:53:45.320 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:53:45.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:45.484 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:45.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:45.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:45.791 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:53:46.265 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:53:46.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:46.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:46.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:46.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:46.737 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:53:47.209 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:53:47.486 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:47.486 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:47.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:47.487 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:47.680 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:53:47.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:47.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:47.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:47.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:47.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:47.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:47.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:47.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:47.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:47.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:47.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:47.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:47.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:47.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:47.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:47.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:53:48.160 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:53:48.640 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:53:49.121 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:53:49.601 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:53:50.082 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:53:50.562 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:53:51.043 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:53:51.522 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:53:52.001 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:53:52.482 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:53:52.707 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:52.707 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:52.707 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:53:52.710 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:52.710 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:52.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:52.710 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:52.710 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:52.710 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:52.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:52.716 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:52.716 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:52.716 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:52.716 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:53:52.719 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:53:52.719 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:53:52.719 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:52.719 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:52.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:52.720 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:53:52.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:52.720 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:53:52.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:52.726 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:53:52.727 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:53:52.727 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:52.727 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:52.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:52.727 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:53:52.728 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:52.728 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:53:52.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:52.734 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:53:52.734 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:53:52.734 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:52.734 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:52.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:52.734 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:53:52.735 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:52.735 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:53:52.735 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:53:52.738 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:53:52.739 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:53:52.739 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:53:52.739 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:52.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:52.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:52.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:52.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:52.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:52.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:52.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:52.740 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:53:57.748 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:53:57.748 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:53:57.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:57.748 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:57.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:57.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:57.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:53:57.755 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:57.755 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:57.755 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:53:57.755 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:53:57.756 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:53:57.757 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:53:57.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:57.757 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:57.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:53:57.757 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:53:57.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:53:57.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:53:57.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:57.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:53:57.758 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:53:57.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:57.758 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:57.758 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:53:57.758 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:53:57.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:53:57.758 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:53:57.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:57.759 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:53:57.759 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:53:57.759 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:57.759 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:53:57.759 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:53:57.759 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:53:57.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:53:57.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:53:57.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:57.761 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:53:57.762 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:53:57.762 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:53:57.762 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:53:57.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:53:57.767 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:53:58.244 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:53:58.285 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:53:58.287 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:53:58.289 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:53:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:53:58.313 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:53:58.313 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:53:58.314 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:53:58.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:53:58.319 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:53:58.319 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:53:58.319 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:53:58.319 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:53:58.716 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:53:58.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:58.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:58.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:58.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:53:59.187 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:53:59.660 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:53:59.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:53:59.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:53:59.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:53:59.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:00.133 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:54:00.605 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:54:00.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:00.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:00.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:00.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:01.076 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:54:01.549 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:54:01.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:01.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:01.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:01.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:02.016 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:54:02.479 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:54:02.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:02.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:02.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:02.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:02.941 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:54:03.409 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:54:03.881 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:54:03.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:04.352 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:54:04.817 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:54:04.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:05.282 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:54:05.747 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:54:05.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:06.213 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:54:06.681 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:54:06.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:07.147 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:54:07.612 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:54:07.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:07.963 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:08.078 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:54:08.542 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:54:09.005 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:54:09.474 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:54:09.943 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:54:10.412 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:54:10.881 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:54:11.349 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:54:11.816 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:54:11.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:12.286 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:54:12.757 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:54:12.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:13.229 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:54:13.700 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:54:13.963 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:14.171 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:54:14.640 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:54:14.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:15.110 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:54:15.580 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:54:15.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:16.049 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:54:16.519 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:54:16.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:16.987 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:54:17.452 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:54:17.916 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:54:18.380 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:54:18.845 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:54:19.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:19.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:19.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:19.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:19.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:19.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:19.006 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:19.006 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:19.006 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:19.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:19.006 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:54:19.006 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:54:19.006 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:54:24.012 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:54:24.012 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:54:24.013 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:24.013 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:24.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:24.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:24.026 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:24.026 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:54:24.026 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:24.027 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:54:24.027 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:54:24.029 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:54:24.029 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:54:24.029 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:54:24.029 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:24.029 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:24.029 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:54:24.030 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:54:24.030 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:54:24.030 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:24.031 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:54:24.031 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:54:24.031 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:54:24.031 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:24.031 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:24.031 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:54:24.031 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:54:24.031 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:54:24.031 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:24.034 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:54:24.034 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:54:24.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:54:24.034 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:24.034 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:24.034 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:54:24.034 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:54:24.034 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:54:24.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:54:24.037 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:54:24.037 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:54:24.037 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:24.037 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.038 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:24.042 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:54:24.516 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:54:24.550 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:54:24.551 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:54:24.551 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:54:24.552 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:54:24.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:24.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:24.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:54:24.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:24.558 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:54:24.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:54:24.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:54:24.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:54:24.605 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:54:24.605 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:54:24.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:54:24.609 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:54:24.609 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:54:24.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:24.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:24.980 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:54:25.040 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:25.040 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:25.042 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:25.044 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:25.446 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:54:25.883 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:54:25.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:25.884 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:25.884 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:25.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:25.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:25.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:25.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:25.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:25.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:25.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:54:25.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:54:25.895 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:54:25.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:25.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:30.901 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:54:30.902 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:54:30.902 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:30.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:30.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:30.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:30.915 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:30.916 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:54:30.916 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:30.916 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:54:30.916 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:54:30.920 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:54:30.921 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:54:30.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:54:30.921 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:30.921 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:30.921 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:54:30.922 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:54:30.922 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:54:30.922 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:30.924 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:54:30.924 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:54:30.924 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:54:30.925 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:30.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:30.925 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:54:30.925 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:54:30.925 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:54:30.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:30.927 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:54:30.927 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:54:30.927 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:54:30.927 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:30.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:30.927 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:54:30.927 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:54:30.927 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:54:30.927 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:54:30.930 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:54:30.930 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:54:30.930 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.930 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:30.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:30.935 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:54:31.406 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:54:31.454 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:54:31.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:54:31.455 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:54:31.456 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:54:31.466 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:31.466 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:31.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:54:31.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:31.470 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:54:31.470 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:54:31.470 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:54:31.470 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:54:31.501 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:54:31.510 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:54:31.525 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:54:31.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:54:31.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:54:31.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:31.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:31.872 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:54:31.933 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:31.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:31.934 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:31.934 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:32.337 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:54:32.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 02:54:32.781 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:32.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:32.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:32.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:32.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:32.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:32.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:32.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:32.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:32.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:32.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:32.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:54:32.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:54:32.794 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:54:37.801 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:54:37.801 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:54:37.802 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:37.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:37.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:37.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:37.816 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:54:37.817 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:54:37.818 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:37.818 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:54:37.818 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:54:37.823 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:54:37.823 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:54:37.823 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:54:37.823 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:37.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:54:37.823 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:54:37.824 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:54:37.824 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:54:37.824 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:37.827 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:54:37.827 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:54:37.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:54:37.827 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:37.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:54:37.827 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:54:37.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:54:37.827 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:54:37.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:37.830 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:54:37.830 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:54:37.830 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:54:37.830 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:54:37.830 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:54:37.830 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:54:37.830 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:54:37.830 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:54:37.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:54:37.834 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:54:37.835 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:54:37.835 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:54:37.835 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:54:37.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:54:37.840 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:54:38.309 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:54:38.357 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:54:38.358 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:54:38.359 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:54:38.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:54:38.371 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:38.371 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:38.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:54:38.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:38.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:54:38.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:54:38.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:54:38.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:54:38.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:54:38.403 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:54:38.403 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:54:38.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:38.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:38.776 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:54:38.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:38.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:38.838 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:38.839 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:39.247 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:54:39.717 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:54:39.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:39.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:39.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:39.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:40.185 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:54:40.650 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:54:40.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:40.840 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:40.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:40.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:41.119 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:54:41.586 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:54:41.840 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:41.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:41.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:41.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:42.054 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:54:42.524 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:54:42.841 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:54:42.841 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:54:42.841 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:54:42.842 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:54:42.994 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:54:43.461 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:54:43.930 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:54:44.395 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:54:44.864 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:54:45.335 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:54:45.806 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:54:46.279 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:54:46.752 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:54:47.224 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:54:47.695 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:54:48.166 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:54:48.639 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:54:49.112 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:54:49.584 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:54:50.056 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:54:50.529 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:54:51.002 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:54:51.474 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:54:51.945 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:54:52.418 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:54:52.891 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:54:53.363 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:54:53.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:54:53.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:53.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:53.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:53.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:54:53.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:54:53.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:54:53.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:53.678 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:54:53.678 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:54:53.678 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:54:53.678 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:54:53.686 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:54:53.688 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:54:53.689 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 02:54:53.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:53.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:54:53.834 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:54:54.305 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:54:54.779 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:54:55.251 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:54:55.725 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:54:56.198 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:54:56.671 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:54:57.144 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:54:57.617 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:54:58.090 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:54:58.563 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:54:59.036 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:54:59.508 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:54:59.982 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:55:00.454 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:55:00.927 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:55:01.400 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:55:01.873 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:55:02.345 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:55:02.819 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:55:03.291 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 02:55:03.763 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 02:55:04.235 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 02:55:04.709 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 02:55:05.182 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 02:55:05.655 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 02:55:06.128 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 02:55:06.600 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 02:55:07.072 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 02:55:07.546 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 02:55:08.019 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 02:55:08.492 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 02:55:08.965 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 02:55:09.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:55:09.147 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:09.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:55:09.149 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:55:09.149 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:55:09.159 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:55:09.159 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:55:09.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:55:09.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:09.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:55:09.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:55:09.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:55:09.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:55:09.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:55:09.208 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:55:09.209 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 02:55:09.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:09.209 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:09.438 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 02:55:09.910 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 02:55:10.394 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 02:55:10.866 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 02:55:11.339 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 02:55:11.812 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 02:55:12.284 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 02:55:12.757 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 02:55:13.230 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 02:55:13.702 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 02:55:14.175 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 02:55:14.648 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 02:55:15.120 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 02:55:15.593 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 02:55:16.066 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 02:55:16.539 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 02:55:17.012 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 02:55:17.484 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 02:55:17.956 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 02:55:18.429 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 02:55:18.902 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 02:55:19.374 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 02:55:19.847 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 02:55:20.321 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 02:55:20.792 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 02:55:21.265 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 02:55:21.739 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 02:55:22.210 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 02:55:22.684 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 02:55:23.157 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 02:55:23.628 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 02:55:24.102 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 02:55:24.575 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 02:55:24.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:55:24.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:24.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:55:24.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:55:24.645 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:55:24.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:55:24.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:55:24.665 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:55:24.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:24.666 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:55:24.666 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:55:24.666 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:55:24.666 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:55:24.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:24.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:55:24.725 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:55:24.725 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:55:24.725 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:24.726 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:25.047 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 02:55:25.520 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 02:55:25.993 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 02:55:26.465 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 02:55:26.939 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 02:55:27.411 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 02:55:27.884 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 02:55:28.357 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 02:55:28.830 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 02:55:29.303 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 02:55:29.776 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 02:55:30.249 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 02:55:30.721 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 02:55:31.194 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 02:55:31.667 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 02:55:32.139 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 02:55:32.613 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 02:55:33.086 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 02:55:33.558 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 02:55:34.029 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 02:55:34.502 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 02:55:34.975 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 02:55:35.447 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 02:55:35.920 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 02:55:36.393 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 02:55:36.866 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 02:55:37.339 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 02:55:37.812 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 02:55:38.284 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 02:55:38.758 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 02:55:39.231 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 02:55:39.703 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 02:55:40.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:55:40.126 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:40.127 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:55:40.127 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:55:40.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:40.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:40.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:40.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:40.140 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:55:40.140 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:55:40.141 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:55:40.141 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:55:40.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:55:40.141 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:55:40.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:55:40.141 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:55:40.141 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:55:40.141 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:55:40.141 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:55:40.141 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:55:40.141 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=13459 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:55:45.144 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:55:45.144 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:55:45.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:55:45.145 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:55:45.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:55:45.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:55:45.153 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:55:45.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:55:45.154 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:45.154 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:55:45.154 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:55:45.158 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:55:45.158 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:55:45.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:55:45.158 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:45.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:55:45.158 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:55:45.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:55:45.159 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:55:45.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:45.161 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:55:45.161 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:55:45.161 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:55:45.161 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:45.161 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:55:45.161 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:55:45.162 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:55:45.162 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:55:45.162 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:45.163 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:55:45.163 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:55:45.163 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:55:45.163 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:45.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:55:45.164 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:55:45.164 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:55:45.164 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:55:45.164 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:45.167 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:55:45.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:55:45.167 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:55:45.167 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:55:45.167 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:55:45.167 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:55:45.168 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:55:45.168 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:55:45.168 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:45.168 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:45.169 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:55:45.169 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:45.169 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:45.169 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:45.169 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:55:45.169 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:55:45.170 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:55:45.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:45.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:45.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:55:50.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:55:50.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:55:50.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:55:50.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:55:50.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:55:50.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:55:50.184 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:55:50.184 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:50.185 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:55:50.185 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:55:50.188 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:55:50.188 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:55:50.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:55:50.189 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:50.189 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:55:50.189 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:55:50.189 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:55:50.189 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:55:50.189 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:50.192 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:55:50.193 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:55:50.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:55:50.193 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:50.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:55:50.194 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:55:50.194 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:55:50.194 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:55:50.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:50.195 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:55:50.196 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:55:50.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:55:50.196 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:55:50.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:55:50.196 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:55:50.196 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:55:50.196 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:55:50.196 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:50.200 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:55:50.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:55:50.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:55:50.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:55:50.200 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:55:50.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.201 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:55:50.201 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:55:50.201 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:55:50.201 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.202 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:55:50.206 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:55:50.684 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:55:50.739 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:55:50.742 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:55:50.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:55:50.744 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:55:50.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:55:50.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:55:50.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:55:50.783 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:55:50.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:50.785 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:55:50.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:55:50.786 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:55:50.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:55:50.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:55:50.835 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:55:50.835 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:55:50.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:50.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:55:51.155 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:55:51.205 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:51.205 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:51.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:51.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:51.628 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:55:52.100 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:55:52.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:52.206 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:52.208 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:52.208 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:52.571 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:55:53.044 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:55:53.207 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:53.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:53.209 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:53.209 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:53.517 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:55:53.989 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:55:54.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:54.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:54.210 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:54.210 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:54.463 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:55:54.936 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:55:55.208 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:55:55.209 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:55:55.211 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:55:55.212 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:55:55.408 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:55:55.882 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:55:56.354 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:55:56.827 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:55:57.297 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:55:57.771 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:55:58.244 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:55:58.716 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:55:59.189 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:55:59.662 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:56:00.135 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:56:00.606 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:56:01.079 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:56:01.551 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:56:01.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:01.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:01.649 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:56:01.649 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:56:01.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:01.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:01.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:01.658 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:01.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:01.660 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:01.660 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:01.660 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:01.660 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:56:01.660 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:56:01.660 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:56:01.660 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2473 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:01.660 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2473 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:01.660 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2473 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:01.660 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2473 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:01.660 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2473 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:01.660 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2473 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:06.665 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:56:06.665 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:56:06.665 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:06.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:06.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:06.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:06.673 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:06.674 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:56:06.675 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:06.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:56:06.675 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:56:06.679 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:56:06.680 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:56:06.680 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:56:06.680 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:06.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:06.681 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:56:06.682 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:56:06.682 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:56:06.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:06.684 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:56:06.684 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:56:06.685 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:56:06.685 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:06.685 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:06.685 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:56:06.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:56:06.686 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:56:06.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:06.687 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:56:06.687 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:56:06.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:56:06.688 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:06.688 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:06.688 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:56:06.688 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:56:06.688 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:56:06.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:06.691 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:56:06.691 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:56:06.691 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:56:06.691 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:56:06.691 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:56:06.692 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:56:06.692 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:56:06.692 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:06.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:06.697 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:56:07.175 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:56:07.217 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:56:07.219 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:56:07.219 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:07.221 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:56:07.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:56:07.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:56:07.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:56:07.249 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:56:07.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:07.252 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:56:07.252 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:56:07.252 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:56:07.252 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:56:07.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:07.276 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:56:07.277 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:56:07.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:07.277 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:07.646 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:56:07.694 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:07.695 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:07.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:07.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:08.118 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:56:08.590 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:56:08.696 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:08.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:08.696 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:08.697 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:09.062 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:56:09.535 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:56:09.697 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:09.698 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:09.698 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:09.698 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:10.007 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:56:10.479 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:56:10.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:10.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:10.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:10.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:10.951 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:56:11.424 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:56:11.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:11.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:11.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:11.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:11.897 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:56:12.369 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:56:12.842 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:56:13.315 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:56:13.787 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:56:14.258 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:56:14.729 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:56:15.203 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:56:15.675 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:56:16.148 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:56:16.618 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:56:17.089 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:56:17.563 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:56:17.652 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:17.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:17.655 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:56:17.655 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:56:17.657 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:17.657 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:17.657 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:17.657 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:17.658 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:17.658 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:17.658 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:17.658 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:17.658 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:56:17.658 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:56:17.658 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:56:22.665 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:56:22.665 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:56:22.665 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:22.665 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:22.665 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:22.665 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:22.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:22.675 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:56:22.676 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:22.676 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:56:22.676 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:56:22.681 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:56:22.681 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:56:22.681 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:56:22.682 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:22.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:22.683 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:56:22.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:56:22.683 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:56:22.683 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:22.685 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:56:22.686 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:56:22.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:56:22.686 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:22.686 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:22.686 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:56:22.686 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:56:22.686 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:56:22.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:22.690 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:56:22.690 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:56:22.690 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:56:22.690 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:22.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:22.690 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:56:22.690 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:56:22.690 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:56:22.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.695 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:56:22.695 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:56:22.695 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:56:22.696 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.696 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:22.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:22.700 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:56:23.178 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:56:23.221 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:56:23.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:23.225 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:56:23.228 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:56:23.265 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:56:23.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:56:23.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:56:23.276 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:56:23.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:23.279 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:56:23.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:56:23.280 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:56:23.280 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:56:23.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:23.328 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:56:23.328 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:56:23.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:23.328 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:23.649 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:56:23.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:23.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:23.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:23.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:24.121 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:56:24.594 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:56:24.617 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:24.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:24.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:24.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:24.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:25.067 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:56:25.540 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:56:25.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:25.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:25.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:25.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:26.012 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:56:26.486 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:56:26.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:26.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:26.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:26.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:26.959 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:56:27.433 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:56:27.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:27.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:27.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:27.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:27.905 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:56:28.376 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:56:28.847 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:56:29.320 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:56:29.793 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:56:30.265 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:56:30.736 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:56:31.210 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:56:31.682 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:56:32.155 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:56:32.628 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:56:33.101 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:56:33.573 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:56:34.044 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:56:34.515 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:56:34.986 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:56:35.456 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:56:35.927 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:56:36.401 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:56:36.874 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:56:37.347 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:56:37.820 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:56:38.292 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:56:38.763 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:56:39.236 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:56:39.709 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:56:40.181 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:56:40.652 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:56:41.126 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:56:41.599 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:56:42.071 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:56:42.545 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:56:43.017 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:56:43.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:43.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:43.350 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:56:43.350 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:56:43.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:43.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:43.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:43.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:43.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:43.361 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:56:43.361 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:56:43.361 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:56:43.361 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:43.361 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:43.361 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:43.361 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4462 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:43.361 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4462 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:43.361 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4462 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:43.361 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4462 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:43.361 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4462 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:43.361 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4462 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:48.365 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:56:48.365 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:56:48.365 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:48.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:48.365 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:48.365 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:48.373 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:48.374 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:56:48.374 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:48.375 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:56:48.375 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:56:48.378 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:56:48.379 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:56:48.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:56:48.379 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:48.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:48.380 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:56:48.381 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:56:48.381 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:56:48.381 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:48.383 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:56:48.383 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:56:48.383 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:56:48.383 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:48.384 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:48.384 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:56:48.384 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:56:48.384 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:56:48.385 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:48.386 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:56:48.386 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:56:48.387 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:56:48.387 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:56:48.387 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:48.387 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:56:48.387 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:56:48.387 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:56:48.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:48.390 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:56:48.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:56:48.390 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:56:48.390 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:56:48.390 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:56:48.390 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:56:48.391 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:56:48.391 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:56:48.391 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.391 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:56:48.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:56:48.396 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:56:48.873 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:56:48.919 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:56:48.922 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:56:48.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:48.923 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:56:48.957 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:56:48.957 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:56:48.957 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:56:48.964 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:56:48.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:48.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:56:48.967 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:56:48.967 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:56:48.967 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:56:49.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:49.026 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:56:49.026 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:56:49.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:49.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:49.344 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:56:49.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:49.394 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:49.394 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:49.394 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:49.817 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:56:50.290 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:56:50.312 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:50.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:50.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:50.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:50.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:50.761 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:56:51.235 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:56:51.278 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:51.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:51.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:51.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:51.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:51.707 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:56:52.180 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:56:52.238 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:52.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:52.397 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:52.397 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:52.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:52.653 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:56:53.125 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:56:53.204 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:53.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:53.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:53.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:53.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:53.599 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:56:54.072 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:56:54.171 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:54.544 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:56:55.015 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:56:55.131 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:55.489 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:56:55.961 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:56:56.097 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:56.433 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:56:56.907 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:56:57.061 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:57.380 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:56:57.851 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:56:58.021 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:58.321 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:56:58.792 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:56:58.982 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:56:59.266 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:56:59.738 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:56:59.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:56:59.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:56:59.841 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:56:59.841 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:56:59.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:56:59.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:56:59.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:56:59.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:56:59.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:56:59.858 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:56:59.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:56:59.859 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:56:59.859 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:56:59.859 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:56:59.859 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:56:59.859 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2476 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:59.859 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2476 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:59.860 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2476 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:59.860 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2476 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:59.860 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2476 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:59.860 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2476 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:56:59.860 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2476 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:04.861 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:04.861 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:04.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:04.861 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:04.861 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:04.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:04.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:04.870 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:04.870 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:04.871 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:04.871 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:57:04.875 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:57:04.875 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:57:04.875 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:04.876 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:04.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:04.876 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:57:04.877 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:04.877 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:57:04.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:04.879 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:57:04.879 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:57:04.879 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:04.879 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:04.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:04.880 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:57:04.880 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:04.880 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:57:04.880 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:04.882 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:57:04.882 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:57:04.882 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:04.882 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:04.882 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:04.882 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:57:04.883 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:04.883 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:57:04.883 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.886 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:57:04.886 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:57:04.886 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:57:04.887 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:04.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:04.891 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:57:05.370 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:57:05.413 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:57:05.414 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:05.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:05.415 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:57:05.437 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:05.437 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:05.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:05.445 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:57:05.447 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:05.448 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:05.448 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:05.448 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:05.448 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:05.448 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:05.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:05.471 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:05.471 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:05.471 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:05.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:05.471 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:05.841 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:57:05.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:05.889 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:05.889 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:05.889 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:06.313 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:57:06.327 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:57:06.787 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:57:06.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:06.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:06.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:06.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:07.259 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:57:07.731 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:57:07.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:07.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:07.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:07.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:08.204 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:57:08.674 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:57:08.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:08.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:08.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:08.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:09.147 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:57:09.620 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:57:09.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:09.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:09.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:09.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:10.093 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:57:10.566 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:57:11.037 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:57:11.510 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:57:11.983 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:57:12.455 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:57:12.926 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:57:13.400 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:57:13.872 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:57:14.345 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:57:14.816 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:57:15.287 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:57:15.760 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:57:15.962 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:16.233 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:57:16.706 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:57:17.179 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:57:17.652 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:57:18.125 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:57:18.598 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:57:19.070 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:57:19.541 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:57:20.015 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:57:20.487 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:57:20.959 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:57:21.430 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:57:21.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:21.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:21.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:21.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:21.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:21.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:21.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:21.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:21.764 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:21.764 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:21.764 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:21.764 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:57:21.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:21.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:21.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:21.765 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:21.765 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:21.765 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:21.766 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:21.766 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:21.766 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:21.766 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3644 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:26.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:26.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:26.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:26.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:26.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:26.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:26.775 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:26.777 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:26.777 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:26.778 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:26.778 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:57:26.782 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:57:26.782 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:57:26.783 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:26.783 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:26.784 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:26.784 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:57:26.785 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:26.785 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:57:26.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:26.788 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:57:26.788 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:57:26.789 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:26.789 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:26.789 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:26.790 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:57:26.790 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:26.790 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:57:26.790 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:26.792 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:57:26.792 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:57:26.792 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:26.792 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:26.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:26.792 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:57:26.793 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:26.793 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:57:26.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.797 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:57:26.797 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:57:26.797 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:57:26.798 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.798 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.799 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:26.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.799 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:26.799 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:26.802 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:57:27.281 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:57:27.330 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:57:27.333 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:27.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:27.335 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:57:27.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:27.353 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:27.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:27.359 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:27.362 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:27.362 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:27.362 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:27.362 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:27.362 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:27.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:27.381 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:27.381 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:27.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:27.381 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:27.752 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:57:27.800 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:27.800 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:27.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:27.801 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:28.225 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:57:28.241 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:57:28.697 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:57:28.801 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:28.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:28.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:28.802 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:29.171 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:57:29.643 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:57:29.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:29.802 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:29.802 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:29.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:30.116 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:57:30.589 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:57:30.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:30.803 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:30.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:30.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:31.062 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:57:31.534 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:57:31.803 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:31.804 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:31.804 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:31.804 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:32.008 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:57:32.480 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:57:32.953 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:57:33.426 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:57:33.899 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:57:34.371 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:57:34.842 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:57:35.316 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:57:35.788 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:57:36.261 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:57:36.734 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:57:37.207 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:57:37.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:37.386 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:37.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:37.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:37.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:37.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:37.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:37.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:37.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:37.396 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:37.396 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:37.396 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:57:37.396 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:37.396 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:37.396 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:37.396 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:37.396 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:37.396 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:37.396 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:37.396 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:37.396 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:42.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:42.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:42.403 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:42.403 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:42.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:42.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:42.412 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:42.414 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:42.414 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:42.415 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:42.415 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:57:42.420 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:57:42.420 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:57:42.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:42.421 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:42.421 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:42.422 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:57:42.422 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:42.423 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:57:42.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:42.425 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:57:42.426 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:57:42.426 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:42.426 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:42.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:42.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:57:42.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:42.428 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:57:42.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:42.430 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:57:42.430 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:57:42.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:42.430 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:42.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:42.430 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:57:42.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:42.430 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:57:42.431 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:42.434 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:57:42.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:57:42.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:57:42.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.435 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:57:42.435 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:57:42.435 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:57:42.435 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.437 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:42.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.437 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:42.437 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:42.440 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:57:42.919 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:57:42.965 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:57:42.967 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:42.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:42.969 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:57:42.983 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:42.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:42.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:42.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:42.985 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:42.985 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:42.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:42.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:43.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:43.032 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:43.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:43.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:43.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:43.391 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:57:43.439 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:43.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:43.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:43.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:43.863 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:57:43.879 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:43.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:43.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:43.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:43.898 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:43.898 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:43.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:43.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:43.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:43.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:43.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:43.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:43.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:43.905 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:57:43.905 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:57:43.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:43.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.334 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:57:44.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:44.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:44.442 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:44.442 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:44.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:44.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:44.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:44.603 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:57:44.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:44.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:44.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:44.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.623 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:44.623 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:44.623 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:44.623 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:44.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:44.670 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:44.670 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:44.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:44.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.773 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:44.773 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:44.789 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:44.789 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:44.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:44.790 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.790 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:44.790 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:44.790 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:44.790 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:44.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:44.802 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:57:44.802 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:57:44.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:44.807 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:57:45.194 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:45.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:45.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:45.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:45.198 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:57:45.206 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:45.207 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:45.207 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:45.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:45.210 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:45.211 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:45.211 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:45.211 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:57:45.211 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:45.212 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:45.212 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:45.212 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:45.212 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:45.212 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:45.212 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:45.212 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:45.212 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:45.212 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:50.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:50.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:50.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:50.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:50.213 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:50.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:50.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:50.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:50.224 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:50.224 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:50.224 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:57:50.229 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:57:50.229 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:57:50.229 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:50.230 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:50.230 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:50.230 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:57:50.230 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:50.230 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:57:50.230 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:50.233 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:57:50.233 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:57:50.233 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:50.233 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:50.233 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:50.234 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:57:50.234 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:50.234 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:57:50.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:50.236 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:57:50.236 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:57:50.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:50.237 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:50.237 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:50.237 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:57:50.237 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:50.237 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:57:50.237 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:57:50.241 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:57:50.242 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:57:50.242 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:57:50.242 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.242 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:50.247 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:57:50.725 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:57:50.771 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:57:50.772 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:50.773 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:57:50.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:50.792 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:50.792 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:50.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:50.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:50.799 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:50.799 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:50.799 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:50.799 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:50.818 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:57:50.822 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 02:57:50.827 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:50.831 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:50.831 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:50.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:50.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:51.198 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:57:51.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:51.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:51.208 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:51.208 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:51.218 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:51.218 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:51.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:51.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:51.220 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:51.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:51.220 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:51.220 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:51.220 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:51.220 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:51.220 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:57:51.221 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:51.221 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:51.221 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:51.221 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:51.221 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:51.221 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=211 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:57:56.225 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:57:56.225 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:57:56.225 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:56.225 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:56.225 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:56.225 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:56.235 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:57:56.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:56.236 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:56.236 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:57:56.236 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:57:56.239 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:57:56.239 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:57:56.239 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:56.239 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:56.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:57:56.240 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:57:56.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:57:56.240 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:57:56.240 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:56.244 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:57:56.244 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:57:56.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:56.245 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:56.245 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:57:56.245 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:57:56.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:57:56.245 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:57:56.246 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:56.249 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:57:56.250 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:57:56.250 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:56.250 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:57:56.250 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:57:56.250 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:57:56.250 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:57:56.250 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:57:56.251 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:56.256 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:57:56.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:57:56.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:57:56.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:57:56.256 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:57:56.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.257 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:57:56.257 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:57:56.257 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:57:56.258 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:57:56.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:57:56.258 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.258 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:57:56.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:57:56.262 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:57:56.741 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:57:56.794 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:57:56.796 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:57:56.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:56.799 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:57:56.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:56.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:56.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:56.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:56.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:56.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:56.828 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:56.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:57:56.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:56.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:56.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:56.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:56.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:56.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:57.211 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:57:57.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:57.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:57.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:57.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:57.684 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:57:58.157 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:57:58.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:58.277 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:58.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:58.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:58.630 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:57:59.103 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:57:59.279 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:57:59.279 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:57:59.279 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:57:59.279 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:57:59.575 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:57:59.966 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:57:59.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:59.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:59.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:59.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:57:59.991 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:57:59.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:57:59.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:57:59.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:57:59.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:57:59.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:57:59.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:58:00.048 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:58:00.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:00.056 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:58:00.056 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 02:58:00.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:00.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:00.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:00.280 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:00.281 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:00.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:00.281 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:00.522 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:58:00.994 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:58:01.282 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:01.282 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:01.282 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:01.282 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:01.468 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:58:01.942 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:58:02.416 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:58:02.889 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:58:03.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:03.215 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:03.217 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:03.217 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:03.217 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:58:03.237 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:03.237 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:03.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:58:03.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:03.239 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:58:03.240 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:58:03.240 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:58:03.240 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:58:03.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:03.288 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:58:03.288 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:58:03.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:03.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:03.362 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:58:03.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:03.834 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:58:04.305 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:58:04.776 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:58:05.249 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:58:05.722 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:58:06.194 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:58:06.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:06.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:06.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:06.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:06.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:06.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:06.620 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:58:06.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:06.621 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:58:06.621 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:58:06.621 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:58:06.621 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:58:06.665 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:58:06.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:06.668 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:58:06.668 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:58:06.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:06.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:06.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:07.136 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:58:07.610 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:58:08.083 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:58:08.556 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:58:09.028 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:58:09.501 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:58:09.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:09.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:09.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:09.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:09.829 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:58:09.839 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:09.839 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:09.840 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:09.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:09.841 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:58:09.841 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:58:09.841 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:58:09.841 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:58:09.841 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:58:09.841 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:58:09.841 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:58:09.841 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:09.841 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:09.841 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:09.841 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:09.841 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:09.841 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2932 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:14.846 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:58:14.847 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:58:14.847 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:58:14.847 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:58:14.847 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:58:14.847 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:58:14.855 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:58:14.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:58:14.856 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:14.856 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:58:14.857 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:58:14.859 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:58:14.860 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:58:14.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:58:14.860 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:14.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:58:14.861 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:58:14.861 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:58:14.861 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:58:14.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:14.862 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:58:14.863 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:58:14.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:58:14.863 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:14.863 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:58:14.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:58:14.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:58:14.863 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:58:14.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:14.865 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:58:14.865 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:58:14.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:58:14.865 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:14.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:58:14.865 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:58:14.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:58:14.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:58:14.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:58:14.869 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:58:14.869 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:58:14.869 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.869 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:14.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:14.873 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:58:15.351 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:58:15.395 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:58:15.397 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:58:15.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:15.400 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:58:15.403 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:15.403 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:15.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:58:15.404 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:15.405 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:58:15.405 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:58:15.406 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:58:15.406 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:58:15.822 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:58:15.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:15.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:15.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:15.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:16.294 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:58:16.767 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:58:16.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:16.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:16.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:16.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:17.240 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:58:17.712 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:58:17.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:17.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:17.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:17.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:18.183 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:58:18.656 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:58:18.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:18.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:18.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:18.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:19.129 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:58:19.601 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:58:19.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:19.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:19.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:19.876 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:20.074 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:58:20.547 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:58:21.019 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:58:21.490 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:58:21.963 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:58:22.436 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:58:22.907 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:58:23.379 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:58:23.852 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:58:24.324 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:58:24.796 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:58:25.267 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:58:25.740 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:58:26.213 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:58:26.685 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:58:27.156 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:58:27.630 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:58:28.102 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:58:28.574 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:58:29.047 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:58:29.332 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:29.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:29.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:29.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:29.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:29.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:29.344 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:58:29.344 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:58:29.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:58:29.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:58:29.344 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:58:29.344 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:58:29.344 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:58:29.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:29.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:29.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:29.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:29.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:29.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:29.344 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:58:34.348 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:58:34.348 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:58:34.348 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:58:34.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:58:34.348 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:58:34.348 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:58:34.358 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:58:34.360 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:58:34.360 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:34.361 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:58:34.361 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:58:34.367 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:58:34.367 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:58:34.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:58:34.367 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:34.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:58:34.368 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:58:34.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:58:34.368 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:58:34.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:34.372 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:58:34.372 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:58:34.372 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:58:34.372 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:34.372 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:58:34.372 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:58:34.373 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:58:34.373 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:58:34.373 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:34.376 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:58:34.377 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:58:34.377 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:58:34.377 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:58:34.377 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:58:34.377 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:58:34.377 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:58:34.377 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:58:34.377 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:34.382 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:58:34.382 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:58:34.382 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:58:34.382 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:58:34.382 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.383 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:58:34.383 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:58:34.383 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:58:34.384 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:58:34.388 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:58:34.866 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:58:34.919 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:58:34.921 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:58:34.922 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:58:34.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:34.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:34.947 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:34.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:58:34.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:34.951 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:58:34.951 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:58:34.951 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:58:34.951 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:58:34.959 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:34.963 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 02:58:34.963 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 02:58:34.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:34.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:35.337 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:58:35.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:35.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:35.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:35.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:35.809 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:58:36.283 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:58:36.388 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:36.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:36.390 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:36.755 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:58:36.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:36.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:36.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:36.964 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 02:58:36.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:58:36.968 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:58:36.968 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:58:36.968 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:58:36.968 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:58:36.968 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:58:37.227 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:58:37.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:37.389 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:37.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:37.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:37.698 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:58:38.171 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:58:38.389 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:38.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:38.390 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:38.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:38.643 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:58:39.115 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:58:39.390 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:39.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:39.391 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:39.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:39.586 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:58:40.060 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:58:40.532 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:58:41.004 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:58:41.478 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:58:41.950 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:58:42.423 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:58:42.896 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:58:43.368 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:58:43.840 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:58:44.311 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:58:44.784 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:58:45.257 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:58:45.729 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:58:46.203 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:58:46.675 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:58:47.147 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:58:47.618 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:58:48.092 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:58:48.564 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:58:49.036 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:58:49.507 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:58:49.981 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:58:50.453 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:58:50.925 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:58:51.396 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:58:51.869 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:58:52.342 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:58:52.814 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:58:53.285 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:58:53.758 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:58:54.230 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:58:54.703 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:58:55.175 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:58:55.648 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:58:56.121 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:58:56.594 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 02:58:57.067 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 02:58:57.538 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 02:58:58.010 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 02:58:58.483 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 02:58:58.955 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 02:58:59.427 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 02:58:59.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:58:59.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:58:59.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:58:59.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:58:59.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:58:59.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:58:59.719 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:58:59.720 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:58:59.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:58:59.720 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:58:59.720 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:58:59.720 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:58:59.720 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:58:59.720 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:59:04.724 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:59:04.724 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:59:04.724 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:04.724 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:04.724 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:04.724 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:04.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:04.735 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:59:04.735 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:04.736 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:59:04.736 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:59:04.741 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:59:04.742 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:59:04.742 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:59:04.742 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:04.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:04.743 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:59:04.744 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:59:04.744 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:59:04.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:04.746 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:59:04.746 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:59:04.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:59:04.747 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:04.747 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:04.747 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:59:04.747 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:59:04.747 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:59:04.748 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:04.750 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:59:04.750 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:59:04.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:59:04.751 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:04.751 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:04.751 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:59:04.751 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:59:04.751 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:59:04.751 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.755 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:59:04.755 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:59:04.755 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:59:04.756 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:04.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:04.760 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:59:05.239 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:59:05.290 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:59:05.292 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:59:05.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:59:05.294 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:59:05.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:59:05.298 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:59:05.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:59:05.298 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:59:05.298 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:59:05.298 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:59:05.299 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:59:05.299 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:59:05.711 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:59:05.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:05.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:05.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:05.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:06.183 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:59:06.654 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:59:06.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:06.762 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:06.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:06.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:07.124 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:59:07.598 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:59:07.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:07.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:07.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:07.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:08.071 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:59:08.543 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:59:08.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:08.764 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:08.764 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:08.764 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:09.014 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:59:09.487 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:59:09.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:09.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:09.766 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:09.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:09.960 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:59:10.432 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:59:10.903 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:59:11.376 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:59:11.849 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:59:12.321 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:59:12.794 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:59:13.267 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:59:13.739 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:59:14.210 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:59:14.683 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:59:15.156 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:59:15.628 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:59:16.099 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:59:16.572 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:59:17.045 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:59:17.517 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:59:17.988 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:59:18.461 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:59:18.933 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:59:19.406 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:59:19.876 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:59:20.350 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:59:20.822 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:59:21.294 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:59:21.768 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:59:22.240 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:59:22.712 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:59:23.183 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:59:23.657 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:59:24.129 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:59:24.601 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:59:25.073 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:59:25.546 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:59:26.018 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:59:26.490 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:59:26.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:59:26.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:59:26.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:26.778 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:26.778 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:26.778 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:26.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:26.781 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:26.781 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:26.781 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:26.781 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:59:26.781 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:59:26.781 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:59:26.782 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:59:26.782 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:59:26.782 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:59:26.782 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:59:26.782 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:59:26.782 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4757 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 02:59:31.787 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:59:31.787 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:59:31.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:31.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:31.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:31.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:31.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:31.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:59:31.795 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:31.795 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:59:31.795 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:59:31.798 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:59:31.798 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:59:31.798 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:59:31.798 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:31.798 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:31.798 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:59:31.799 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:59:31.799 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:59:31.799 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:31.800 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:59:31.800 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:59:31.800 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:59:31.801 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:31.801 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:31.801 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:59:31.801 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:59:31.801 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:59:31.801 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:31.802 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:59:31.802 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:59:31.802 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:59:31.802 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:31.802 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:31.802 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:59:31.802 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:59:31.802 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:59:31.803 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.805 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:59:31.805 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:59:31.805 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:59:31.805 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:31.810 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:59:32.285 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:59:32.331 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:59:32.332 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:59:32.332 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:59:32.333 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:59:32.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:59:32.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:59:32.334 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:59:32.335 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:59:32.335 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:59:32.335 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:59:32.335 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:59:32.335 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:59:32.757 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:59:32.808 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:32.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:32.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:32.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:33.229 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 02:59:33.700 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 02:59:33.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:33.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:33.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:33.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:34.174 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 02:59:34.646 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 02:59:34.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:34.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:34.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:34.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:35.119 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 02:59:35.592 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 02:59:35.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:35.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:35.812 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:35.812 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:36.064 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 02:59:36.535 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 02:59:36.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:36.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:36.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:36.813 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:37.008 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 02:59:37.480 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 02:59:37.952 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 02:59:38.423 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 02:59:38.897 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 02:59:39.369 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 02:59:39.841 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 02:59:40.312 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 02:59:40.785 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 02:59:41.258 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 02:59:41.730 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 02:59:42.201 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 02:59:42.674 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 02:59:43.147 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 02:59:43.619 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 02:59:44.090 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 02:59:44.563 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 02:59:45.035 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 02:59:45.507 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 02:59:45.981 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 02:59:46.453 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 02:59:46.925 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 02:59:47.396 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 02:59:47.870 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 02:59:48.342 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 02:59:48.814 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 02:59:49.288 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 02:59:49.760 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 02:59:50.232 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 02:59:50.703 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 02:59:51.173 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 02:59:51.647 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 02:59:52.119 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 02:59:52.591 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 02:59:53.062 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 02:59:53.535 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 02:59:53.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:59:53.824 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:59:53.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:53.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:53.829 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:53.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:53.829 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:53.829 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:53.829 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:53.829 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:59:53.829 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:59:53.830 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 02:59:53.830 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:58.836 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 02:59:58.836 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 02:59:58.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:58.836 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:58.836 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:58.836 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:58.846 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 02:59:58.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:59:58.847 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:58.847 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 02:59:58.847 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 02:59:58.851 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 02:59:58.851 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 02:59:58.852 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:59:58.852 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:58.852 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 02:59:58.853 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 02:59:58.853 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 02:59:58.853 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 02:59:58.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:58.855 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 02:59:58.855 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 02:59:58.855 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:59:58.855 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:58.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 02:59:58.856 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 02:59:58.856 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 02:59:58.856 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 02:59:58.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:58.858 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 02:59:58.858 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 02:59:58.858 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:59:58.858 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 02:59:58.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 02:59:58.858 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 02:59:58.858 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 02:59:58.858 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 02:59:58.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 02:59:58.861 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 02:59:58.861 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 02:59:58.861 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 02:59:58.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 02:59:58.866 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 02:59:59.343 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 02:59:59.386 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 02:59:59.387 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 02:59:59.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 02:59:59.388 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 02:59:59.390 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 02:59:59.390 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 02:59:59.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 02:59:59.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 02:59:59.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 02:59:59.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 02:59:59.391 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 02:59:59.391 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 02:59:59.814 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 02:59:59.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 02:59:59.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 02:59:59.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 02:59:59.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:00.287 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:00:00.759 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:00:00.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:00.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:00.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:00.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:01.232 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:00:01.704 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:00:01.866 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:01.866 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:01.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:01.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:02.175 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:00:02.645 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:00:02.867 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:02.867 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:02.867 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:02.867 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:03.117 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:00:03.589 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:00:03.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:03.868 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:03.868 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:03.869 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:04.060 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:00:04.530 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:00:05.002 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:00:05.475 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:00:05.948 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:00:06.420 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:00:06.891 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:00:07.364 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:00:07.836 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:00:08.308 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:00:08.779 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:00:09.252 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:00:09.725 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:00:10.197 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:00:10.670 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:00:11.143 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:00:11.615 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:00:12.086 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:00:12.559 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:00:13.032 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:00:13.504 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:00:13.975 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:00:14.448 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:00:14.921 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:00:15.393 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:00:15.864 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:00:16.337 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:00:16.810 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:00:17.282 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:00:17.753 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:00:18.226 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:00:18.698 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:00:19.171 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:00:19.644 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:00:20.116 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:00:20.588 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:00:21.059 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:00:21.533 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:00:22.005 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:00:22.477 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:00:22.948 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:00:23.422 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:00:23.894 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:00:24.366 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:00:24.837 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:00:25.310 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:00:25.783 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:00:26.255 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:00:26.726 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:00:27.195 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:00:27.662 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:00:28.133 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:00:28.607 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:00:29.079 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:00:29.551 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:00:30.024 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:00:30.497 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:00:30.969 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:00:31.442 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:00:31.915 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:00:32.387 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:00:32.858 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:00:32.883 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:00:32.883 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:00:32.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:32.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:32.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:32.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:32.889 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:00:32.889 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:00:32.889 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:00:32.889 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:00:32.889 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:00:32.889 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:00:32.889 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:32.889 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7353 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:00:37.894 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:00:37.894 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:00:37.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:00:37.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:00:37.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:00:37.895 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:00:37.902 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:00:37.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:00:37.903 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:00:37.903 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:00:37.903 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:00:37.907 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:00:37.907 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:00:37.907 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:00:37.907 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:00:37.908 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:00:37.908 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:00:37.908 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:00:37.908 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:00:37.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:37.912 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:00:37.912 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:00:37.912 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:00:37.912 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:00:37.912 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:00:37.912 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:00:37.913 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:00:37.913 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:00:37.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:37.916 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:00:37.916 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:00:37.916 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:00:37.916 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:00:37.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:00:37.917 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:00:37.917 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:00:37.917 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:00:37.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.922 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:00:37.923 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:00:37.923 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:00:37.923 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.923 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:00:37.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:00:37.928 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:00:38.405 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:00:38.454 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:00:38.456 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:00:38.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:00:38.457 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:00:38.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:00:38.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:00:38.459 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:00:38.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:00:38.460 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:00:38.460 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:00:38.460 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:00:38.461 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:00:38.877 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:00:38.926 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:38.927 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:38.927 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:38.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:39.348 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:00:39.822 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:00:39.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:39.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:39.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:39.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:40.294 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:00:40.766 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:00:40.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:40.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:40.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:40.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:41.237 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:00:41.711 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:00:41.931 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:41.931 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:41.931 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:41.931 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:42.183 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:00:42.655 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:00:42.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:00:42.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:00:42.932 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:00:42.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:00:43.126 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:00:43.599 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:00:44.072 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:00:44.544 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:00:45.015 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:00:45.488 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:00:45.961 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:00:46.432 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:00:46.904 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:00:47.374 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:00:47.847 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:00:48.320 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:00:48.792 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:00:49.266 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:00:49.738 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:00:50.210 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:00:50.681 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:00:51.155 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:00:51.627 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:00:52.099 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:00:52.570 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:00:53.041 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:00:53.515 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:00:53.987 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:00:54.459 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:00:54.930 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:00:55.403 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:00:55.876 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:00:56.348 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:00:56.820 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:00:57.294 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:00:57.766 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:00:58.239 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:00:58.711 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:00:59.183 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:00:59.654 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:01:00.128 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:01:00.600 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:01:01.072 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:01:01.543 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:01:02.016 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:01:02.488 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:01:02.960 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:01:03.432 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:01:03.905 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:01:04.377 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:01:04.850 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:01:05.323 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:01:05.795 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:01:05.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:01:05.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:01:05.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:05.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:05.946 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:05.946 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:05.947 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:05.947 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:05.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:05.947 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:05.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:05.947 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:05.947 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:01:10.953 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:10.953 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:10.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:10.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:10.954 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:10.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:10.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:10.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:10.964 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:10.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:10.964 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:01:10.969 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:01:10.969 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:01:10.969 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:10.969 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:10.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:10.969 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:01:10.970 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:10.970 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:01:10.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:10.973 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:01:10.974 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:01:10.974 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:10.974 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:10.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:10.974 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:01:10.974 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:10.974 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:01:10.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:10.978 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:01:10.978 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:01:10.978 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:10.978 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:10.978 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:10.978 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:01:10.978 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:10.978 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:01:10.979 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:10.983 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:01:10.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:01:10.983 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:01:10.983 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:01:10.983 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:01:10.983 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.984 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:01:10.984 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:01:10.984 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:01:10.984 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:10.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:10.989 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:01:11.467 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:01:11.521 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:01:11.523 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:01:11.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:01:11.526 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:01:11.541 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:11.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:11.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:11.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:11.545 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:11.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:11.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:11.546 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:11.546 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:11.546 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:11.546 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:01:11.547 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:11.547 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:11.547 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:11.547 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:11.547 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:11.547 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:11.547 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=121 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:16.552 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:16.552 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:16.553 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:16.553 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:16.553 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:16.553 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:16.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:16.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:16.563 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:16.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:16.563 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:01:16.566 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:01:16.566 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:01:16.566 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:16.566 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:16.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:16.566 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:01:16.567 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:16.567 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:01:16.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:16.569 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:01:16.569 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:01:16.569 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:16.569 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:16.569 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:16.569 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:01:16.569 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:16.569 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:01:16.569 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:16.571 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:01:16.571 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:01:16.571 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:16.571 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:16.571 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:16.571 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:01:16.571 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:16.571 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:01:16.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:16.574 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.575 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:01:16.575 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:01:16.575 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:01:16.576 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:16.580 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:01:17.054 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:01:17.106 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:01:17.109 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:01:17.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:01:17.111 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:01:17.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:17.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:17.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:17.125 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:17.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:17.129 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:17.129 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:17.129 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:01:17.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:17.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:17.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:17.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:17.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:17.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:17.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:17.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:17.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:17.131 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:22.130 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:22.130 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:22.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:22.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:22.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:22.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:22.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:22.137 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:22.137 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:22.137 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:22.137 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:01:22.140 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:01:22.140 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:01:22.141 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:22.141 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:22.141 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:22.141 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:01:22.142 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:22.142 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:01:22.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:22.143 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:01:22.144 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:01:22.144 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:22.144 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:22.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:22.144 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:01:22.144 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:22.144 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:01:22.144 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:22.146 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:01:22.146 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:01:22.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:22.146 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:22.146 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:22.146 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:01:22.146 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:22.146 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:01:22.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:01:22.150 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:01:22.150 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:01:22.150 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:22.150 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:22.154 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:01:22.632 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:01:22.675 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:01:22.677 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:01:22.679 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:01:22.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:01:22.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:22.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:22.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:22.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:22.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:22.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:22.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:22.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:22.689 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:22.689 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:22.689 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:01:22.689 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:22.689 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:22.689 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:22.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:22.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:22.690 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=116 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:27.694 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:27.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:27.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:27.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:27.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:27.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:27.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:27.702 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:27.702 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:27.702 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:27.702 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:01:27.705 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:01:27.705 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:01:27.706 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:27.706 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:27.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:27.706 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:01:27.707 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:27.707 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:01:27.707 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:27.709 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:01:27.709 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:01:27.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:27.709 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:27.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:27.709 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:01:27.709 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:27.709 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:01:27.709 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:27.712 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:01:27.712 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:01:27.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:27.712 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:27.712 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:27.712 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:01:27.712 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:27.712 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:01:27.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:27.716 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:01:27.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:01:27.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:01:27.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:01:27.716 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:01:27.716 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:01:27.717 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:01:27.717 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:01:27.717 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:27.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:27.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:27.722 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:01:28.201 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:01:28.239 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:01:28.241 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:01:28.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:01:28.242 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:01:28.244 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:01:28.244 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:01:28.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:01:28.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:01:28.245 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:01:28.245 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:01:28.245 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:01:28.245 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:01:28.673 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:01:28.720 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:28.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:28.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:28.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:29.144 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:01:29.615 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:01:29.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:29.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:29.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:29.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:30.088 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:01:30.561 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:01:30.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:30.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:30.722 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:30.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:31.033 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:01:31.504 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:01:31.723 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:31.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:31.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:31.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:31.977 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:01:32.450 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:01:32.724 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:32.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:32.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:32.726 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:32.922 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:01:33.393 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:01:33.866 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:01:34.339 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:01:34.810 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:01:35.282 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:01:35.755 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:01:36.227 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:01:36.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:01:36.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:01:36.301 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:36.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:36.301 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:36.301 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:36.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:36.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:36.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:36.304 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:01:36.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:36.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:36.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:36.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:36.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:36.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:36.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:36.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:36.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:01:41.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:41.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:41.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:41.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:41.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:41.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:41.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:41.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:41.319 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:41.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:41.319 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:01:41.323 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:01:41.323 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:01:41.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:41.324 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:41.324 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:41.324 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:01:41.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:41.324 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:01:41.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:41.328 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:01:41.328 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:01:41.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:41.329 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:41.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:41.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:01:41.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:41.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:01:41.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:41.333 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:01:41.333 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:01:41.333 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:41.333 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:41.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:41.333 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:01:41.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:41.334 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:01:41.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:01:41.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:01:41.340 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:01:41.340 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:01:41.340 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.341 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:41.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:41.345 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:01:41.823 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:01:41.869 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:01:41.870 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:01:41.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:01:41.872 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:01:41.875 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:01:41.875 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:01:41.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:01:41.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:01:41.875 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:01:41.875 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:01:41.876 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:01:41.876 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:01:42.295 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:01:42.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:42.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:42.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:42.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:42.766 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:01:43.237 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:01:43.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:43.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:43.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:43.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:43.709 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:01:44.182 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:01:44.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:44.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:44.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:44.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:44.654 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:01:45.125 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:01:45.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:45.348 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:45.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:45.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:45.599 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:01:46.071 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:01:46.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:46.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:46.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:46.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:46.543 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:01:47.016 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:01:47.489 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:01:47.961 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:01:48.434 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:01:48.907 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:01:49.379 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:01:49.852 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:01:49.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:01:49.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:49.925 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:49.926 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:49.926 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:49.926 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:01:54.935 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:01:54.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:01:54.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:54.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:54.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:54.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:54.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:01:54.957 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:54.957 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:54.958 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:01:54.958 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:01:54.963 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:01:54.963 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:01:54.963 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:54.963 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:54.964 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:01:54.964 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:01:54.965 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:01:54.965 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:01:54.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:54.967 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:01:54.968 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:01:54.968 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:54.968 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:54.968 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:01:54.968 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:01:54.969 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:01:54.969 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:01:54.969 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:54.972 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:01:54.972 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:01:54.972 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:54.972 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:01:54.972 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:01:54.973 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:01:54.973 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:01:54.973 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:01:54.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:54.977 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:01:54.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:01:54.977 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:01:54.977 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:01:54.977 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:01:54.977 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:01:54.978 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:01:54.978 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:01:54.978 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:01:54.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:01:54.980 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:01:54.983 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:01:55.460 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:01:55.516 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:01:55.518 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:01:55.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:01:55.520 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:01:55.524 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:01:55.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:01:55.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:01:55.525 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:01:55.525 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:01:55.525 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:01:55.525 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:01:55.525 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:01:55.932 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:01:55.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:55.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:55.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:55.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:56.403 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:01:56.874 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:01:56.983 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:56.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:56.983 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:56.984 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:57.348 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:01:57.820 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:01:57.984 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:57.984 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:57.985 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:57.985 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:58.292 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:01:58.763 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:01:58.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:58.986 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:58.986 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:58.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:01:59.236 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:01:59.709 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:01:59.987 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:01:59.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:01:59.987 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:01:59.987 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:00.181 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:02:00.652 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:02:01.125 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:02:01.597 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:02:02.069 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:02:02.540 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:02:03.013 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:02:03.485 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:02:03.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:03.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:03.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:03.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:03.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:03.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:03.563 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:03.563 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:03.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:03.563 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:03.563 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:03.563 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:03.563 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:02:08.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:08.570 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:08.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:08.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:08.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:08.571 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:08.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:08.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:08.581 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:08.581 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:08.581 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:02:08.585 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:02:08.585 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:02:08.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:08.585 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:08.585 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:08.586 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:02:08.586 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:08.586 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:02:08.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:08.590 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:02:08.590 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:02:08.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:08.590 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:08.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:08.590 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:02:08.590 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:08.590 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:02:08.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:08.594 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:02:08.594 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:02:08.594 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:08.594 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:08.595 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:08.595 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:02:08.595 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:08.595 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:02:08.595 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:02:08.601 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:02:08.601 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:02:08.601 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.601 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.602 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:08.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.603 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:08.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.603 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:08.606 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:02:09.081 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:02:09.124 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:02:09.125 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:02:09.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:02:09.127 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:02:09.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:09.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:09.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:02:09.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:02:09.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:02:09.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:02:09.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:02:09.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:02:09.551 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:02:09.604 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:09.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:09.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:09.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:10.023 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:02:10.495 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:02:10.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:10.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:10.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:10.607 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:10.967 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:02:11.440 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:02:11.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:11.608 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:11.608 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:11.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:11.912 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:02:12.384 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:02:12.608 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:12.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:12.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:12.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:12.858 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:02:13.330 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:02:13.609 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:13.609 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:13.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:13.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:13.803 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:02:14.276 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:02:14.748 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:02:15.220 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:02:15.691 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:02:16.165 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:02:16.637 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:02:17.109 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:02:17.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:17.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:17.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:17.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:17.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:17.181 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:17.183 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:17.183 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:17.183 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:17.183 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:02:17.183 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:17.183 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:17.183 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:17.183 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:22.188 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:22.188 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:22.188 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:22.188 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:22.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:22.188 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:22.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:22.195 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:22.195 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:22.196 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:22.196 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:02:22.199 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:02:22.200 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:02:22.200 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:22.200 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:22.201 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:22.201 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:02:22.202 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:22.202 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:02:22.202 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:22.203 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:02:22.203 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:02:22.204 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:22.204 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:22.204 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:22.204 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:02:22.204 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:22.204 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:02:22.204 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:22.206 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:02:22.206 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:02:22.207 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:22.207 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:22.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:22.207 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:02:22.207 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:22.207 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:02:22.207 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.210 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:02:22.210 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:02:22.211 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:02:22.211 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.211 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.212 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:22.215 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:02:22.693 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:02:22.738 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:02:22.740 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:02:22.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:02:22.742 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:02:22.745 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:22.746 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:22.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:02:22.746 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:02:22.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:02:22.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:02:22.747 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:02:22.747 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:02:23.165 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:02:23.214 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:23.214 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:23.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:23.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:23.636 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:02:24.109 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:02:24.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:24.215 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:24.215 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:24.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:24.582 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:02:25.054 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:02:25.215 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:25.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:25.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:25.216 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:25.527 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:02:26.000 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:02:26.217 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:26.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:26.218 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:26.218 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:26.472 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:02:26.943 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:02:27.219 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:27.219 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:27.219 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:27.219 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:27.416 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:02:27.889 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:02:28.360 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:02:28.832 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:02:29.305 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:02:29.777 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:02:30.249 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:02:30.720 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:02:30.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:30.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:30.798 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:30.798 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:30.798 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:30.799 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:30.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:30.803 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:30.803 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:30.803 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:30.803 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:30.803 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:30.803 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:02:30.804 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1856 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:30.804 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1856 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:30.804 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1856 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:30.804 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1856 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:30.804 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1856 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:30.804 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1856 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:35.810 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:35.810 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:35.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:35.810 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:35.810 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:35.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:35.818 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:35.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:35.819 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:35.819 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:35.819 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:02:35.822 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:02:35.823 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:02:35.823 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:35.823 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:35.823 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:35.823 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:02:35.823 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:35.823 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:02:35.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:35.827 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:02:35.827 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:02:35.827 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:35.827 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:35.827 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:35.827 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:02:35.828 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:35.828 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:02:35.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:35.831 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:02:35.832 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:02:35.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:35.832 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:35.832 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:35.832 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:02:35.832 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:35.832 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:02:35.832 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:35.837 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:02:35.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:02:35.837 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.838 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:02:35.839 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:02:35.839 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:02:35.839 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.839 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:35.843 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:02:36.320 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:02:36.370 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:02:36.372 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:02:36.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:02:36.373 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:02:36.374 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:36.374 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:36.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:02:36.374 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:02:36.374 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:02:36.374 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:02:36.374 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:02:36.374 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:02:36.792 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:02:36.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:36.842 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:36.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:36.843 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:37.263 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:02:37.737 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:02:37.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:37.844 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:37.844 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:37.844 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:38.209 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:02:38.681 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:02:38.844 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:38.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:38.854 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:38.854 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:39.152 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:02:39.626 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:02:39.854 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:39.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:39.855 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:39.855 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:40.098 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:02:40.570 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:02:40.855 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:40.855 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:40.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:40.856 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:41.043 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:02:41.515 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:02:41.987 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:02:42.461 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:02:42.933 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:02:43.405 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:02:43.876 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:02:44.350 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:02:44.822 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:02:45.294 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:02:45.765 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:02:46.236 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:02:46.709 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:02:47.181 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:02:47.653 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:02:48.124 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:02:48.597 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:02:49.070 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:02:49.542 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:02:50.016 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:02:50.488 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:02:50.960 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:02:51.431 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:02:51.905 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:02:52.377 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:02:52.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:52.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:52.431 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:52.432 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:52.432 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:52.432 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:52.435 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:52.436 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:52.436 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:52.436 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:02:52.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:52.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:52.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:52.436 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3583 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.436 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3583 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3583 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3583 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3583 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:52.437 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3584 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:02:57.438 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:02:57.438 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:02:57.438 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:57.438 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:57.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:57.438 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:57.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:02:57.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:57.444 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:57.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:02:57.445 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:02:57.447 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:02:57.448 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:02:57.448 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:57.448 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:57.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:02:57.449 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:02:57.450 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:02:57.450 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:02:57.450 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:57.452 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:02:57.452 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:02:57.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:57.453 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:57.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:02:57.453 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:02:57.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:02:57.453 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:02:57.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:57.456 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:02:57.456 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:02:57.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:57.456 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:02:57.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:02:57.456 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:02:57.457 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:02:57.457 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:02:57.457 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.461 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:02:57.461 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:02:57.461 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:02:57.462 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.463 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:02:57.466 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:02:57.944 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:02:57.998 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:02:58.000 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:02:58.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:02:58.001 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:02:58.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:02:58.014 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:02:58.014 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:02:58.015 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:02:58.016 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:02:58.016 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:02:58.016 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:02:58.016 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:02:58.416 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:02:58.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:58.466 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:58.467 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:58.467 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:58.887 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:02:59.360 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:02:59.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:02:59.467 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:02:59.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:02:59.468 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:02:59.833 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:03:00.304 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:03:00.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:00.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:00.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:00.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:00.776 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:03:01.249 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:03:01.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:01.469 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:01.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:01.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:01.721 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:03:02.193 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:03:02.469 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:02.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:02.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:02.470 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:02.664 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:03:03.138 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:03:03.610 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:03:04.083 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:03:04.556 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:03:05.028 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:03:05.501 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:03:05.974 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:03:06.045 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:06.045 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:06.058 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:06.058 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:06.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:06.058 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:06.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:06.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:06.061 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:06.061 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:06.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:06.062 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:06.062 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:03:11.066 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:11.066 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:11.066 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:11.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:11.066 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:11.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:11.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:11.077 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:11.077 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:11.078 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:11.078 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:03:11.083 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:03:11.084 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:03:11.084 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:11.084 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:11.084 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:11.085 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:03:11.085 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:11.085 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:03:11.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:11.089 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:03:11.090 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:03:11.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:11.090 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:11.090 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:11.090 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:03:11.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:11.090 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:03:11.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:11.094 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:03:11.094 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:03:11.094 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:11.094 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:11.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:11.094 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:03:11.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:11.095 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:03:11.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:11.098 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:03:11.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.099 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:03:11.099 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:03:11.099 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:03:11.099 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.101 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:11.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:11.101 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:11.104 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:03:11.582 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:03:11.629 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:03:11.631 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:03:11.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:03:11.633 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:03:11.639 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:11.639 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:11.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:03:11.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:03:11.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:03:11.640 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:03:11.640 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:03:11.640 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:03:12.054 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:03:12.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:12.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:12.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:12.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:12.526 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:03:12.999 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:03:13.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:13.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:13.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:13.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:13.471 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:03:13.943 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:03:14.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:14.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:14.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:14.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:14.416 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:03:14.889 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:03:15.107 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:15.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:15.108 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:15.108 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:15.361 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:03:15.832 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:03:16.108 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:16.108 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:16.109 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:16.109 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:16.306 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:03:16.778 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:03:17.250 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:03:17.723 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:03:18.196 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:03:18.668 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:03:19.139 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:03:19.612 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:03:20.085 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:03:20.556 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:03:21.027 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:03:21.501 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:03:21.973 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:03:22.445 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:03:22.918 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:03:23.391 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:03:23.863 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:03:24.334 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:03:24.807 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:03:25.279 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:03:25.751 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:03:26.222 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:03:26.696 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:03:27.168 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:03:27.640 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:03:27.689 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:27.689 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:27.699 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:27.699 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:27.699 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:27.699 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:27.702 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:27.702 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:27.702 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:27.702 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:27.702 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:03:27.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:27.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:27.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3585 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:32.706 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:32.706 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:32.706 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:32.706 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:32.706 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:32.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:32.713 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:32.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:32.714 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:32.714 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:32.714 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:03:32.718 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:03:32.718 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:03:32.719 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:32.719 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:32.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:32.719 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:03:32.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:32.720 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:03:32.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:32.722 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:03:32.723 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:03:32.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:32.723 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:32.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:32.723 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:03:32.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:32.723 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:03:32.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:32.726 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:03:32.726 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:03:32.726 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:32.726 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:32.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:32.727 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:03:32.727 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:32.727 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:03:32.727 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:32.731 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:03:32.731 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:03:32.731 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.732 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:03:32.732 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:03:32.732 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:03:32.733 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.733 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:32.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:32.737 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:03:33.214 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:03:33.259 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:03:33.259 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:03:33.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:03:33.259 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:03:33.285 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:33.285 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:33.286 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:03:33.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:33.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:33.297 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:33.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:33.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:33.301 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:33.301 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:33.301 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:03:33.301 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:33.301 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:33.301 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:33.301 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:33.301 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:33.301 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:33.301 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:33.301 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:33.301 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:38.304 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:38.304 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:38.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:38.304 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:38.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:38.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:38.311 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:38.312 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:38.313 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:38.313 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:38.313 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:03:38.316 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:03:38.316 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:03:38.316 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:38.316 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:38.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:38.317 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:03:38.317 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:38.317 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:03:38.318 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:38.318 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:03:38.319 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:03:38.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:38.319 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:38.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:38.319 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:03:38.319 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:38.319 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:03:38.319 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:38.321 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:03:38.321 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:03:38.321 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:38.321 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:38.321 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:38.321 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:03:38.321 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:38.321 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:03:38.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:03:38.324 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:03:38.324 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:03:38.324 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.325 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:38.329 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:03:38.806 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:03:38.848 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:03:38.850 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:03:38.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:03:38.853 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:03:38.878 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:38.878 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:38.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:03:38.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:38.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:38.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:38.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:38.897 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:38.897 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:38.897 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:38.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:38.897 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:38.897 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:38.897 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:03:43.903 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:43.903 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:43.903 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:43.903 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:43.903 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:43.903 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:43.906 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:43.906 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:43.906 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:43.906 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:43.906 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:03:43.907 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:03:43.907 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:03:43.908 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:43.908 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:43.908 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:43.908 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:03:43.908 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:43.908 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:03:43.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:43.909 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:03:43.909 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:03:43.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:43.909 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:43.909 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:43.909 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:03:43.909 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:43.909 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:03:43.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:43.910 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:03:43.910 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:03:43.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:43.910 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:43.910 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:43.910 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:03:43.910 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:43.910 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:03:43.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:03:43.912 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:03:43.912 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:03:43.912 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.912 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:43.913 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:43.917 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:03:44.396 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:03:44.440 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:03:44.442 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:03:44.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:03:44.444 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:03:44.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:44.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:44.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:03:44.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:44.489 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:44.489 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:44.489 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:44.491 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:44.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:44.492 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:44.492 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:44.492 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:44.492 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:44.492 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:03:49.493 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:49.493 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:49.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:49.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:49.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:49.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:49.501 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:49.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:49.501 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:49.501 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:49.501 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:03:49.504 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:03:49.504 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:03:49.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:49.505 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:49.505 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:49.505 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:03:49.505 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:49.505 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:03:49.505 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:49.508 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:03:49.508 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:03:49.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:49.509 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:49.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:49.509 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:03:49.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:49.509 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:03:49.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:49.511 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:03:49.512 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:03:49.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:49.512 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:49.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:49.512 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:03:49.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:49.512 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:03:49.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:49.515 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:03:49.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:03:49.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:03:49.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:03:49.515 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:03:49.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:03:49.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:03:49.516 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:03:49.516 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:03:49.516 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:49.521 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:03:49.998 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:03:50.043 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:03:50.046 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:03:50.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:03:50.049 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:03:50.072 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:50.073 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:50.073 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:03:50.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:50.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:50.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:50.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:50.107 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:50.107 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:50.107 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:50.107 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:03:50.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:50.107 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:50.107 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:50.107 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:50.107 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:50.107 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:50.107 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:50.107 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:50.107 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:50.107 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=127 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:55.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:55.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:55.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:55.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:55.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:55.112 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:55.122 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:55.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:55.123 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:55.123 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:03:55.123 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:03:55.125 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:03:55.125 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:03:55.125 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:55.125 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:55.125 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:55.126 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:03:55.126 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:03:55.126 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:03:55.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:55.127 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:03:55.127 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:03:55.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:55.127 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:55.127 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:55.127 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:03:55.127 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:03:55.127 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:03:55.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:55.129 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:03:55.129 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:03:55.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:55.129 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:03:55.129 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:55.129 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:03:55.129 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:03:55.129 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:03:55.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:03:55.131 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:03:55.131 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:03:55.131 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.131 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.132 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:03:55.136 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:03:55.613 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:03:55.655 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:03:55.657 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:03:55.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:03:55.659 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:03:55.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:55.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:55.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:03:55.696 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:03:55.696 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:03:55.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:03:55.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:03:55.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:03:55.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:03:55.700 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:03:55.701 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:03:55.701 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:03:55.701 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:03:55.701 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:03:55.701 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:03:55.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:03:55.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:03:55.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:55.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:55.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:55.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:55.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:03:55.702 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:00.708 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:04:00.708 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:04:00.708 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:00.708 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:00.708 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:00.708 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:00.714 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:00.715 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:00.715 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:00.716 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:00.716 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:04:00.718 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:04:00.719 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:04:00.719 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:00.719 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:00.720 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:00.720 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:04:00.720 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:00.720 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:04:00.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:00.722 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:04:00.722 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:04:00.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:00.723 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:00.723 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:00.723 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:04:00.723 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:00.723 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:04:00.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:00.725 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:04:00.725 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:04:00.725 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:00.725 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:00.725 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:00.725 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:04:00.725 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:00.725 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:04:00.725 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.728 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:04:00.728 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:04:00.728 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:04:00.728 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:00.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:00.733 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:04:01.211 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:04:01.254 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:04:01.256 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:04:01.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:04:01.259 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:04:01.284 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:04:01.284 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:04:01.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:04:01.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:04:01.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:04:01.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:04:01.305 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:01.305 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:01.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:01.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:01.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:01.306 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:04:01.306 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:04:01.306 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:04:01.307 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:06.313 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:04:06.313 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:04:06.313 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:06.313 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:06.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:06.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:06.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:06.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:06.322 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:06.322 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:06.322 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:04:06.325 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:04:06.326 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:04:06.326 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:06.326 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:06.326 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:06.327 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:04:06.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:06.327 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:04:06.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:06.329 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:04:06.330 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:04:06.330 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:06.330 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:06.330 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:06.330 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:04:06.330 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:06.330 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:04:06.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:06.333 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:04:06.333 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:04:06.333 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:06.333 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:06.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:06.333 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:04:06.334 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:06.334 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:04:06.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:04:06.339 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:04:06.339 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:04:06.339 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.339 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:06.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:06.344 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:04:06.820 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:04:06.874 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:04:06.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:04:06.875 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:04:06.876 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:04:06.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:04:06.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:04:06.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:04:06.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:04:06.881 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:04:06.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:04:06.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:04:06.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:04:07.292 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:04:07.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:07.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:07.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:07.346 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:07.763 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:04:08.237 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:04:08.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:08.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:08.345 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:08.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:08.709 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:04:09.181 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:04:09.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:09.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:09.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:09.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:09.655 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:04:10.127 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:04:10.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:10.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:10.348 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:10.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:10.599 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:04:11.070 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:04:11.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:11.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:11.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:11.350 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:11.544 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:04:12.016 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:04:12.488 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:04:12.962 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:04:13.433 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:04:13.905 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:04:14.376 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:04:14.850 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:04:15.322 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:04:15.794 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:04:16.265 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:04:16.739 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:04:17.211 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:04:17.683 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:04:18.157 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:04:18.629 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:04:19.101 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:04:19.572 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:04:20.046 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:04:20.518 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:04:20.990 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:04:21.464 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:04:21.936 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:04:22.408 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:04:22.879 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:04:23.352 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:04:23.825 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:04:24.297 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:04:24.768 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:04:25.241 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:04:25.714 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:04:26.185 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:04:26.657 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:04:27.130 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:04:27.602 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:04:28.074 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:04:28.545 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:04:29.017 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:04:29.491 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:04:29.962 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:04:30.434 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:04:30.907 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:04:31.380 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:04:31.852 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:04:32.323 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:04:32.796 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:04:33.268 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:04:33.740 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:04:34.212 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:04:34.685 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:04:35.157 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:04:35.629 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:04:36.100 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:04:36.571 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:04:37.044 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:04:37.517 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:04:37.989 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:04:38.460 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:04:38.933 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:04:39.405 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:04:39.877 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:04:40.348 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:04:40.360 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:04:40.360 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:04:40.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:40.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:40.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:40.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:40.369 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:40.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:40.370 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:04:40.370 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:04:40.370 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:04:40.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:40.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7350 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.371 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.372 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.372 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.372 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:40.372 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=7351 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:04:45.370 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:04:45.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:04:45.371 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:45.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:45.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:45.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:45.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:45.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:45.380 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:45.380 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:45.380 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:04:45.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:04:45.382 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:04:45.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:45.383 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:45.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:45.383 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:04:45.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:45.383 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:04:45.383 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:45.385 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:04:45.385 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:04:45.385 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:45.385 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:45.385 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:45.385 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:04:45.385 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:45.385 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:04:45.386 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:45.388 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:04:45.388 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:04:45.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:45.388 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:45.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:45.388 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:04:45.388 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:45.388 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:04:45.388 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:45.391 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:04:45.391 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:04:45.391 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:04:45.391 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:04:45.391 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:04:45.392 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:04:45.392 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:04:45.392 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.392 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:45.397 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:04:45.873 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:04:45.915 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:04:45.917 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:04:45.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:04:45.919 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:04:46.343 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:04:46.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:46.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:46.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:46.396 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:46.816 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:04:47.288 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:04:47.396 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:47.396 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:47.396 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:47.397 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:47.761 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:04:48.234 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:04:48.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:48.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:48.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:48.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:48.706 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:04:48.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:04:48.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:48.936 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:48.936 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:48.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:48.939 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:48.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:48.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:48.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:48.939 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:04:48.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:04:48.939 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:04:53.943 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:04:53.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:04:53.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:53.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:53.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:53.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:53.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:04:53.953 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:53.953 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:53.953 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:04:53.953 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:04:53.956 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:04:53.956 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:04:53.957 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:53.957 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:53.957 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:04:53.957 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:04:53.957 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:04:53.958 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:04:53.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:53.959 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:04:53.959 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:04:53.959 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:53.959 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:53.959 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:04:53.959 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:04:53.959 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:04:53.959 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:04:53.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:53.961 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:04:53.961 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:04:53.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:53.961 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:04:53.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:04:53.961 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:04:53.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:04:53.961 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:04:53.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:04:53.964 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:04:53.964 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:04:53.964 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:04:53.969 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:04:54.445 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:04:54.487 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:04:54.488 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:04:54.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:04:54.489 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:04:54.917 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:04:54.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:54.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:54.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:54.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:55.391 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:04:55.863 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:04:55.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:55.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:55.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:55.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:56.335 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:04:56.810 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:04:56.969 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:56.969 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:56.970 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:56.970 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:57.281 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:04:57.753 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:04:57.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:57.970 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:57.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:57.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:58.227 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:04:58.700 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:04:58.972 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:04:58.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:04:58.972 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:04:58.972 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:04:59.171 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:04:59.651 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:05:00.123 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:05:00.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:00.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:00.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:00.501 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:00.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:00.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:00.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:00.502 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:00.502 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:00.502 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:00.502 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:05:00.502 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1410 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:00.502 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1410 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:00.502 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1410 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:00.502 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1410 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:05.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:05.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:05.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:05.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:05.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:05.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:05.522 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:05.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:05.524 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:05.524 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:05.524 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:05:05.528 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:05:05.528 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:05:05.528 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:05.529 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:05.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:05.529 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:05:05.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:05.530 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:05:05.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:05.531 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:05:05.531 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:05:05.531 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:05.532 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:05.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:05.532 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:05:05.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:05.532 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:05:05.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:05.534 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:05:05.534 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:05:05.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:05.534 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:05.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:05.534 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:05:05.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:05.534 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:05:05.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:05:05.537 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:05:05.537 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:05:05.537 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:05.542 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:05:06.019 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:05:06.064 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:05:06.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:06.067 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:05:06.071 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:05:06.490 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:05:06.540 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:06.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:06.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:06.541 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:06.962 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:05:07.434 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:05:07.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:07.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:07.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:07.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:07.909 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:05:08.381 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:05:08.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:08.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:08.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:08.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:08.856 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:05:09.328 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:05:09.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:09.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:09.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:09.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:09.802 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:05:10.274 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:05:10.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:10.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:10.746 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:05:11.222 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:05:11.694 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:05:12.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:12.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:12.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:12.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:12.086 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:12.086 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:12.086 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:12.086 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:12.086 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:12.086 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:12.086 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:05:17.094 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:17.094 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:17.094 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:17.094 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:17.094 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:17.094 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:17.104 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:17.105 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:17.105 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:17.106 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:17.106 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:05:17.108 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:05:17.109 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:05:17.109 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:17.109 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:17.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:17.110 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:05:17.110 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:17.111 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:05:17.111 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:17.112 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:05:17.112 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:05:17.112 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:17.112 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:17.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:17.113 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:05:17.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:17.113 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:05:17.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:17.116 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:05:17.116 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:05:17.116 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:17.116 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:17.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:17.116 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:05:17.116 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:17.116 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:05:17.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:17.120 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:05:17.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:05:17.120 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:05:17.120 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:05:17.120 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:05:17.120 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:05:17.121 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:05:17.121 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:05:17.121 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.121 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:17.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.123 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:17.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:17.126 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:05:17.601 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:05:17.654 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:05:17.656 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:05:17.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:17.659 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:05:18.073 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:05:18.124 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:18.125 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:18.125 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:18.126 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:18.549 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:05:19.021 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:05:19.125 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:19.126 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:19.127 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:19.127 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:19.496 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:05:19.968 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:05:20.127 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:20.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:20.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:20.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:20.442 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:05:20.914 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:05:21.129 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:21.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:21.129 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:21.129 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:21.386 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:05:21.860 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:05:22.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:22.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:22.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:22.131 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:22.332 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:05:22.804 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:05:23.278 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:05:23.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:23.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:23.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:23.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:23.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:23.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:23.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:23.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:23.675 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:05:23.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:23.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:28.681 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:28.681 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:28.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:28.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:28.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:28.681 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:28.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:28.690 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:28.690 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:28.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:28.691 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:05:28.694 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:05:28.694 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:05:28.694 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:28.694 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:28.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:28.695 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:05:28.695 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:28.696 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:05:28.696 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:28.698 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:05:28.698 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:05:28.699 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:28.699 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:28.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:28.699 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:05:28.699 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:28.699 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:05:28.700 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:28.702 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:05:28.702 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:05:28.702 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:28.702 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:28.702 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:28.702 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:05:28.702 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:28.702 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:05:28.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.707 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:05:28.708 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:05:28.708 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:05:28.708 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:28.713 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:05:29.190 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:05:29.236 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:05:29.238 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:05:29.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:29.241 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:05:29.662 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:05:29.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:29.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:29.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:29.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:30.136 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:05:30.608 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:05:30.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:30.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:30.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:30.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:31.080 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:05:31.555 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:05:31.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:31.715 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:31.715 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:31.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:32.027 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:05:32.501 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:05:32.716 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:32.716 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:32.716 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:32.716 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:32.973 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:05:33.270 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:33.447 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:05:33.717 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:33.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:33.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:33.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:33.922 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:05:34.394 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:05:34.869 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:05:35.341 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:05:35.816 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:05:36.288 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:05:36.763 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:05:37.235 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:05:37.278 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:37.278 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:37.278 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:37.278 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:37.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:37.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:37.279 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:37.279 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:37.279 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:37.279 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:37.279 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:05:42.285 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:42.285 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:42.285 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:42.285 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:42.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:42.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:42.292 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:42.293 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:42.294 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:42.294 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:42.294 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:05:42.299 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:05:42.300 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:05:42.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:42.300 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:42.300 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:42.300 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:05:42.300 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:42.301 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:05:42.301 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:42.304 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:05:42.304 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:05:42.304 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:42.304 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:42.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:42.305 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:05:42.305 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:42.305 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:05:42.305 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:42.308 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:05:42.308 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:05:42.308 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:42.308 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:42.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:42.309 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:05:42.309 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:42.309 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:05:42.309 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:42.313 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:05:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:05:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:05:42.313 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.314 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:05:42.314 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:05:42.314 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:05:42.315 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.315 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.316 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:42.319 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:05:42.796 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:05:42.844 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:05:42.846 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:05:42.846 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:42.847 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:05:43.268 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:05:43.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:43.319 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:43.320 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:43.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:43.744 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:05:44.216 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:05:44.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:44.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:44.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:44.321 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:44.691 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:05:45.163 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:05:45.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:45.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:45.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:45.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:45.637 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:05:46.109 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:05:46.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:46.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:46.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:46.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:46.581 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:05:46.859 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:46.859 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:46.859 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:46.859 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:46.860 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:46.860 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:46.860 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:46.860 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:46.860 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:46.860 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:46.860 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:05:51.867 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:51.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:51.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:51.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:51.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:51.867 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:51.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:51.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:51.878 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:51.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:51.878 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:05:51.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:05:51.883 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:05:51.884 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:51.884 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:51.884 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:51.885 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:05:51.885 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:51.885 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:05:51.886 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:51.887 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:05:51.887 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:05:51.887 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:51.887 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:51.888 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:51.888 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:05:51.888 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:51.888 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:05:51.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:51.891 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:05:51.891 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:05:51.891 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:51.891 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:51.891 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:51.891 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:05:51.891 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:51.891 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:05:51.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:51.894 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:05:51.894 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:05:51.894 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:05:51.894 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:05:51.894 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:05:51.895 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:05:51.895 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:05:51.895 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:05:51.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:51.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:51.900 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:05:52.376 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:05:52.411 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:05:52.412 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:05:52.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:52.414 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:05:52.423 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:52.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:52.424 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:52.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:52.428 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:52.428 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:52.428 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:52.428 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:52.428 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:52.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:52.429 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:05:52.429 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:52.429 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:52.429 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:52.429 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:52.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:52.430 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:57.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:57.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:57.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:57.431 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:57.431 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:57.431 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:57.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:57.437 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:57.437 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:57.438 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:05:57.438 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:05:57.441 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:05:57.441 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:05:57.441 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:57.441 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:57.441 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:57.441 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:05:57.442 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:05:57.442 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:05:57.442 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:57.444 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:05:57.444 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:05:57.444 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:57.445 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:57.445 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:57.445 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:05:57.445 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:05:57.445 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:05:57.445 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:57.447 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:05:57.447 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:05:57.447 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:57.447 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:05:57.447 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:57.447 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:05:57.447 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:05:57.447 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:05:57.447 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:57.449 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:05:57.450 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:05:57.450 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:05:57.450 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.450 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.451 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:05:57.455 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:05:57.927 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:05:57.976 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:05:57.977 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:05:57.980 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:05:57.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:57.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:05:57.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:05:57.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:05:57.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:05:57.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:05:58.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:05:58.001 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:05:58.001 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:05:58.001 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:05:58.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:05:58.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:05:58.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:05:58.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:58.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:58.002 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:58.002 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:58.002 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:05:58.002 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=120 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.004 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:03.004 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:03.004 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:03.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:03.004 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:03.004 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:03.013 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:03.015 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:03.015 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:03.015 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:03.015 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:06:03.019 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:06:03.020 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:06:03.020 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:03.020 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:03.021 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:03.021 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:06:03.022 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:03.022 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:06:03.022 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:03.024 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:06:03.024 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:06:03.024 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:03.024 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:03.025 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:03.025 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:06:03.025 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:03.025 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:06:03.025 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:03.027 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:06:03.028 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:06:03.028 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:03.028 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:03.028 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:03.028 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:06:03.028 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:03.028 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:06:03.028 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:03.031 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:06:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:06:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:06:03.031 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:06:03.031 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:06:03.032 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:06:03.032 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:06:03.032 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.032 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:03.033 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:03.037 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:06:03.514 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:06:03.559 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:06:03.562 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:06:03.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:03.564 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:06:03.580 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:03.580 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:03.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:03.581 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:03.584 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:03.585 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:03.585 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:03.585 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:06:03.585 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:03.586 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:03.586 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.586 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:03.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:08.588 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:08.588 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:08.588 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:08.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:08.588 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:08.588 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:08.592 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:08.592 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:08.592 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:08.593 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:08.593 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:06:08.595 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:06:08.595 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:06:08.595 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:08.596 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:08.596 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:08.596 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:06:08.597 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:08.597 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:06:08.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:08.598 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:06:08.598 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:06:08.599 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:08.599 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:08.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:08.599 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:06:08.599 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:08.599 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:06:08.599 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:08.601 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:06:08.602 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:06:08.602 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:08.602 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:08.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:08.602 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:06:08.602 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:08.602 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:06:08.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:06:08.606 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:06:08.607 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:06:08.607 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:06:08.607 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.607 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:08.612 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:06:09.088 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:06:09.141 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:06:09.142 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:06:09.143 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:06:09.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:09.150 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:09.150 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:09.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:06:09.150 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:09.150 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:06:09.150 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:06:09.150 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:06:09.150 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:06:09.560 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:06:09.610 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:09.611 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:09.611 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:09.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:10.032 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:06:10.505 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:06:10.612 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:10.612 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:10.612 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:10.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:10.977 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:06:11.449 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:06:11.613 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:11.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:11.614 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:11.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:11.920 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:06:12.204 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:06:12.204 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:06:12.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:12.205 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:12.250 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:12.250 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:12.250 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:06:12.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:12.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:12.257 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:12.257 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:12.257 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:12.257 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:12.257 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:12.257 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:12.257 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:06:17.267 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:17.267 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:17.268 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:17.268 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:17.268 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:17.268 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:17.275 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:17.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:17.276 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:17.276 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:17.276 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:06:17.278 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:06:17.279 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:06:17.279 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:17.279 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:17.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:17.279 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:06:17.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:17.280 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:06:17.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:17.281 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:06:17.281 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:06:17.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:17.281 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:17.281 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:17.281 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:06:17.281 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:17.281 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:06:17.281 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:17.283 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:06:17.283 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:06:17.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:17.283 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:17.283 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:17.283 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:06:17.283 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:17.283 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:06:17.283 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:06:17.285 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:06:17.285 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:06:17.285 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:17.290 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:06:17.767 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:06:17.804 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:06:17.804 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:06:17.806 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:06:17.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:17.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:17.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:17.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:06:17.812 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:17.812 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:06:17.812 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:06:17.812 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:06:17.812 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:06:18.239 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:06:18.288 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:18.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:18.288 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:18.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:18.711 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:06:19.181 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:06:19.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:19.289 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:19.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:19.290 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:19.655 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:06:20.127 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:06:20.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:20.290 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:20.291 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:20.291 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:20.600 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:06:20.883 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:06:20.883 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:06:20.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:20.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:21.072 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:06:21.291 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:21.291 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:21.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:21.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:21.545 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:06:21.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:21.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:21.557 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:06:21.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:21.564 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:21.564 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:21.564 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:21.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:21.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:21.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:21.567 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:21.567 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:21.567 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:06:21.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:21.567 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:26.570 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:26.570 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:26.570 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:26.570 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:26.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:26.570 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:26.579 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:26.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:26.580 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:26.580 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:26.580 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:06:26.583 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:06:26.583 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:06:26.584 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:26.584 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:26.584 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:26.584 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:06:26.585 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:26.585 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:06:26.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:26.587 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:06:26.587 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:06:26.587 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:26.587 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:26.588 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:26.588 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:06:26.588 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:26.588 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:06:26.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:26.591 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:06:26.591 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:06:26.591 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:26.591 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:26.591 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:26.591 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:06:26.592 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:26.592 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:06:26.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:26.598 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:06:26.599 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:06:26.599 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:06:26.599 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.599 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:26.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:26.604 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:06:27.081 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:06:27.130 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:06:27.133 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:27.134 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:06:27.137 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:06:27.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:27.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:27.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:06:27.146 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:27.146 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:06:27.146 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:06:27.146 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:06:27.146 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:06:27.553 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:06:27.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:27.603 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:27.604 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:27.608 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:28.024 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:06:28.498 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:06:28.603 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:28.604 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:28.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:28.609 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:28.970 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:06:29.442 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:06:29.605 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:29.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:29.605 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:29.611 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:29.915 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:06:30.196 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:06:30.196 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:06:30.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:30.197 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:30.388 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:06:30.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:30.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:30.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:30.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:30.860 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:06:31.333 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:06:31.607 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:31.607 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:31.607 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:31.612 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:31.806 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:06:32.277 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:06:32.749 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:06:33.222 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:06:33.694 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:06:34.165 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:06:34.637 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:06:35.110 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:06:35.199 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:35.199 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:35.199 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:06:35.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:35.216 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:35.216 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:35.216 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:35.217 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:35.218 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:35.219 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:35.219 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:35.219 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:06:35.219 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:35.219 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:35.219 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:35.219 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:35.219 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:35.219 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:35.219 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:35.219 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:35.219 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:40.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:40.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:40.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:40.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:40.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:40.224 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:40.231 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:40.232 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:40.233 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:40.233 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:40.233 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:06:40.237 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:06:40.238 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:06:40.238 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:40.238 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:40.239 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:40.239 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:06:40.240 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:40.240 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:06:40.241 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:40.243 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:06:40.243 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:06:40.244 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:40.244 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:40.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:40.245 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:06:40.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:40.245 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:06:40.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:40.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:06:40.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:06:40.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:40.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:40.249 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:40.249 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:06:40.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:40.249 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:06:40.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:06:40.256 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:06:40.256 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:06:40.256 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:40.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.258 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:40.258 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:40.261 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:06:40.739 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:06:40.791 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:06:40.794 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:40.794 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:06:40.798 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:06:40.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:40.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:40.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:06:40.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:40.810 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:06:40.810 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:06:40.810 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:06:40.810 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:06:41.211 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:06:41.259 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:41.259 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:41.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:41.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:41.682 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:06:42.156 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:06:42.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:42.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:42.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:42.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:42.628 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:06:43.100 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:06:43.261 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:43.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:43.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:43.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:43.571 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:06:43.854 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:06:43.855 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:06:43.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:43.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:44.045 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:06:44.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:44.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:44.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:44.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:44.517 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:06:44.988 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:06:45.264 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:45.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:45.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:45.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:45.460 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:06:45.933 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:06:46.405 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:06:46.877 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:06:47.348 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:06:47.822 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:06:48.294 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:06:48.765 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:06:48.857 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:48.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:48.858 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:06:48.858 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:48.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:48.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:48.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:48.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:48.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:48.877 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:48.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:48.878 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:06:48.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:48.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:48.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:48.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:48.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:48.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:48.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:48.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:48.878 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:06:53.881 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:06:53.881 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:06:53.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:53.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:53.881 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:53.881 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:53.888 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:06:53.889 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:53.890 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:53.890 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:06:53.890 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:06:53.894 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:06:53.895 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:06:53.895 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:53.895 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:53.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:06:53.895 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:06:53.896 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:06:53.896 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:06:53.896 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:53.901 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:06:53.901 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:06:53.901 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:53.901 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:53.902 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:06:53.902 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:06:53.902 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:06:53.902 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:06:53.902 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:53.907 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:06:53.907 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:06:53.908 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:53.908 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:06:53.908 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:06:53.908 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:06:53.908 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:06:53.908 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:06:53.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.915 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:06:53.916 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:06:53.916 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:06:53.916 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.916 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.917 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:06:53.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:06:53.921 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:06:54.396 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:06:54.448 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:06:54.450 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:06:54.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:06:54.452 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:06:54.455 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:06:54.455 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:06:54.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:06:54.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:54.456 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:06:54.456 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:06:54.456 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:06:54.456 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:06:54.868 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:06:54.919 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:54.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:54.921 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:54.922 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:55.339 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:06:55.810 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:06:55.920 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:55.920 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:55.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:55.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:56.283 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:06:56.756 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:06:56.921 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:56.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:56.923 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:56.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:57.228 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:06:57.511 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:06:57.511 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:06:57.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:57.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:06:57.699 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:06:57.923 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:57.923 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:57.924 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:57.924 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:58.172 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:06:58.644 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:06:58.924 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:06:58.924 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:06:58.925 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:06:58.925 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:06:59.117 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:06:59.588 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:07:00.061 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:07:00.532 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:07:01.004 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:07:01.476 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:07:01.949 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:07:02.422 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:07:02.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:02.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:02.514 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:07:02.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:02.530 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:02.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:02.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:02.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:02.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:02.534 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:02.534 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:02.534 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:07:02.534 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:02.534 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:02.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:02.534 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:02.534 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:02.534 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:02.534 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:02.534 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:02.534 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1862 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:07.536 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:07.536 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:07.536 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:07.537 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:07.543 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:07.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:07.543 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:07.543 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:07.544 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:07:07.547 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:07:07.547 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:07:07.547 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:07.547 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:07.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:07.548 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:07:07.548 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:07.548 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:07:07.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:07.551 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:07:07.551 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:07:07.551 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:07.551 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:07.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:07.551 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:07:07.552 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:07.552 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:07:07.552 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:07.554 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:07:07.554 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:07:07.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:07.554 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:07.554 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:07.554 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:07:07.554 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:07.554 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:07:07.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:07:07.558 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:07:07.558 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:07:07.558 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:07.559 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:07.563 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:07:08.038 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:07:08.082 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:07:08.085 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:07:08.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:08.087 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:07:08.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:08.092 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:08.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:07:08.092 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:08.092 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:07:08.092 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:07:08.093 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:07:08.093 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:07:08.128 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:07:08.128 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:07:08.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:08.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:08.508 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:07:08.560 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:08.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:08.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:08.561 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:08.981 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:07:09.452 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:07:09.562 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:09.562 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:09.562 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:09.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:09.924 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:07:10.397 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:07:10.563 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:10.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:10.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:10.563 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:10.869 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:07:11.341 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:07:11.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:11.565 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:11.565 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:11.565 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:11.813 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:07:12.286 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:07:12.565 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:12.566 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:12.566 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:12.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:12.758 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:07:13.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:13.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:13.130 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:07:13.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:13.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:13.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:13.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:13.136 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:13.136 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:13.136 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:13.136 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:13.136 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:07:13.136 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:13.136 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:18.143 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:18.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:18.143 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:18.143 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:18.143 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:18.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:18.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:18.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:18.152 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:18.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:18.153 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:07:18.155 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:07:18.155 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:07:18.156 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:18.156 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:18.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:18.156 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:07:18.156 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:18.156 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:07:18.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:18.163 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:07:18.163 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:07:18.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:18.163 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:18.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:18.164 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:07:18.164 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:18.164 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:07:18.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:18.168 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:07:18.168 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:07:18.168 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:18.168 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:18.169 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:18.169 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:07:18.169 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:18.169 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:07:18.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:18.175 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:07:18.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:07:18.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:07:18.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:07:18.175 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:18.176 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.177 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:07:18.177 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:07:18.177 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:07:18.177 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:07:18.177 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.177 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.177 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.179 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:18.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.179 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:18.179 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:18.182 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:07:18.657 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:07:18.706 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:07:18.709 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:07:18.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:18.711 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:07:18.718 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:18.718 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:18.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:07:18.720 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:18.720 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:07:18.720 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:07:18.720 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:07:18.720 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:07:19.129 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:07:19.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:19.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:19.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:19.183 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:19.600 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:07:20.073 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:07:20.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:20.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:20.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:20.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:20.546 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:07:21.018 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:07:21.182 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:21.182 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:21.182 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:21.184 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:21.489 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:07:21.772 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:07:21.772 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:07:21.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:21.773 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:21.962 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:07:22.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:22.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:22.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:22.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:22.434 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:07:22.906 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:07:23.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:23.185 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:23.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:23.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:23.378 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:07:23.774 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:23.774 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:23.774 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:07:23.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:23.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:23.786 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:23.786 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:23.786 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:07:28.793 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:28.793 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:28.793 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:28.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:28.793 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:28.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:28.796 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:28.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:28.797 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:28.797 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:28.797 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:07:28.799 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:07:28.800 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:07:28.800 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:28.800 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:28.800 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:28.800 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:07:28.801 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:28.801 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:07:28.801 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:28.802 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:07:28.802 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:07:28.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:28.802 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:28.802 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:28.802 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:07:28.802 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:28.802 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:07:28.803 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:28.804 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:07:28.804 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:07:28.804 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:28.804 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:28.804 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:28.804 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:07:28.804 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:28.804 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:07:28.805 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:07:28.807 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:07:28.807 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:07:28.807 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:07:28.807 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:28.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:28.812 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:07:29.288 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:07:29.333 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:07:29.336 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:07:29.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:29.338 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:07:29.344 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:29.344 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:29.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:07:29.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:29.344 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:07:29.344 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:07:29.344 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:07:29.344 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:07:29.760 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:07:29.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:29.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:29.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:29.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:30.232 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:07:30.705 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:07:30.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:30.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:30.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:30.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:31.177 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:07:31.649 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:07:31.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:31.811 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:31.811 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:31.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:32.120 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:07:32.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:32.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:32.441 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:32.441 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:32.441 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:32.441 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:32.442 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:32.442 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:32.442 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:32.442 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:32.442 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:32.442 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:32.442 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:07:32.442 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:32.442 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:32.442 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:32.442 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:32.442 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:32.442 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:37.447 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:37.447 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:37.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:37.448 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:37.448 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:37.448 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:37.455 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:37.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:37.457 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:37.457 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:37.457 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:07:37.462 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:07:37.462 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:07:37.462 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:37.462 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:37.462 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:37.462 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:07:37.463 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:37.463 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:07:37.463 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:37.467 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:07:37.467 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:07:37.467 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:37.467 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:37.467 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:37.468 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:07:37.468 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:37.468 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:07:37.468 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:37.472 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:07:37.472 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:07:37.472 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:37.472 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:37.472 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:37.472 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:07:37.472 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:37.472 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:07:37.473 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:37.478 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:07:37.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:07:37.478 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:07:37.478 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:07:37.478 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:07:37.478 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.479 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:07:37.479 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:07:37.479 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:07:37.480 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.480 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:37.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:37.484 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:07:37.962 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:07:38.009 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:07:38.012 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:07:38.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:38.014 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:07:38.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:38.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:38.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:07:38.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:38.022 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:07:38.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:07:38.022 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:07:38.022 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:07:38.433 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:07:38.483 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:38.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:38.484 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:38.484 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:38.905 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:07:39.378 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:07:39.484 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:39.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:39.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:39.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:39.851 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:07:40.324 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:07:40.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:40.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:40.486 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:40.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:40.794 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:07:41.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:41.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:41.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:41.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:41.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:41.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:41.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:41.116 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:41.116 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:41.116 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:41.116 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:41.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:41.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:41.116 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:07:41.116 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:41.116 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:41.116 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:41.116 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:41.116 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:41.116 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=786 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:46.121 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:46.121 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:46.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:46.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:46.121 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:46.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:46.130 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:46.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:46.132 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:46.132 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:46.132 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:07:46.137 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:07:46.138 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:07:46.138 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:46.138 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:46.139 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:46.139 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:07:46.139 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:46.140 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:07:46.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:46.141 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:07:46.141 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:07:46.141 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:46.141 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:46.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:46.142 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:07:46.142 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:46.142 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:07:46.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:46.144 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:07:46.144 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:07:46.145 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:46.145 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:46.145 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:46.145 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:07:46.145 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:46.145 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:07:46.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.148 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:07:46.149 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:07:46.149 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:07:46.149 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:46.149 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:46.153 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:07:46.631 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:07:46.674 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:07:46.676 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:07:46.678 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:07:46.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:46.685 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:46.685 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:46.685 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:07:46.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:46.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:07:46.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:07:46.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:07:46.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:07:46.947 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:46.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:46.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:46.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:46.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:46.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:46.955 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:46.955 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:46.955 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:46.955 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:46.955 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:46.955 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:46.955 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:07:46.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:46.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:46.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:46.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:46.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:46.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:46.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:51.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:51.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:51.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:51.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:51.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:51.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:51.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:51.971 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:51.971 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:51.972 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:51.972 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:07:51.977 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:07:51.977 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:07:51.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:51.978 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:51.978 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:51.979 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:07:51.980 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:51.980 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:07:51.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:51.982 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:07:51.982 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:07:51.983 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:51.983 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:51.983 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:51.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:07:51.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:51.984 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:07:51.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:51.986 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:07:51.987 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:07:51.987 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:51.987 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:51.987 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:51.987 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:07:51.988 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:51.988 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:07:51.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:51.991 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:07:51.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:07:51.991 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:07:51.991 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:07:51.991 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:07:51.991 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:07:51.992 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:07:51.992 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:07:51.992 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:51.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:51.997 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:07:52.473 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:07:52.519 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:07:52.521 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:07:52.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:52.524 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:07:52.530 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:52.530 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:52.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:07:52.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:52.531 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:07:52.531 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:07:52.531 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:07:52.531 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:07:52.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:52.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:52.749 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:52.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:52.750 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:52.750 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:52.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:52.752 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:52.752 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:52.752 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:07:52.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:52.752 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:52.752 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:52.752 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:52.752 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:52.752 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:52.752 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:52.752 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:52.752 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=164 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:07:57.756 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:07:57.756 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:07:57.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:57.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:57.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:57.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:57.764 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:07:57.765 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:57.765 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:57.765 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:07:57.765 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:07:57.768 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:07:57.768 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:07:57.768 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:57.768 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:57.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:07:57.769 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:07:57.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:07:57.769 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:07:57.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:57.771 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:07:57.771 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:07:57.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:57.771 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:57.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:07:57.771 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:07:57.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:07:57.771 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:07:57.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:57.773 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:07:57.773 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:07:57.773 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:57.773 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:07:57.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:07:57.773 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:07:57.774 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:07:57.774 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:07:57.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.776 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:07:57.777 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:07:57.777 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:07:57.777 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:07:57.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:07:57.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:07:57.781 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:07:58.257 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:07:58.306 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:07:58.308 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:07:58.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:07:58.311 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:07:58.320 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:07:58.320 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:07:58.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:07:58.321 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:07:58.321 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:07:58.321 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:07:58.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:07:58.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:07:58.729 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:07:58.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:58.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:58.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:58.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:07:59.200 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:07:59.674 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:07:59.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:07:59.781 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:07:59.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:07:59.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:00.146 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:08:00.619 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:08:00.781 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:00.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:00.783 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:00.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:01.089 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:08:01.560 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:08:01.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:01.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:01.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:01.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:02.033 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:08:02.506 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:08:02.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:02.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:02.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:02.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:02.978 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:08:03.451 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:08:03.923 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:08:04.396 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:08:04.869 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:08:05.341 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:08:05.813 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:08:06.284 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:08:06.757 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:08:07.102 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:08:07.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:08:07.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:07.110 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:07.110 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:07.110 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:08:12.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:12.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:12.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:12.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:12.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:12.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:12.124 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:12.125 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:12.125 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:12.125 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:12.125 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:08:12.127 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:08:12.128 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:08:12.128 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:12.128 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:12.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:12.129 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:08:12.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:12.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:08:12.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:12.130 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:08:12.130 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:08:12.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:12.130 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:12.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:12.130 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:08:12.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:12.130 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:08:12.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:12.132 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:08:12.132 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:08:12.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:12.132 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:12.132 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:12.133 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:08:12.133 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:12.133 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:08:12.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.135 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:08:12.135 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:08:12.135 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:08:12.136 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.136 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:12.140 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:08:12.618 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:08:12.661 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:08:12.663 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:08:12.666 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:08:12.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:08:12.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:08:12.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:08:12.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:08:12.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:08:12.674 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:08:12.674 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:08:12.674 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:08:12.674 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:08:13.089 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:08:13.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:13.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:13.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:13.139 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:13.561 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:08:14.035 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:08:14.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:14.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:14.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:14.140 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:14.507 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:08:14.979 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:08:15.141 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:15.141 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:15.141 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:15.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:15.450 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:08:15.923 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:08:16.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:16.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:16.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:16.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:16.396 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:08:16.868 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:08:17.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:17.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:17.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:17.143 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:17.339 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:08:17.809 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:08:18.280 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:08:18.754 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:08:19.226 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:08:19.698 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:08:20.169 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:08:20.640 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:08:21.113 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:08:21.459 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:08:21.459 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:08:21.465 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:21.465 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:21.465 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:21.465 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:21.469 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:21.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:21.469 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:21.469 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:21.469 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:21.469 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:21.469 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2017 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:21.469 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2018 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:26.472 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:26.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:26.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:26.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:26.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:26.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:26.481 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:26.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:26.484 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:26.484 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:26.484 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:08:26.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:08:26.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:08:26.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:26.491 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:26.492 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:26.492 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:08:26.493 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:26.493 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:08:26.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:26.495 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:08:26.495 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:08:26.496 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:26.496 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:26.496 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:26.497 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:08:26.497 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:26.497 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:08:26.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:26.500 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:08:26.500 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:08:26.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:26.500 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:26.500 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:26.500 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:08:26.500 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:26.500 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:08:26.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:26.504 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:08:26.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:08:26.504 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:08:26.504 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:08:26.504 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:08:26.504 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:08:26.505 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:08:26.505 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:08:26.505 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.505 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:26.510 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:08:26.988 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:08:27.037 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:08:27.040 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:08:27.041 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:08:27.042 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:08:27.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:08:27.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:08:27.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:08:27.054 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:08:27.054 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:08:27.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:08:27.056 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:08:27.056 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:08:27.460 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:08:27.509 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:27.509 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:27.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:27.510 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:27.931 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:08:28.405 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:08:28.510 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:28.511 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:28.511 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:28.511 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:28.876 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:08:29.348 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:08:29.512 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:29.512 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:29.512 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:29.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:29.820 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:08:30.103 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:08:30.103 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=0, maio=1, ma_len=2
2026-03-01 03:08:30.103 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:08:30.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:08:30.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:08:30.293 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:08:30.513 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:30.513 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:30.513 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:30.514 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:30.765 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:08:31.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:08:31.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:08:31.153 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:08:31.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:08:31.159 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:31.159 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:31.160 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:31.160 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:31.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:31.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:31.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:31.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:31.163 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:31.163 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:31.164 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:08:31.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1006 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:31.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1006 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:31.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1006 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:31.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1006 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:31.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1006 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:31.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1006 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:36.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:36.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:36.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:36.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:36.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:36.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:36.171 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:36.171 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:36.171 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:36.171 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:36.171 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:08:36.174 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:08:36.174 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:08:36.174 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:36.174 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:36.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:36.175 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:08:36.175 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:36.175 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:08:36.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:36.177 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:08:36.177 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:08:36.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:36.177 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:36.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:36.177 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:08:36.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:36.178 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:08:36.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:36.180 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:08:36.180 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:08:36.180 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:36.180 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:36.180 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:36.180 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:08:36.180 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:36.180 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:08:36.181 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:08:36.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:08:36.185 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:08:36.185 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:08:36.185 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:36.190 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:08:36.667 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:08:36.715 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:08:36.717 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:08:36.717 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:08:36.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:08:36.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:36.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:36.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:36.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:36.793 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:36.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:36.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:36.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:36.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:36.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:36.794 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:08:36.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=131 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:36.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=131 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:36.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=131 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:36.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=131 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:36.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=131 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:36.794 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=131 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:41.798 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:41.798 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:41.798 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:41.798 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:41.798 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:41.798 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:41.806 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:41.807 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:41.808 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:41.808 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:41.808 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:08:41.810 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:08:41.810 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:08:41.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:41.811 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:41.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:41.811 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:08:41.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:41.812 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:08:41.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:41.812 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:08:41.813 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:08:41.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:41.813 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:41.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:41.813 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:08:41.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:41.813 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:08:41.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:41.814 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:08:41.815 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:08:41.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:41.815 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:41.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:41.815 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:08:41.815 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:41.815 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:08:41.815 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:08:41.817 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:08:41.817 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:08:41.817 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.817 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.818 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:41.822 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:08:42.298 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:08:42.342 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:08:42.345 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:08:42.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:08:42.347 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:08:42.770 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:08:42.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:42.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:42.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:42.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:43.245 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:08:43.717 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:08:43.821 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:43.821 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:43.821 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:43.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:44.188 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:08:44.662 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:08:44.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:44.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:44.823 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:44.823 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:45.134 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:08:45.610 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:08:45.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:45.823 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:45.824 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:45.824 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:46.083 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:08:46.557 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:08:46.825 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:46.825 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:46.825 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:46.825 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:47.029 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:08:47.504 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:08:47.976 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:08:48.452 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:08:48.924 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:08:49.399 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:08:49.871 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:08:50.345 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:08:50.809 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:08:51.273 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:08:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:08:51.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:51.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:51.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:51.366 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:51.367 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:51.368 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:51.368 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:51.368 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:08:51.368 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:51.368 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:51.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:51.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2063 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:51.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2063 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:51.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2063 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:51.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2063 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:51.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2063 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:51.368 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2063 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:08:56.371 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:08:56.371 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:08:56.371 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:56.371 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:56.371 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:56.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:56.378 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:08:56.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:56.379 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:56.379 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:08:56.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:08:56.382 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:08:56.383 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:08:56.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:56.383 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:56.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:08:56.383 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:08:56.383 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:08:56.383 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:08:56.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:56.387 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:08:56.387 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:08:56.387 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:56.387 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:56.387 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:08:56.387 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:08:56.387 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:08:56.387 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:08:56.388 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:56.390 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:08:56.390 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:08:56.390 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:56.390 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:08:56.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:08:56.391 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:08:56.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:08:56.391 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:08:56.391 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:08:56.394 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:08:56.395 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:08:56.395 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:08:56.395 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:08:56.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:08:56.399 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:08:56.876 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:08:56.921 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:08:56.923 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:08:56.925 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:08:56.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:08:57.348 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:08:57.397 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:57.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:57.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:57.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:57.823 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:08:58.295 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:08:58.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:58.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:58.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:58.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:58.770 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:08:59.242 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:08:59.400 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:08:59.401 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:08:59.401 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:08:59.401 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:08:59.716 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:09:00.188 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:09:00.402 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:00.402 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:00.402 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:00.402 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:00.660 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:09:01.135 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:09:01.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:01.404 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:01.404 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:01.404 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:01.608 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:09:02.075 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:09:02.539 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:09:03.003 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:09:03.467 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:09:03.930 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:09:04.394 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:09:04.861 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:09:05.323 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:09:05.786 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:09:05.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:05.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:05.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:05.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:05.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:05.939 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:05.939 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:05.939 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:05.939 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:05.939 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:05.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:05.939 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:09:10.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:10.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:10.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:10.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:10.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:10.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:10.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:10.944 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:10.944 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:10.944 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:10.945 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:09:10.945 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:09:10.946 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:09:10.946 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:10.946 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:10.946 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:10.946 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:09:10.946 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:10.946 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:09:10.946 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:10.947 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:09:10.947 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:09:10.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:10.947 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:10.947 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:10.947 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:09:10.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:10.947 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:09:10.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:10.948 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:09:10.948 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:09:10.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:10.948 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:10.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:10.948 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:09:10.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:10.948 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:09:10.948 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:10.950 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:09:10.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:09:10.950 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:09:10.950 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:09:10.950 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:09:10.950 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:09:10.951 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:09:10.951 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:09:10.951 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:10.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:10.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:10.956 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:09:11.423 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:09:11.477 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:09:11.479 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:09:11.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:11.480 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:09:11.890 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:09:11.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:11.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:11.954 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:11.954 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:12.361 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:09:12.832 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:09:12.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:12.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:12.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:12.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:13.303 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:09:13.774 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:09:13.957 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:13.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:13.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:13.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:14.244 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:09:14.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:14.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:14.529 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:14.529 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:14.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:14.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:14.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:14.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:14.530 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:14.530 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:14.530 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:14.530 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:09:14.530 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=778 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:14.530 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=778 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:14.530 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=778 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:14.530 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=778 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:14.530 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=778 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:19.538 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:19.538 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:19.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:19.539 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:19.539 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:19.539 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:19.552 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:19.554 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:19.554 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:19.555 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:19.555 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:09:19.559 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:09:19.559 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:09:19.559 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:19.559 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:19.559 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:19.559 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:09:19.560 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:19.560 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:09:19.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:19.562 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:09:19.562 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:09:19.562 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:19.562 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:19.563 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:19.563 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:09:19.563 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:19.563 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:09:19.563 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:19.565 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:09:19.566 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:09:19.566 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:19.566 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:19.566 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:19.566 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:09:19.566 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:19.566 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:09:19.566 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.569 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:09:19.569 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:09:19.569 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:09:19.570 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.571 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:19.571 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:19.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:19.574 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:09:20.046 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:09:20.093 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:09:20.095 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:09:20.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:20.096 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:09:20.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:20.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:20.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:09:20.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:09:20.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:09:20.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:09:20.117 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:09:20.117 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:09:20.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:20.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:09:20.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:09:20.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:09:20.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:09:20.509 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:09:20.513 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:20.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:09:20.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:20.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:20.520 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:20.520 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:20.520 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:20.520 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:20.524 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:20.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:20.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:20.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:20.525 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:09:20.526 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:20.526 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:20.526 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=209 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:20.526 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=209 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:20.526 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=209 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:20.526 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=209 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:20.526 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=209 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:20.526 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=209 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:25.523 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:25.523 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:25.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:25.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:25.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:25.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:25.529 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:25.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:25.529 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:25.529 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:25.529 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:09:25.530 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:09:25.530 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:09:25.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:25.530 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:25.531 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:25.531 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:09:25.531 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:25.531 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:09:25.531 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:25.531 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:09:25.531 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:09:25.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:25.532 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:25.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:25.532 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:09:25.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:25.532 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:09:25.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:25.533 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:09:25.533 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:09:25.533 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:25.533 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:25.533 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:25.533 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:09:25.533 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:25.533 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:09:25.533 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:09:25.535 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:09:25.535 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:09:25.535 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:25.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:25.540 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:09:26.010 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:09:26.055 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:09:26.056 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:09:26.057 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:09:26.059 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:26.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:26.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:26.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:26.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:26.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:26.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:26.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:26.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:26.073 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:26.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:26.073 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:09:26.074 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:26.074 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:26.074 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:26.074 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:26.074 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:26.074 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:09:31.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:31.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:31.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:31.070 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:31.070 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:31.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:31.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:31.074 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:31.074 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:31.074 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:31.074 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:09:31.075 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:09:31.075 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:09:31.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:31.075 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:31.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:31.075 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:09:31.075 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:31.075 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:09:31.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:31.076 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:09:31.076 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:09:31.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:31.076 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:31.076 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:31.076 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:09:31.076 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:31.076 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:09:31.076 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:31.077 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:09:31.077 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:09:31.077 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:31.077 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:31.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:31.077 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:09:31.077 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:31.077 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:09:31.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:09:31.079 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:09:31.079 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:09:31.079 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:09:31.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:31.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:31.084 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:09:31.555 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:09:31.592 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:09:31.592 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:09:31.593 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:09:31.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:32.021 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:09:32.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:32.082 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:32.082 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:32.082 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:32.492 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:09:32.960 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:09:33.083 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:33.083 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:33.084 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:33.084 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:33.426 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:09:33.600 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:33.600 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:33.600 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:33.600 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:33.601 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:33.601 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:33.601 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:33.601 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:33.601 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:33.601 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:33.601 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:09:38.606 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:38.606 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:38.606 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:38.606 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:38.606 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:38.606 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:38.614 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:38.614 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:38.614 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:38.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:38.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:09:38.617 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:09:38.617 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:09:38.617 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:38.617 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:38.618 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:38.618 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:09:38.618 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:38.618 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:09:38.619 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:38.620 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:09:38.620 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:09:38.620 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:38.620 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:38.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:38.620 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:09:38.620 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:38.620 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:09:38.620 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:38.623 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:09:38.623 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:09:38.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:38.623 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:38.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:38.623 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:09:38.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:38.623 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:09:38.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:38.626 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:09:38.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:09:38.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:09:38.627 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:09:38.627 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:09:38.627 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:09:38.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:38.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:38.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:38.632 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:09:39.110 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:09:39.162 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:09:39.164 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:09:39.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:39.167 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:09:39.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:39.171 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:39.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:09:39.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:09:39.172 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:09:39.172 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:09:39.172 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:09:39.172 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:09:39.581 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:09:39.630 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:39.631 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:39.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:39.631 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:40.048 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:09:40.516 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:09:40.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:40.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:40.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:40.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:40.989 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:09:41.461 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:09:41.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:41.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:41.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:41.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:41.932 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:09:41.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:41.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:41.952 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:41.952 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:41.953 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:41.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:41.953 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:41.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:41.953 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:41.953 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:41.953 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:41.953 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:09:41.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:46.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:46.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:46.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:46.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:46.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:46.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:46.964 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:46.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:46.964 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:46.964 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:46.964 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:09:46.965 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:09:46.965 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:09:46.965 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:46.965 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:46.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:46.965 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:09:46.965 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:46.965 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:09:46.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:46.966 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:09:46.967 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:09:46.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:46.967 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:46.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:46.967 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:09:46.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:46.967 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:09:46.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:46.968 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:09:46.968 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:09:46.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:46.968 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:46.968 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:46.968 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:09:46.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:46.968 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:09:46.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:09:46.970 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:09:46.970 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:09:46.970 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.970 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:46.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:46.975 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:09:47.453 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:09:47.496 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:09:47.498 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:09:47.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:47.499 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:09:47.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:47.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:47.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:09:47.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:09:47.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:09:47.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:09:47.504 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:09:47.504 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:09:47.925 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:09:47.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:47.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:47.974 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:47.974 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:48.396 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:09:48.867 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:09:48.975 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:48.975 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:48.975 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:48.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:49.341 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:09:49.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:49.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:49.597 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:49.597 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:49.597 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:49.597 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:49.599 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:49.599 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:49.599 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:49.599 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:49.599 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:09:49.599 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:49.599 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:54.604 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:54.605 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:54.605 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:54.605 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:54.605 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:54.605 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:54.613 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:54.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:54.615 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:54.615 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:09:54.615 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:09:54.619 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:09:54.619 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:09:54.620 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:54.620 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:54.620 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:54.620 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:09:54.621 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:09:54.621 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:09:54.621 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:54.622 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:09:54.623 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:09:54.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:54.623 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:54.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:54.623 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:09:54.623 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:09:54.623 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:09:54.623 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:54.625 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:09:54.625 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:09:54.625 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:54.626 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:09:54.626 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:54.626 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:09:54.626 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:09:54.626 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:09:54.626 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:54.628 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:09:54.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:09:54.629 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:09:54.629 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:09:54.629 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:09:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:09:54.634 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:09:55.111 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:09:55.157 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:09:55.159 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:09:55.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:09:55.161 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:09:55.172 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:55.172 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:55.172 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:09:55.173 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:09:55.174 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:09:55.174 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:09:55.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:09:55.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:09:55.583 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:09:55.631 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:55.632 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:55.632 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:55.632 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:56.054 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:09:56.528 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:09:56.632 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:56.633 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:56.633 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:56.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:56.999 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:09:57.471 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:09:57.633 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:57.634 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:57.634 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:57.634 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:57.942 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:09:57.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:09:57.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:09:57.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:09:57.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:09:57.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:09:57.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:09:57.967 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:09:57.967 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:09:57.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:09:57.967 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:09:57.967 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:09:57.967 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:09:57.967 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:02.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:02.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:02.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:02.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:02.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:02.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:02.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:02.983 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:02.983 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:02.983 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:02.984 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:02.986 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:02.986 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:02.986 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:02.986 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:02.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:02.987 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:02.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:02.987 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:02.987 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:02.988 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:02.988 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:02.988 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:02.988 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:02.989 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:02.989 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:02.989 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:02.989 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:02.989 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:02.990 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:02.990 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:02.990 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:02.990 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:02.990 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:02.991 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:02.991 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:02.991 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:02.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:02.993 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:02.993 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:02.993 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.993 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:02.994 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:02.998 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:10:03.476 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:10:03.513 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:10:03.514 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:10:03.516 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:10:03.517 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:03.521 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:03.521 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:03.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:10:03.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:10:03.523 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:10:03.523 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:10:03.523 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:10:03.523 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:10:03.948 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:10:03.996 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:03.997 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:03.997 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:03.997 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:04.420 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:10:04.893 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:10:04.998 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:04.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:04.998 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:04.998 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:05.365 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:10:05.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:05.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:05.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:05.627 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:05.627 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:05.628 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:05.630 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:05.630 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:05.630 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:05.630 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:05.630 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:05.630 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:05.630 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:05.630 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=569 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:05.630 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=569 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:05.630 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=569 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:05.630 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=569 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:05.630 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=569 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:05.631 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=569 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:10.634 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:10.634 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:10.634 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:10.634 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:10.634 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:10.634 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:10.657 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:10.659 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:10.659 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:10.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:10.660 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:10.666 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:10.667 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:10.667 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:10.667 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:10.668 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:10.669 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:10.669 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:10.669 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:10.670 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:10.673 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:10.673 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:10.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:10.674 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:10.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:10.675 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:10.675 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:10.675 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:10.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:10.676 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:10.677 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:10.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:10.677 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:10.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:10.677 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:10.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:10.677 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:10.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:10.681 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:10.681 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:10.681 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:10.681 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:10.686 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:10:11.164 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:10:11.214 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:10:11.216 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:10:11.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:11.218 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:10:11.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:11.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:11.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:10:11.227 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:10:11.227 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:10:11.227 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:10:11.227 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:10:11.227 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:10:11.635 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:10:11.685 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:11.685 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:11.685 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:11.685 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:12.107 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:10:12.581 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:10:12.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:12.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:12.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:12.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:13.053 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:10:13.525 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:10:13.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:13.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:13.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:13.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:13.998 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:10:14.470 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:10:14.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:14.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:14.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:14.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:14.942 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:10:14.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:14.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:14.968 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:14.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:14.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:14.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:14.970 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:14.971 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:14.971 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:14.971 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:14.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:14.971 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:14.971 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:14.971 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:14.971 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:14.971 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:14.971 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:14.971 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:14.971 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=926 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:19.975 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:19.975 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:19.975 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:19.975 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:19.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:19.975 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:19.983 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:19.984 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:19.984 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:19.984 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:19.984 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:19.986 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:19.987 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:19.987 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:19.987 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:19.988 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:19.988 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:19.988 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:19.988 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:19.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:19.990 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:19.990 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:19.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:19.990 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:19.990 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:19.990 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:19.990 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:19.990 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:19.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:19.992 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:19.993 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:19.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:19.993 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:19.993 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:19.993 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:19.993 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:19.993 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:19.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:19.996 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:19.996 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:19.996 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:19.996 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:19.996 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:19.997 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:19.997 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:19.997 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.997 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:19.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:20.002 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:10:20.480 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:10:20.523 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:10:20.526 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:10:20.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:20.528 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:10:20.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:20.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:20.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:10:20.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:10:20.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:10:20.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:10:20.534 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:10:20.534 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:10:20.952 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:10:21.000 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:21.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:21.001 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:21.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:21.424 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:10:21.895 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:10:22.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:22.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:22.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:22.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:22.368 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:10:22.840 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:10:23.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:23.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:23.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:23.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:23.313 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:10:23.784 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:10:24.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:24.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:24.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:24.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:24.256 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:10:24.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:24.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:24.516 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:24.516 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:24.516 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:24.516 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:24.520 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:24.520 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:24.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:24.521 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:24.521 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:24.521 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:24.521 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:24.521 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=978 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:24.521 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=978 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:24.521 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=978 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:24.522 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=978 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:24.522 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=978 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:24.522 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=978 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:24.522 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=978 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:29.523 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:29.523 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:29.523 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:29.523 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:29.523 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:29.523 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:29.533 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:29.535 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:29.535 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:29.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:29.536 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:29.541 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:29.542 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:29.542 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:29.542 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:29.543 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:29.543 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:29.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:29.544 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:29.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:29.546 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:29.547 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:29.547 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:29.547 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:29.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:29.548 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:29.548 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:29.548 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:29.549 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:29.550 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:29.551 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:29.551 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:29.551 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:29.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:29.551 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:29.552 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:29.552 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:29.552 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:29.555 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:29.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:29.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:29.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:29.555 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:29.556 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:29.556 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:29.556 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:29.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:29.561 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:10:30.039 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:10:30.086 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:10:30.088 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:10:30.090 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:10:30.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:30.511 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:10:30.559 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:30.560 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:30.560 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:30.560 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:30.986 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:10:31.458 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:10:31.561 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:31.561 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:31.561 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:31.562 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:31.932 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:10:32.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:32.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:32.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:32.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:32.106 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:32.106 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:32.106 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:32.106 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:32.106 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:32.106 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:32.106 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:37.116 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:37.116 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:37.117 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:37.117 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:37.117 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:37.117 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:37.123 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:37.124 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:37.124 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:37.125 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:37.125 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:37.127 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:37.127 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:37.128 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:37.128 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:37.128 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:37.129 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:37.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:37.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:37.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:37.130 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:37.130 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:37.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:37.130 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:37.131 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:37.131 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:37.131 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:37.131 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:37.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:37.133 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:37.133 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:37.133 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:37.133 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:37.133 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:37.133 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:37.133 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:37.133 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:37.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:37.136 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:37.136 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:37.136 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:37.136 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:37.136 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:37.137 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:37.137 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:37.137 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:37.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.142 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:10:37.620 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:10:37.666 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:10:37.668 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:10:37.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:37.671 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:10:37.694 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:37.694 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:37.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:10:37.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:37.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:38.091 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:10:38.140 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:38.140 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:38.140 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:38.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:38.567 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:10:39.039 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:10:39.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:39.142 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:39.142 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:39.142 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:39.513 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:10:39.985 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:10:40.143 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:40.143 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:40.143 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:40.144 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:40.457 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:10:40.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:40.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:40.727 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:40.727 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:40.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:40.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:40.729 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:40.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:40.729 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:40.729 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:40.729 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:40.729 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:40.729 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=775 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:45.735 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:45.735 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:45.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:45.735 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:45.735 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:45.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:45.743 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:45.744 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:45.744 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:45.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:45.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:45.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:45.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:45.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:45.749 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:45.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:45.750 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:45.750 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:45.750 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:45.750 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:45.751 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:45.751 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:45.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:45.751 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:45.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:45.752 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:45.752 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:45.752 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:45.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:45.754 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:45.754 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:45.754 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:45.754 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:45.754 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:45.754 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:45.754 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:45.754 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:45.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:45.756 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:45.757 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:45.757 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:45.757 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:45.762 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:10:46.239 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:10:46.287 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:10:46.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:46.290 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:10:46.294 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:10:46.318 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:46.318 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:46.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:10:46.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:46.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:46.330 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:46.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:46.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:46.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:46.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:46.335 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:46.335 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:46.335 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:46.336 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:46.336 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:46.336 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:46.336 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:51.340 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:51.340 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:51.341 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:51.341 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:51.341 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:51.341 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:51.348 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:51.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:51.349 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:51.349 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:51.349 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:51.351 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:51.352 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:51.352 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:51.352 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:51.352 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:51.352 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:51.353 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:51.353 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:51.353 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:51.354 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:51.354 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:51.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:51.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:51.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:51.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:51.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:51.354 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:51.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:51.356 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:51.356 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:51.356 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:51.356 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:51.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:51.356 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:51.357 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:51.357 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:51.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:51.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:51.359 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:51.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:51.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:51.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:10:51.842 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:10:51.878 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:10:51.878 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:10:51.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:51.881 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:10:51.906 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:10:51.906 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:10:51.906 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:10:51.913 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:51.914 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:52.313 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:10:52.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:52.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:52.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:52.362 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:52.785 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:10:53.257 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:10:53.363 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:53.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:53.364 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:53.364 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:53.732 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:10:54.204 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:10:54.365 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:54.365 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:54.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:54.365 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:54.679 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:10:54.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:10:54.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:54.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:54.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:54.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:54.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:54.934 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:54.934 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:54.934 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:54.934 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:10:54.934 [WARNING] transceiver.py:257 (TRX1@172.18.36.20:5700/1) RX TRXD message (ver=1 fn=771 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:54.934 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:54.934 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=771 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:54.934 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=771 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:54.934 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=771 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:54.934 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=771 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:54.934 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=771 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:54.934 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=771 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:10:59.939 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:10:59.939 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:10:59.940 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:59.940 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:59.940 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:59.940 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:59.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:10:59.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:59.950 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:59.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:10:59.950 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:10:59.953 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:10:59.953 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:10:59.953 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:59.954 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:59.954 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:10:59.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:10:59.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:10:59.954 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:10:59.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:10:59.958 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:10:59.958 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:10:59.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:59.958 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:59.958 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:10:59.958 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:10:59.958 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:10:59.958 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:10:59.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:10:59.960 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:10:59.960 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:10:59.960 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:59.960 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:10:59.960 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:10:59.961 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:10:59.961 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:10:59.961 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:10:59.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:10:59.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:10:59.964 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:10:59.964 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:10:59.964 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.964 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:10:59.968 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:00.447 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:00.490 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:00.492 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:00.493 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:00.494 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:00.519 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:11:00.519 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:11:00.519 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:11:00.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:00.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:00.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:00.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:00.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:00.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:00.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:00.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:00.540 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:00.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:00.541 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:00.541 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:00.541 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:00.541 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:00.541 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:00.541 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:00.541 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:00.541 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:00.541 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:00.541 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:00.541 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=124 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:05.546 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:05.546 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:05.546 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:05.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:05.546 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:05.546 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:05.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:05.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:05.557 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:05.557 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:05.557 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:05.561 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:05.562 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:05.562 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:05.562 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:05.562 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:05.562 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:05.562 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:05.562 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:05.563 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:05.566 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:05.566 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:05.566 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:05.566 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:05.566 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:05.566 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:05.567 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:05.567 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:05.567 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:05.570 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:05.570 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:05.570 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:05.570 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:05.570 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:05.570 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:05.571 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:05.571 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:05.571 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:05.575 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:05.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:05.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:05.575 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:05.575 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:05.575 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:05.575 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:05.576 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:05.576 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:05.576 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:05.576 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.578 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:05.581 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:06.059 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:06.111 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:06.113 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:06.115 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:06.117 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:06.128 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:06.128 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:06.128 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:06.128 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:06.129 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:06.129 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:06.129 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:06.129 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:06.130 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:06.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:06.130 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:06.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:06.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:06.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:06.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:06.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:06.130 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=119 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:11.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:11.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:11.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:11.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:11.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:11.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:11.143 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:11.144 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:11.145 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:11.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:11.145 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:11.149 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:11.149 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:11.149 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:11.149 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:11.150 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:11.150 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:11.150 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:11.150 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:11.150 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:11.153 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:11.153 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:11.153 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:11.153 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:11.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:11.154 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:11.154 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:11.154 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:11.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:11.157 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:11.157 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:11.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:11.157 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:11.157 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:11.157 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:11.157 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:11.157 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:11.157 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.161 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:11.161 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:11.161 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:11.161 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:11.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:11.166 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:11.644 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:11.690 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:11.693 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:11.694 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:11.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:11.701 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:11.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:11.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:11.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:11.705 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:11.705 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:11.705 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:11.705 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:11.705 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:11.705 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:11.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:11.705 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:11.705 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:11.705 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:11.705 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:11.705 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:11.705 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=117 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:16.709 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:16.709 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:16.709 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:16.709 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:16.709 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:16.709 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:16.717 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:16.719 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:16.719 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:16.719 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:16.719 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:16.723 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:16.723 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:16.723 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:16.723 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:16.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:16.724 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:16.724 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:16.724 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:16.724 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:16.728 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:16.728 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:16.728 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:16.728 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:16.729 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:16.729 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:16.729 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:16.729 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:16.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:16.733 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:16.733 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:16.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:16.733 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:16.733 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:16.733 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:16.733 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:16.733 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:16.734 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.739 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:16.740 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:16.740 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.740 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:16.740 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.741 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.742 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:16.745 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:17.223 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:17.272 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:17.274 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:17.276 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:17.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:17.286 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:17.286 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:17.286 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:17.286 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:17.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:17.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:17.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:17.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:17.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:17.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:17.288 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:17.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:17.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:17.288 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:17.289 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:17.289 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:17.289 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:22.293 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:22.293 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:22.293 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:22.293 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:22.293 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:22.293 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:22.300 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:22.301 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:22.301 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:22.301 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:22.302 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:22.306 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:22.306 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:22.306 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:22.307 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:22.307 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:22.307 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:22.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:22.308 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:22.308 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:22.309 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:22.309 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:22.309 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:22.309 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:22.310 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:22.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:22.310 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:22.310 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:22.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:22.313 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:22.313 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:22.313 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:22.313 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:22.313 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:22.313 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:22.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:22.314 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:22.314 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.317 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:22.317 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:22.317 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:22.317 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:22.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:22.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:22.322 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:22.801 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:22.847 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:22.849 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:22.851 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:22.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:22.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:22.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:22.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:22.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:22.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:22.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:22.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:22.869 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:22.870 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:22.870 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:22.870 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:22.870 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:22.870 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:22.870 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:22.870 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:22.870 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:22.870 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:22.871 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=118 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:27.872 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:27.872 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:27.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:27.872 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:27.872 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:27.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:27.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:27.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:27.881 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:27.881 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:27.881 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:27.885 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:27.885 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:27.886 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:27.886 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:27.887 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:27.887 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:27.887 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:27.888 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:27.888 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:27.890 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:27.890 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:27.891 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:27.891 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:27.891 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:27.892 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:27.892 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:27.892 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:27.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:27.894 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:27.895 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:27.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:27.895 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:27.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:27.895 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:27.895 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:27.895 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:27.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:27.900 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:27.900 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.901 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:27.902 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:27.902 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:27.902 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.902 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:27.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:27.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:27.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:27.906 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:28.384 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:28.438 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:28.441 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:28.442 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:28.442 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:28.856 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:11:28.906 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:28.907 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:28.907 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:28.908 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:29.330 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:11:29.802 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:11:29.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:29.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:29.908 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:29.910 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:30.274 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:11:30.748 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:11:30.910 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:30.910 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:30.910 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:30.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:31.220 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:11:31.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:11:31.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:11:31.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:11:31.465 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:11:31.465 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:11:31.466 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:11:31.466 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:11:31.466 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:11:31.692 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:11:31.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:31.911 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:31.911 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:31.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:32.163 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:11:32.637 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:11:32.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:32.913 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:32.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:32.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:33.109 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:11:33.581 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:11:33.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:11:33.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:11:33.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:33.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:33.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:33.712 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:33.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:33.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:33.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:33.716 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:33.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:33.716 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:33.716 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:33.716 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:33.717 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1255 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:33.717 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1255 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:33.717 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1255 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:33.717 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1255 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:33.717 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1255 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:33.717 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1255 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:38.723 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:38.723 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:38.723 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:38.724 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:38.724 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:38.724 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:38.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:38.732 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:38.732 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:38.732 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:38.732 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:38.734 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:38.734 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:38.735 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:38.735 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:38.735 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:38.735 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:38.735 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:38.735 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:38.735 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:38.737 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:38.737 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:38.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:38.737 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:38.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:38.737 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:38.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:38.737 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:38.737 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:38.739 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:38.739 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:38.739 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:38.739 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:38.739 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:38.739 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:38.740 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:38.740 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:38.740 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:38.743 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:38.743 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:38.743 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:38.743 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.744 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:38.745 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:38.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:38.748 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:39.225 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:39.273 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:39.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:39.277 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:39.279 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:39.301 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:11:39.301 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:11:39.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:11:39.312 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:39.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:39.313 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:39.313 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:39.316 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:39.316 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:39.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:39.316 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:39.316 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:39.316 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:39.316 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:39.317 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:39.317 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:39.317 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:39.317 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:39.317 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:39.317 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:44.320 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:44.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:44.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:44.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:44.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:44.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:44.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:44.330 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:44.330 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:44.331 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:44.331 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:44.336 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:44.336 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:44.337 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:44.337 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:44.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:44.338 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:44.338 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:44.338 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:44.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:44.340 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:44.341 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:44.341 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:44.341 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:44.342 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:44.342 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:44.342 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:44.342 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:44.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:44.344 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:44.344 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:44.344 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:44.344 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:44.344 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:44.344 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:44.344 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:44.344 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:44.345 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:44.348 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:44.349 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:44.349 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:44.349 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.349 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:44.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.353 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:44.832 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:44.879 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:44.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:44.882 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:44.885 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:44.908 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:11:44.909 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:11:44.909 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:11:44.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:44.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:44.927 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:44.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:44.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:44.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:44.930 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:44.931 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:44.931 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:44.931 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:44.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:44.931 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:44.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:44.931 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:44.931 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:44.931 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:44.931 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:44.931 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:44.931 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=125 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:49.935 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:49.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:49.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:49.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:49.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:49.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:49.942 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:49.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:49.943 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:49.943 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:49.944 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:49.945 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:49.946 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:49.946 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:49.946 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:49.946 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:49.946 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:49.947 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:49.947 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:49.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:49.948 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:49.948 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:49.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:49.948 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:49.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:49.948 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:49.948 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:49.948 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:49.948 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:49.950 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:49.950 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:49.950 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:49.950 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:49.950 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:49.950 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:49.950 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:49.950 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:49.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:49.953 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:49.953 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:49.953 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:49.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:49.957 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:50.436 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:50.478 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:50.480 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:50.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:50.482 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:50.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:11:50.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:11:50.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:11:50.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:50.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:50.520 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:50.524 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:50.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:50.525 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:50.525 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:50.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:50.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:50.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:50.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:50.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:50.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:50.528 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:55.530 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:55.530 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:55.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:55.530 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:55.530 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:55.530 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:55.535 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:55.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:55.536 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:55.536 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:11:55.536 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:11:55.538 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:11:55.539 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:11:55.539 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:55.539 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:55.539 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:55.539 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:11:55.540 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:11:55.540 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:11:55.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:55.541 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:11:55.541 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:11:55.542 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:55.542 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:55.542 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:55.542 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:11:55.542 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:11:55.542 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:11:55.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:55.544 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:11:55.544 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:11:55.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:55.544 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:11:55.544 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:55.544 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:11:55.544 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:11:55.544 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:11:55.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:11:55.547 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:11:55.547 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:11:55.547 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.547 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:55.548 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:11:55.552 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:11:56.028 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:11:56.075 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:11:56.077 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:11:56.078 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:11:56.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.097 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:11:56.097 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:11:56.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:11:56.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:11:56.119 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.123 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:11:56.158 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:11:56.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:11:56.158 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:11:56.158 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:11:56.161 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:11:56.161 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:11:56.162 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:11:56.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:11:56.162 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:11:56.162 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:11:56.162 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:11:56.162 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.162 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=132 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:11:56.163 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:01.163 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:01.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:01.164 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:01.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:01.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:01.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:01.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:01.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:01.174 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:01.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:01.174 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:12:01.179 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:12:01.179 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:12:01.179 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:01.179 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:01.180 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:01.180 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:12:01.180 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:01.180 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:12:01.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:01.183 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:12:01.184 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:12:01.184 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:01.184 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:01.184 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:01.184 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:12:01.184 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:01.184 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:12:01.184 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:01.188 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:12:01.188 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:12:01.188 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:01.188 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:01.188 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:01.188 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:12:01.188 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:01.188 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:12:01.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:01.194 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:12:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:12:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:12:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:12:01.194 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:12:01.194 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.195 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:12:01.195 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:12:01.195 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:12:01.196 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:12:01.196 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.196 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.196 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:12:01.196 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:01.197 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:01.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:01.200 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:12:01.679 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:12:01.734 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:12:01.737 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:12:01.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:01.739 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:12:01.741 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 03:12:01.741 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 200
2026-03-01 03:12:01.741 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 03:12:01.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:02.154 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:12:02.170 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:02.371 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:02.371 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:02.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:02.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:02.572 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:02.629 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:12:03.101 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:12:03.177 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:03.378 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 03:12:03.378 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 0
2026-03-01 03:12:03.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 03:12:03.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:03.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:03.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:03.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:03.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:03.387 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:03.387 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:03.387 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:03.388 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:03.388 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:03.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:03.388 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:03.388 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:03.388 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:03.388 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:12:08.395 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:08.395 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:08.395 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:08.395 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:08.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:08.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:08.401 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:08.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:08.402 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:08.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:08.402 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:12:08.405 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:12:08.405 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:12:08.405 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:08.406 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:08.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:08.406 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:12:08.406 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:08.406 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:12:08.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:08.409 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:12:08.410 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:12:08.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:08.410 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:08.410 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:08.410 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:12:08.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:08.410 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:12:08.411 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:08.413 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:12:08.413 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:12:08.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:08.413 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:08.414 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:08.414 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:12:08.414 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:08.414 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:12:08.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.418 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:12:08.419 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:12:08.419 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:12:08.419 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:08.423 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:12:08.900 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:12:08.948 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:12:08.951 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:12:08.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:08.953 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:12:08.955 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 03:12:08.956 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 200
2026-03-01 03:12:08.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 03:12:09.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:09.376 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:12:09.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:09.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:09.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:09.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:09.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:09.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:09.851 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:12:09.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.328 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:12:10.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.591 [DEBUG] fake_trx.py:382 (BTS@172.18.36.20:5700) Recv FAKE_TRXC_DELAY cmd
2026-03-01 03:12:10.591 [INFO] fake_trx.py:385 (BTS@172.18.36.20:5700) Artificial TRXC delay set to 0
2026-03-01 03:12:10.591 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD FAKE_TRXC_DELAY
2026-03-01 03:12:10.591 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:10.591 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:10.591 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:10.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:10.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.593 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.595 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:10.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:10.602 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:10.602 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:12:15.609 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:15.609 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:15.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:15.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:15.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:15.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:15.616 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:15.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:15.617 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:15.617 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:15.617 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:12:15.619 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:12:15.619 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:12:15.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:15.619 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:15.619 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:15.619 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:12:15.619 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:15.619 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:12:15.620 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:15.620 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:12:15.620 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:12:15.620 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:15.620 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:15.620 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:15.620 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:12:15.621 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:15.621 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:12:15.621 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:15.622 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:12:15.622 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:12:15.622 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:15.623 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:15.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:15.623 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:12:15.623 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:15.623 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:12:15.623 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:12:15.626 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:12:15.627 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:12:15.627 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:12:15.627 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.627 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:15.632 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:12:16.110 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:12:16.156 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:12:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:16.159 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:12:16.161 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:12:16.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:16.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:16.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:16.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:16.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:16.194 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:16.194 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:16.194 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:16.194 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:16.195 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:16.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:16.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:16.196 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:16.196 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:16.196 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:12:16.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:16.196 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:16.196 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:16.196 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:16.196 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=122 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:21.203 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:21.203 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:21.203 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:21.203 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:21.203 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:21.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:21.210 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:21.211 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:21.211 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:21.212 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:21.212 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:12:21.215 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:12:21.215 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:12:21.216 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:21.216 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:21.216 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:21.217 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:12:21.217 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:21.217 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:12:21.217 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:21.219 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:12:21.219 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:12:21.219 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:21.220 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:21.220 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:21.220 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:12:21.221 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:21.221 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:12:21.221 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:21.223 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:12:21.223 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:12:21.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:21.223 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:21.223 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:21.223 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:12:21.223 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:21.223 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:12:21.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:21.227 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:12:21.228 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:12:21.228 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:12:21.228 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.228 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:21.232 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:12:21.710 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:12:21.755 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:12:21.758 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:12:21.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:21.760 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:12:21.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:21.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:21.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:21.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:21.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:21.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:21.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:21.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:21.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:21.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:21.822 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:21.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:21.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:21.822 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:21.822 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:21.822 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:12:21.822 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:21.823 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:21.823 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:21.823 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:21.823 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:21.823 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:21.823 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=128 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:12:26.825 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:12:26.825 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:12:26.825 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:26.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:26.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:26.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:26.832 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:12:26.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:26.833 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:26.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:12:26.834 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:12:26.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:12:26.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:12:26.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:26.836 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:26.837 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:12:26.837 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:12:26.837 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:12:26.837 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:12:26.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:26.838 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:12:26.838 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:12:26.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:26.838 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:26.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:12:26.839 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:12:26.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:12:26.839 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:12:26.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:26.840 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:12:26.840 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:12:26.840 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:26.840 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:12:26.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:12:26.840 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:12:26.841 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:12:26.841 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:12:26.841 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:12:26.843 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:12:26.843 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:12:26.843 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:12:26.844 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:12:26.848 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:12:27.324 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:12:27.373 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:12:27.375 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:12:27.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:27.375 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:12:27.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:27.397 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:27.397 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:27.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:27.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:27.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:27.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:27.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:27.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:27.426 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:27.426 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:27.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:27.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:27.483 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:27.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:27.486 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:27.486 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:27.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:27.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:27.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:27.507 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:27.507 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:27.507 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:27.507 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:27.507 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:27.561 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:27.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:27.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:27.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:27.568 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:27.796 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:12:27.845 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:27.846 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:27.846 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:27.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:28.268 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:12:28.741 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:12:28.847 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:28.847 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:28.847 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:28.847 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:29.213 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:12:29.686 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:12:29.848 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:29.848 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:29.849 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:29.849 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:30.159 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:12:30.570 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:30.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.575 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:30.576 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:30.595 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:30.595 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:30.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:30.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.596 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:30.596 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:30.596 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:30.596 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:30.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:30.631 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:12:30.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:30.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:30.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.692 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:30.694 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:30.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:30.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:30.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:30.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:30.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.715 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:30.715 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:30.715 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:30.715 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:30.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:30.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:30.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:30.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:30.849 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:30.849 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:30.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:30.850 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:31.102 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:12:31.575 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:12:31.850 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:12:31.850 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:12:31.850 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:12:31.851 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:12:32.047 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:12:32.518 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:12:32.991 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:12:33.464 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:12:33.725 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:33.727 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:33.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:33.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:33.749 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:33.749 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:33.749 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:33.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:33.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:33.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:33.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:33.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:33.795 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:33.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:33.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:33.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:33.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:33.936 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:12:34.407 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:12:34.880 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:12:35.353 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:12:35.826 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:12:36.299 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:12:36.772 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:12:36.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:36.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:36.809 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:36.810 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:36.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:36.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:36.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:36.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:36.830 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:36.830 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:36.830 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:36.830 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:36.866 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:36.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:36.873 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:36.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:36.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:36.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:36.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:36.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:36.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:36.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:36.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:36.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:36.936 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:36.936 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:36.936 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:36.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:36.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:36.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:36.963 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:36.963 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:36.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:36.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:37.244 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:12:37.715 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:12:37.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:37.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:37.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:37.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:37.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:37.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:37.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:37.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:37.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:37.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:37.941 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:37.941 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:37.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:37.947 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:37.947 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:12:37.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:37.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:38.014 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:38.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:38.018 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:38.018 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:38.018 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:38.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:38.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:38.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:38.037 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:38.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:38.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:38.038 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:38.038 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:38.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:38.098 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:38.098 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:12:38.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:38.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:38.185 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:12:38.657 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:12:39.130 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:12:39.602 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:12:40.074 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:12:40.548 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:12:41.020 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:12:41.101 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:41.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:41.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:41.105 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:41.131 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:41.131 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:41.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:41.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.133 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:41.133 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:41.133 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:41.133 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:41.161 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:41.168 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:41.168 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:12:41.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:41.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:41.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:41.227 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:41.245 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:41.245 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:41.245 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:41.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.246 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:41.246 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:41.246 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:41.246 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:41.252 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:41.254 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:41.254 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:12:41.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:41.492 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:12:41.965 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:12:42.438 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:12:42.911 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:12:43.384 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:12:43.857 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:12:44.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:44.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:44.261 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:44.261 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:44.261 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:44.280 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:44.280 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:44.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:44.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:44.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:44.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:44.282 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:44.282 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:44.329 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:12:44.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:44.339 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:44.339 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:12:44.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:44.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:44.802 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:12:45.275 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:12:45.747 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:12:46.221 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:12:46.694 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:12:47.166 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:12:47.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:47.344 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.346 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:47.346 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:47.346 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:47.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:47.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:47.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:47.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:47.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:47.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:47.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:47.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:47.409 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:47.409 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:12:47.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:47.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:47.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:47.492 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:47.505 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:47.505 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:47.505 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:47.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.506 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:47.506 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:47.506 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:47.506 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:47.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:47.551 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:47.551 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:12:47.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:47.639 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:12:48.112 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:12:48.585 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:12:48.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:48.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:48.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:48.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:48.766 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:48.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:48.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:48.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:48.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:48.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:48.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:48.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:48.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:48.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:48.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:48.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:48.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:48.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:49.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:49.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:49.051 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:49.051 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:49.055 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:12:49.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:49.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:49.068 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:49.069 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:49.069 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:49.069 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:49.069 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:49.069 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:49.102 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:49.104 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:49.104 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:49.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:49.104 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:49.526 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:12:49.997 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:12:50.468 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:12:50.941 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:12:51.414 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:12:51.886 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:12:52.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:52.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.110 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:52.110 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:52.130 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:52.130 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:52.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:52.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.132 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:52.132 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:52.132 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:52.132 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:52.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:52.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:52.176 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:52.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.347 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:52.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:52.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:52.356 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:12:52.367 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:52.367 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:52.367 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:52.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.368 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:52.368 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:52.368 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:52.368 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:52.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:52.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:52.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:52.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:52.827 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:12:53.298 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:12:53.769 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:12:54.243 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:12:54.715 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:12:55.187 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:12:55.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:55.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:55.416 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:55.416 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:55.433 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:55.433 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:55.433 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:55.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:55.434 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:55.434 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:55.434 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:55.434 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:55.469 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:55.475 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:55.476 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:55.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:55.476 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:55.658 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:12:56.131 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:12:56.604 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:12:57.076 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:12:57.550 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:12:58.022 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:12:58.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:58.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:58.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:58.494 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:12:58.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:58.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:58.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:58.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.503 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:58.503 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:58.503 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:58.503 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:58.542 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:58.549 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:58.549 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:58.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.549 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:58.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.725 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:58.725 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:58.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:58.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:58.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:58.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.742 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:58.742 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:58.742 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:58.742 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:58.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:58.784 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:58.785 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:58.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:58.963 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:12:59.436 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:12:59.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:59.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:59.481 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:59.499 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:59.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:59.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:59.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:59.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:59.500 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:59.500 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:59.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:59.539 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:59.539 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:12:59.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:59.594 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:59.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:59.596 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:12:59.610 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:12:59.610 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:12:59.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:12:59.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.611 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:12:59.611 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:12:59.611 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:12:59.611 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:12:59.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:12:59.619 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:12:59.619 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:12:59.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:12:59.908 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:13:00.380 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:13:00.853 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:13:01.326 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 03:13:01.800 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 03:13:02.273 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 03:13:02.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:02.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:02.626 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:02.626 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:02.626 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:02.643 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:02.643 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:02.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:02.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:02.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:02.645 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:02.645 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:02.645 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:02.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:02.700 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:02.700 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:02.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:02.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:02.746 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 03:13:03.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:03.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:03.139 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:03.139 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:03.140 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:03.158 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:03.158 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:03.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:03.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:03.160 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:03.160 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:03.160 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:03.160 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:03.163 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:03.165 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:03.165 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:03.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:03.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:03.217 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 03:13:03.689 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 03:13:04.162 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 03:13:04.635 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 03:13:05.108 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 03:13:05.581 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 03:13:06.053 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 03:13:06.168 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:06.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:06.173 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:06.173 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:06.173 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:06.189 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:06.189 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:06.189 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:06.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:06.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:06.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:06.190 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:06.190 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:06.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:06.247 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:06.247 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:06.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:06.248 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:06.525 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 03:13:06.996 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 03:13:07.470 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 03:13:07.942 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 03:13:08.414 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 03:13:08.885 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 03:13:09.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:09.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.255 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:09.255 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:09.255 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:09.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:09.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:09.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:09.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:09.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:09.275 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:09.275 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:09.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:09.318 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:09.319 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:09.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.357 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 03:13:09.734 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:09.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.738 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:09.739 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:09.739 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:09.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:09.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:09.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:09.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.758 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:09.759 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:09.759 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:09.759 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:09.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:09.775 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:09.776 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:09.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:09.829 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 03:13:10.302 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 03:13:10.774 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 03:13:11.248 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 03:13:11.720 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 03:13:12.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:12.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:12.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:12.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:12.180 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:12.192 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:12.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:12.192 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 03:13:12.192 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:12.192 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:12.196 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:12.196 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:12.196 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:12.196 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:12.197 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:12.197 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:12.197 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:13:12.197 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=9795 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:12.197 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=9795 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:12.197 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=9795 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:12.197 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=9795 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:12.198 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=9795 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:12.198 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=9795 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:17.198 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:17.198 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:17.198 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:17.198 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:17.198 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:17.198 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:17.203 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:17.203 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:17.204 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:17.204 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:17.204 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:13:17.206 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:13:17.206 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:13:17.207 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:17.207 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:17.207 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:17.207 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:13:17.208 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:17.208 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:13:17.208 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:17.210 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:13:17.210 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:13:17.211 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:17.211 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:17.211 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:17.212 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:13:17.212 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:17.212 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:13:17.212 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:17.214 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:13:17.214 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:13:17.214 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:17.215 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:17.215 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:17.215 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:13:17.215 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:17.215 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:13:17.215 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:13:17.220 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:13:17.221 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:13:17.221 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:13:17.221 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.221 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.222 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.223 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:17.223 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:17.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.223 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:17.226 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:13:17.704 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:13:17.753 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:13:17.755 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:13:17.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:17.757 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:13:17.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:17.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:17.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:17.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.782 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:17.782 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:17.782 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:17.782 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:17.800 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:17.807 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:17.807 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:17.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:17.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:17.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:17.882 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:17.882 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:17.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:17.883 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:17.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:17.884 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:17.884 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:17.886 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:17.888 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:17.888 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:13:17.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:17.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:17.985 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:17.985 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:17.985 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:18.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:18.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:18.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:18.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:18.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:18.005 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:18.005 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:18.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:18.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:18.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:18.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:18.098 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.100 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:18.100 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:18.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:18.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:18.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:18.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.118 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:18.118 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:18.118 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:18.118 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:18.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:18.123 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:18.123 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:18.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.123 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.174 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:13:18.225 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:18.225 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:18.225 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:18.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:18.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:18.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:18.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:18.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:18.258 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:18.267 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:18.267 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:18.267 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:18.268 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:18.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:18.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:18.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:18.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:18.271 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:18.271 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:18.271 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:13:18.271 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=227 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:18.271 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=227 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:18.271 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=227 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:18.271 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=227 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:18.271 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=227 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:18.271 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=227 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:23.273 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:23.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:23.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:23.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:23.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:23.274 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:23.282 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:23.283 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:23.283 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:23.283 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:23.283 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:13:23.286 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:13:23.286 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:13:23.287 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:23.287 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:23.287 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:23.287 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:13:23.288 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:23.288 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:13:23.288 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:23.289 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:13:23.289 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:13:23.289 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:23.289 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:23.289 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:23.289 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:13:23.289 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:23.289 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:13:23.289 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:23.291 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:13:23.291 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:13:23.291 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:23.291 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:23.291 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:23.292 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:13:23.292 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:23.292 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:13:23.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:23.294 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:13:23.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:13:23.294 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:13:23.294 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:13:23.294 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:13:23.294 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:13:23.295 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:13:23.295 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:13:23.295 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:23.296 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:23.300 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:13:23.778 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:13:23.816 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:13:23.817 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:13:23.819 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:13:23.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:23.838 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:23.838 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:23.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:23.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:23.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:23.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:23.844 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:23.844 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:23.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:23.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:23.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:23.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:23.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:24.251 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:13:24.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:24.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:24.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:24.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:24.722 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:13:24.738 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:24.741 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:24.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:24.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:24.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:24.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:24.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:24.765 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:24.766 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:24.766 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:24.766 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:24.766 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:24.816 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:24.823 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:24.823 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:13:24.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:24.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.194 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:13:25.298 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:25.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:25.299 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:25.299 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:25.458 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:25.461 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:25.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:25.463 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:25.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:25.480 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:25.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:25.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:25.481 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:25.481 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:25.481 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:25.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:25.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:25.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:25.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:25.632 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.633 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:25.633 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:25.653 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:25.653 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:25.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:25.656 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:25.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:25.657 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:25.657 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:25.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:25.663 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:25.663 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:25.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:25.666 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:13:26.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:26.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:26.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:26.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:26.058 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:26.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:26.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:26.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:26.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:26.070 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:26.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:26.070 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:26.070 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:26.070 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:26.070 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:13:26.071 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:26.071 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:26.071 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:26.071 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:26.071 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:26.071 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=600 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:31.075 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:31.075 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:31.075 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:31.075 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:31.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:31.075 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:31.083 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:31.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:31.083 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:31.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:31.084 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:13:31.087 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:13:31.087 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:13:31.087 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:31.087 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:31.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:31.088 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:13:31.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:31.089 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:13:31.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:31.090 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:13:31.090 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:13:31.090 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:31.091 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:31.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:31.091 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:13:31.091 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:31.091 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:13:31.091 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:31.092 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:13:31.092 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:13:31.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:31.093 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:31.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:31.093 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:13:31.093 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:31.093 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:13:31.093 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.095 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:13:31.096 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:13:31.096 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:13:31.096 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.096 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:31.100 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:13:31.578 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:13:31.622 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:13:31.624 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:13:31.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:31.625 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:13:31.646 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:31.646 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:31.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:31.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:31.651 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:31.651 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:31.651 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:31.651 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:31.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:31.682 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:31.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:31.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:31.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:31.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:31.849 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:31.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:31.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:31.864 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:31.864 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:31.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:31.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:31.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:31.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:31.865 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:31.865 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:31.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:31.916 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:31.916 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:13:31.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:31.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.050 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:13:32.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:32.099 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:32.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:32.099 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:32.193 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:32.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:32.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:32.198 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:32.216 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:32.216 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:32.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:32.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.219 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:32.219 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:32.219 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:32.219 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:32.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:32.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:32.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:32.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.511 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:32.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:32.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:32.521 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:13:32.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:32.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:32.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:32.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.534 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:32.534 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:32.534 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:32.534 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:32.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:32.576 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:32.576 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:32.576 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.577 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:32.992 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:13:33.100 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:33.100 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:33.100 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:33.100 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:33.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:33.382 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:33.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:33.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:33.384 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:33.394 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:33.395 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:33.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:33.395 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:33.398 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:33.399 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:33.399 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:33.399 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:13:33.399 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:33.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:33.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:33.400 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:33.400 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:33.400 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:33.400 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:33.400 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:33.400 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:33.400 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:38.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:38.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:38.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:38.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:38.403 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:38.403 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:38.411 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:38.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:38.412 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:38.412 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:38.412 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:13:38.415 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:13:38.416 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:13:38.416 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:38.416 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:38.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:38.417 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:13:38.417 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:38.417 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:13:38.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:38.418 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:13:38.418 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:13:38.418 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:38.418 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:38.418 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:38.419 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:13:38.419 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:38.419 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:13:38.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:38.421 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:13:38.421 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:13:38.421 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:38.421 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:38.421 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:38.421 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:13:38.421 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:38.421 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:13:38.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:13:38.424 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:13:38.424 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:13:38.424 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.424 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.425 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:38.429 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:13:38.907 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:13:38.951 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:13:38.953 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:13:38.954 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:38.956 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:13:38.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:38.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:38.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:38.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:38.984 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:38.984 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:38.985 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:38.985 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:39.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:39.010 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:39.011 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:39.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.011 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:39.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.179 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:39.179 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:39.196 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:39.196 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:39.196 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:39.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.198 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:39.198 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:39.198 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:39.198 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:39.239 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:39.246 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:39.246 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:13:39.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.246 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.379 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:13:39.427 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:39.427 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:39.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:39.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:39.521 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:39.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.526 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:39.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:39.527 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:39.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:39.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:39.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:39.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:39.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:39.544 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:39.544 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:39.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:39.569 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:39.569 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:39.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.569 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.841 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:39.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:39.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:39.852 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:13:39.863 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:39.863 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:39.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:39.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.865 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:39.865 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:39.865 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:39.865 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:39.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:39.905 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:39.905 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:39.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:39.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:40.325 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:13:40.429 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:40.429 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:40.429 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:40.429 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:40.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:40.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:40.719 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:40.719 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:40.719 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:40.729 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:40.729 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:40.729 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:40.729 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:40.733 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:40.733 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:40.733 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:40.734 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:13:40.734 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:40.734 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:40.734 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:40.734 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:40.734 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:40.735 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:40.735 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:40.735 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:40.735 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=498 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:13:45.736 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:13:45.736 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:13:45.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:45.736 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:45.736 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:45.736 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:45.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:13:45.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:45.745 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:45.745 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:13:45.745 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:13:45.748 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:13:45.748 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:13:45.748 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:45.748 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:45.749 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:13:45.749 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:13:45.749 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:13:45.749 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:13:45.749 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:45.750 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:13:45.750 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:13:45.750 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:45.750 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:45.751 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:13:45.751 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:13:45.751 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:13:45.751 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:13:45.751 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:45.752 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:13:45.753 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:13:45.753 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:45.753 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:13:45.753 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:13:45.753 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:13:45.753 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:13:45.753 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:13:45.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:45.755 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:13:45.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:13:45.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:13:45.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:13:45.755 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:13:45.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:13:45.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:13:45.756 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:13:45.756 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:13:45.756 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.757 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:13:45.760 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:13:46.238 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:13:46.287 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:13:46.289 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:13:46.291 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:13:46.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:46.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:46.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:46.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:46.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:46.308 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:46.308 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:46.308 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:46.308 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:46.334 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:46.339 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:46.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:46.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:46.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:46.709 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:13:46.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:46.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:46.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:46.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:47.181 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:13:47.652 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:13:47.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:47.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:47.760 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:47.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:48.123 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:13:48.166 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:48.168 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:48.170 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:48.170 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:48.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:48.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:48.188 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:48.190 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:48.190 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:48.190 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:48.190 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:48.190 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:48.216 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:48.222 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:48.222 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:13:48.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:48.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:48.595 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:13:48.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:48.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:48.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:48.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:49.069 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:13:49.541 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:13:49.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:49.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:49.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:49.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:50.014 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:13:50.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:50.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:50.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:50.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:50.342 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:13:50.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:50.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:50.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:50.360 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:50.360 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:50.360 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:50.360 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:50.361 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:50.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:50.391 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:50.391 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:50.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:50.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:50.487 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:13:50.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:13:50.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:13:50.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:13:50.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:13:50.959 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:13:51.430 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:13:51.901 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:13:51.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:51.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:51.944 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:51.944 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:51.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:13:51.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:13:51.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:13:51.966 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:51.966 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:13:51.966 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:13:51.966 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:13:51.966 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:13:51.994 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:13:52.002 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:13:52.002 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:13:52.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:52.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:13:52.373 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:13:52.846 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:13:53.318 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:13:53.791 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:13:54.264 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:13:54.735 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:13:55.208 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:13:55.681 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:13:56.153 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:13:56.626 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:13:57.099 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:13:57.571 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:13:58.044 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:13:58.517 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:13:58.989 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:13:59.462 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:13:59.936 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:14:00.408 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:14:00.879 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:14:01.353 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:14:01.826 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:14:02.299 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:14:02.771 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:14:03.237 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:14:03.708 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:14:04.180 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:14:04.650 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:14:05.123 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:14:05.597 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:14:06.068 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:14:06.540 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:14:07.014 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:14:07.486 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:14:07.958 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:14:08.431 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:14:08.904 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:14:09.375 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:14:09.848 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:14:10.320 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:14:10.792 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:14:11.265 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:14:11.739 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:14:11.968 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:11.968 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:11.968 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:14:11.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:11.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:11.971 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:11.971 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:11.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:14:11.972 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:14:11.972 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:14:11.972 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:14:11.972 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:14:11.972 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:14:11.972 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:14:11.972 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5662 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:14:11.972 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5662 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:14:11.972 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5662 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:14:16.979 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:14:16.979 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:14:16.979 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:14:16.979 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:14:16.979 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:14:16.979 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:14:16.987 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:14:16.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:14:16.988 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:16.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:14:16.988 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:14:16.991 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:14:16.991 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:14:16.991 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:14:16.991 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:16.991 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:14:16.991 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:14:16.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:14:16.992 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:14:16.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:16.993 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:14:16.993 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:14:16.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:14:16.994 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:16.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:14:16.994 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:14:16.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:14:16.994 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:14:16.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:16.995 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:14:16.996 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:14:16.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:14:16.996 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:16.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:14:16.996 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:14:16.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:14:16.996 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:14:16.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:16.998 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:14:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:14:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:14:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:14:16.998 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:14:16.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:14:16.999 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:14:16.999 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:14:16.999 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:16.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:17.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:17.004 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:14:17.481 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:14:17.526 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:14:17.527 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:14:17.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:17.528 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:14:17.545 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:17.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:17.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:17.550 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:17.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:17.550 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:17.551 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:17.551 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:17.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:17.585 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:17.586 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:17.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:17.586 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:17.952 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:14:18.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:18.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:18.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:18.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:18.425 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:14:18.896 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:14:19.003 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:19.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:19.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:19.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:19.368 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:14:19.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:19.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:19.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:19.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:19.436 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:19.436 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:19.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:19.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:19.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:19.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:19.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:19.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:19.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:19.469 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:14:19.469 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:14:19.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:19.470 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:19.840 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:14:20.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:20.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:20.004 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:20.004 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:20.313 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:14:20.785 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:14:21.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:21.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:21.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:21.259 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:14:21.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:21.587 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:21.589 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:21.589 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:21.589 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:14:21.608 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:21.608 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:21.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:21.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:21.610 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:21.610 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:21.610 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:21.610 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:21.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:21.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:21.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:21.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:21.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:21.732 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:14:22.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:22.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:22.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:22.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:22.204 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:14:22.676 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:14:23.149 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:14:23.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:23.186 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:23.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:23.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:23.206 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:23.206 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:23.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:23.208 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:23.208 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:23.208 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:23.208 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:23.208 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:23.240 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:23.246 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:14:23.247 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:14:23.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:23.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:23.621 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:14:24.093 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:14:24.564 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:14:25.038 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:14:25.509 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:14:25.981 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:14:26.454 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:14:26.927 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:14:27.399 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:14:27.870 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:14:28.344 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:14:28.816 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:14:29.288 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:14:29.761 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:14:30.234 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:14:30.706 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:14:31.179 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:14:31.652 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:14:32.124 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:14:32.598 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:14:33.070 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:14:33.543 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:14:34.016 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:14:34.489 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:14:34.962 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:14:35.435 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:14:35.907 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:14:36.380 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:14:36.853 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:14:37.325 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:14:37.797 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:14:38.269 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:14:38.742 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:14:39.214 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:14:39.686 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:14:40.159 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:14:40.631 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:14:41.104 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:14:41.577 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:14:42.050 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:14:42.522 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:14:42.995 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:14:43.210 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:43.210 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:43.210 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:14:43.213 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:14:43.213 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:14:43.214 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:14:43.214 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5660 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:14:43.214 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5660 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:14:43.214 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5660 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:14:43.214 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5660 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:14:48.221 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:14:48.221 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:14:48.222 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:14:48.222 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:14:48.222 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:14:48.222 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:14:48.230 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:14:48.232 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:14:48.232 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:48.232 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:14:48.233 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:14:48.238 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:14:48.239 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:14:48.239 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:14:48.240 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:48.240 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:14:48.241 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:14:48.241 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:14:48.241 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:14:48.242 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:48.244 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:14:48.244 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:14:48.244 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:14:48.244 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:48.244 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:14:48.244 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:14:48.245 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:14:48.245 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:14:48.245 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:48.248 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:14:48.248 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:14:48.248 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:14:48.248 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:14:48.248 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:14:48.248 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:14:48.249 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:14:48.249 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:14:48.249 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:48.254 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:14:48.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:14:48.254 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:14:48.254 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:14:48.254 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:14:48.254 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.255 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:14:48.255 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:14:48.255 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.255 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.257 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:14:48.260 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:14:48.738 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:14:48.784 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:14:48.786 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:14:48.789 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:48.789 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:14:48.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:48.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:48.811 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:48.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:48.815 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:48.815 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:48.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:48.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:48.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:48.841 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:48.841 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:48.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:48.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:49.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:49.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:49.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:49.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:49.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:49.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:49.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:49.040 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:49.040 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:49.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:49.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:49.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:49.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:49.075 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:49.076 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:49.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:49.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:49.211 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:14:49.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:49.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:49.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:49.261 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:49.682 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:14:50.155 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:14:50.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:50.261 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:50.261 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:50.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:50.623 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:14:51.094 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:14:51.138 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:51.141 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.142 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:51.142 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:51.157 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:51.157 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:51.157 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:51.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.158 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:51.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:51.158 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:51.158 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:51.187 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:51.194 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:51.194 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:51.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.194 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:51.262 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:51.262 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:51.262 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:51.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:51.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.359 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:51.359 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:51.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:51.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:51.375 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:51.376 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.376 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:51.376 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:51.376 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:51.376 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:51.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:51.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:51.431 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:51.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:51.565 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:14:52.036 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:14:52.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:52.263 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:52.263 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:52.263 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:52.506 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:14:52.977 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:14:53.263 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:14:53.264 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:14:53.264 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:14:53.264 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:14:53.451 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:14:53.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:53.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:53.543 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:53.543 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:53.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:53.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:53.560 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:53.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:53.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:53.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:53.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:53.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:53.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:53.592 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:14:53.592 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:14:53.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:53.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:53.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:53.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:53.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:53.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:53.861 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:14:53.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:53.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:53.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:53.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:53.877 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:53.877 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:53.877 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:53.877 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:53.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:53.923 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:14:53.930 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:14:53.930 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:14:53.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:53.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:54.395 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:14:54.868 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:14:55.341 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:14:55.813 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:14:56.190 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:56.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.194 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:56.194 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:56.195 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:14:56.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:56.212 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:56.212 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:56.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:56.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:56.214 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:56.214 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:56.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:56.238 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:14:56.238 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:14:56.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.238 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.285 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:14:56.509 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:56.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.514 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:56.514 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:56.514 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:14:56.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:56.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:56.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:56.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:56.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:56.533 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:56.533 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:56.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:56.573 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:14:56.573 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:14:56.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:56.758 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:14:57.230 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:14:57.703 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:14:58.176 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:14:58.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:58.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:58.603 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:58.603 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:58.603 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:14:58.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:58.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:58.613 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:58.614 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:58.614 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:58.614 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:58.614 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:58.614 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:58.648 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:14:58.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:58.656 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:58.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:58.657 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:58.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:59.119 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:14:59.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:59.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:59.277 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:59.277 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:59.293 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:14:59.293 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:14:59.293 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:14:59.294 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:59.295 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:59.295 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:59.295 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:14:59.295 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:14:59.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:14:59.300 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:14:59.300 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:14:59.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:59.301 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:14:59.590 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:15:00.061 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:15:00.531 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:15:00.968 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:00.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:00.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:00.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:00.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:00.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:00.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:00.992 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:00.992 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:00.992 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:00.992 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:00.992 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:00.998 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:00.999 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:00.999 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:00.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:00.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:01.002 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:15:01.473 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:15:01.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:01.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:01.631 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:01.631 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:01.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:01.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:01.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:01.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:01.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:01.652 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:01.652 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:01.652 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:01.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:01.717 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:01.717 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:01.717 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:01.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:01.946 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:15:02.419 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:15:02.891 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:15:03.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:03.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:03.331 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:03.332 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:03.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:03.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:03.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:03.353 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:03.353 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:03.353 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:03.353 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:03.353 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:03.357 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:03.359 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:03.359 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:03.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:03.359 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:03.362 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:15:03.833 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:15:04.306 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:15:04.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:04.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:04.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:04.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:04.625 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:04.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:04.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:04.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:04.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:04.634 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:04.634 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:04.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:04.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:04.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:04.683 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:04.684 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:04.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:04.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:04.779 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:15:05.251 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:15:05.724 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:15:06.197 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:15:06.669 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:15:07.141 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:15:07.614 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:15:08.086 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:15:08.559 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:15:09.032 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:15:09.503 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:15:09.975 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:15:10.449 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:15:10.921 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:15:11.394 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:15:11.866 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:15:12.339 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:15:12.812 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:15:13.284 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:15:13.756 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:15:14.229 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:15:14.702 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:15:15.174 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:15:15.647 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:15:16.120 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:15:16.592 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:15:17.065 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:15:17.538 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:15:18.010 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:15:18.484 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:15:18.956 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:15:19.429 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:15:19.902 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:15:20.374 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:15:20.846 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:15:21.318 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:15:21.791 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:15:22.263 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:15:22.736 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 03:15:23.209 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 03:15:23.681 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 03:15:24.153 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 03:15:24.625 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 03:15:24.637 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:24.637 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:24.637 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:24.640 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:24.640 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:24.641 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:15:29.647 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:29.647 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:29.647 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:29.647 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:29.647 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:29.647 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:29.655 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:29.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:29.657 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:29.657 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:29.657 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:15:29.661 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:15:29.661 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:15:29.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:29.662 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:29.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:29.662 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:15:29.662 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:29.662 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:15:29.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:29.666 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:15:29.666 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:15:29.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:29.666 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:29.667 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:29.667 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:15:29.667 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:29.667 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:15:29.667 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:29.670 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:15:29.670 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:15:29.671 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:29.671 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:29.671 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:29.671 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:15:29.671 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:29.671 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:15:29.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:29.676 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:15:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:15:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:15:29.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:15:29.676 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.677 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:15:29.677 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:15:29.677 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:15:29.678 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.679 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:29.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.680 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:29.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:29.682 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:15:30.160 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:15:30.209 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:15:30.211 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.211 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:15:30.213 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:15:30.232 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.232 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.233 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:30.237 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.237 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.237 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.237 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:30.237 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:30.255 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.321 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.321 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.340 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.340 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:30.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.342 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.342 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.342 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:30.342 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:30.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.478 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.501 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.501 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:30.502 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.502 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.502 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.502 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:30.502 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:30.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.544 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:30.544 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:30.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.545 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.631 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:15:30.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.639 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.641 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.641 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.642 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:30.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:30.662 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.662 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.662 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.662 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:30.662 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:30.670 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.672 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:30.672 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:30.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:30.682 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:30.682 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:30.683 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:30.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.755 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.757 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:30.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:30.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:30.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:30.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.777 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:30.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:30.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:30.814 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:30.814 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:30.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:30.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:31.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:31.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:31.033 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:31.033 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:31.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:31.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.036 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:31.036 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:31.036 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:31.036 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:31.045 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:31.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:31.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:31.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.102 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:15:31.259 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:31.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:31.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:31.281 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:31.281 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:31.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:31.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:31.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:31.283 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:31.283 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:31.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:31.348 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:31.348 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:31.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.421 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:31.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.426 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:31.426 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:31.427 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:31.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:31.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:31.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:31.445 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.445 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:31.446 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:31.446 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:31.446 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:31.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:31.487 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:31.487 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:31.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.487 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.574 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:15:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:31.660 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:31.661 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:31.662 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:31.662 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:31.670 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:31.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:31.671 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:31.671 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:31.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:31.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:31.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:31.675 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:15:31.676 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:31.676 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:31.676 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:31.676 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=432 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:31.676 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=432 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:31.676 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=432 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:31.676 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=432 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:31.677 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=432 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:31.677 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=432 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:31.677 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=432 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:36.678 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:36.679 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:36.679 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:36.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:36.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:36.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:36.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:36.689 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:36.690 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:36.690 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:36.690 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:15:36.692 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:15:36.692 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:15:36.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:36.692 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:36.692 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:36.692 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:15:36.692 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:36.693 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:15:36.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:36.694 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:15:36.694 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:15:36.694 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:36.694 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:36.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:36.694 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:15:36.694 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:36.694 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:15:36.694 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:36.695 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:15:36.695 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:15:36.695 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:36.695 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:36.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:36.695 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:15:36.695 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:36.695 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:15:36.695 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.697 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:15:36.698 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:15:36.698 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:15:36.698 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:36.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:36.702 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:15:37.179 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:15:37.226 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:15:37.228 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:15:37.230 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:15:37.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:37.254 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:37.254 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:37.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:37.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:37.259 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:37.259 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:37.260 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:37.260 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:37.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:37.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:37.283 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:37.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:37.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:37.650 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:15:37.700 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:37.701 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:37.701 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:37.701 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:38.122 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:15:38.141 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:38.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.145 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:38.145 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:38.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:38.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:38.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:38.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.163 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:38.163 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:38.163 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:38.163 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:38.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:38.167 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:38.167 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:38.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.590 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:15:38.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:38.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.618 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:38.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:38.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:38.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:38.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:38.638 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.638 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:38.638 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:38.638 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:38.638 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:38.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:38.690 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:38.690 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:38.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:38.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:38.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:38.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:38.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:39.062 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:15:39.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:39.340 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:39.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:39.342 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:39.356 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:39.356 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:39.356 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:39.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.357 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:39.358 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:39.358 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:39.358 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:39.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:39.393 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:39.394 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:39.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.535 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:15:39.703 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:39.703 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:39.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:39.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:39.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:39.824 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:39.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:39.827 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:39.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:39.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:39.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:39.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.845 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:39.845 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:39.845 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:39.845 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:39.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:39.866 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:39.866 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:39.866 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:39.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:39.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:39.994 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:39.994 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:39.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:39.995 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:39.995 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:39.995 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:39.995 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:39.995 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:40.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:40.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:40.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:40.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.006 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:15:40.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:40.447 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.448 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:40.449 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:40.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:40.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:40.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:40.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.469 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:40.469 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:40.469 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:40.469 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:40.474 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:40.475 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:40.475 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:40.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.478 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:15:40.704 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:40.704 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:40.705 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:40.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:40.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:40.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:40.873 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:40.873 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:40.880 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:40.880 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:40.880 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:40.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.882 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:40.882 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:40.882 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:40.882 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:40.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:40.897 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:40.897 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:40.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:40.948 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:15:41.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:41.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:41.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:41.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:41.343 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:41.352 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:41.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:41.352 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:41.353 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:41.355 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:41.355 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:41.355 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:41.355 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:15:41.355 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:41.355 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:41.355 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:41.355 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1008 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:41.355 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1008 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:41.355 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1008 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:41.355 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1008 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:41.355 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1008 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:41.355 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1008 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:41.355 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1008 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:15:46.359 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:46.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:46.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:46.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:46.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:46.359 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:46.376 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:46.377 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:46.378 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:46.378 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:46.379 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:15:46.383 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:15:46.384 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:15:46.384 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:46.384 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:46.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:46.385 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:15:46.386 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:46.386 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:15:46.386 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:46.388 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:15:46.388 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:15:46.388 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:46.388 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:46.388 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:46.388 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:15:46.389 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:46.389 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:15:46.389 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:46.391 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:15:46.391 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:15:46.391 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:46.391 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:46.391 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:46.391 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:15:46.392 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:46.392 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:15:46.392 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.395 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:15:46.395 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:15:46.395 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:15:46.395 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:46.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:46.400 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:15:46.878 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:15:46.923 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:15:46.926 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:15:46.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:46.928 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:15:46.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:46.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:46.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:46.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:46.955 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:46.955 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:46.955 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:46.955 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:46.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:46.981 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:46.981 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:46.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:46.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.057 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.057 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:47.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.058 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.058 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.058 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:47.059 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:47.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.117 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.117 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.156 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.159 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.160 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.160 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.178 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.178 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.178 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:47.180 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.180 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.180 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.180 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:47.180 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:47.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.216 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:47.216 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:47.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.216 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.296 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.300 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.300 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.300 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:47.319 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.319 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:47.320 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.320 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.320 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.321 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:47.321 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:47.345 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:15:47.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.357 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:47.357 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:47.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:47.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:47.398 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:47.398 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:47.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.415 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.417 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.417 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.417 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:47.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:47.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.436 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:47.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:47.485 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.574 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.575 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.593 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:47.595 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.595 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.595 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.595 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:47.595 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:47.628 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.637 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.809 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.816 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:15:47.830 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:47.830 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:47.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:47.831 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.832 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:47.832 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:47.832 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:47.832 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:47.864 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:47.870 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:47.870 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:47.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:47.871 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:48.288 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:15:48.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:48.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:48.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:48.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:48.440 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:48.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:48.444 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:48.444 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:48.444 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:48.462 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:48.462 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:48.463 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:48.464 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:48.464 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:48.464 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:48.464 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:48.464 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:48.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:48.469 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:48.469 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:48.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:48.469 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:48.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:48.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:48.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:48.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:48.679 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:48.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:48.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:48.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:48.686 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:48.687 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:48.687 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:48.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:48.687 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:48.687 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:48.687 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:48.687 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:15:53.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:15:53.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:15:53.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:53.715 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:53.715 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:53.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:53.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:15:53.721 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:53.721 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:53.722 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:15:53.722 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:15:53.730 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:15:53.730 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:15:53.730 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:53.730 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:53.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:15:53.731 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:15:53.731 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:15:53.731 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:15:53.731 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:53.736 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:15:53.737 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:15:53.737 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:53.737 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:53.737 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:15:53.737 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:15:53.738 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:15:53.738 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:15:53.738 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:53.743 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:15:53.743 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:15:53.743 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:53.743 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:15:53.744 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:15:53.744 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:15:53.744 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:15:53.744 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:15:53.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:53.752 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:15:53.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:15:53.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:15:53.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:15:53.752 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:15:53.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.753 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:15:53.753 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:15:53.753 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:15:53.754 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:15:53.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.754 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.754 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:15:53.754 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.755 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:15:53.756 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:15:53.758 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:15:54.235 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:15:54.286 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:15:54.288 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:15:54.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:54.290 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:15:54.307 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:54.308 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:54.308 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:54.311 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:54.311 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:54.311 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:54.312 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:54.312 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:54.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:54.338 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:54.339 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:54.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:54.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:54.706 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:15:54.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:54.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:54.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:54.760 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:55.179 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:15:55.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:55.202 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:55.204 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:55.204 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:55.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:55.220 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:55.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:55.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:55.221 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:55.221 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:55.221 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:55.221 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:55.275 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:55.282 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:55.282 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:55.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:55.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:55.651 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:15:55.759 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:55.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:55.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:55.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:56.122 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:15:56.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:56.160 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:56.162 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:56.162 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:56.174 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:56.174 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:56.174 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:56.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:56.175 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:56.175 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:56.175 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:56.175 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:56.217 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:56.224 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:56.225 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:56.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:56.226 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:56.595 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:15:56.760 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:56.760 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:56.761 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:56.762 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:57.068 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:15:57.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:57.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:57.373 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:57.373 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:57.373 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:57.388 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:57.388 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:57.388 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:57.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:57.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:57.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:57.390 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:57.390 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:57.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:57.394 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:57.394 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:15:57.394 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:57.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:57.539 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:15:57.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:57.761 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:57.762 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:57.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:58.013 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:15:58.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:58.332 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:58.334 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:58.334 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:58.334 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:15:58.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:58.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:58.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:58.352 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:58.352 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:58.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:58.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:58.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:58.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:58.390 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:58.390 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:58.390 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:58.391 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:58.484 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:15:58.762 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:15:58.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:15:58.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:15:58.765 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:15:58.957 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:15:58.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:59.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:59.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:59.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:59.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:59.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:59.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:59.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:59.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:59.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:59.024 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:59.024 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:59.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:59.059 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:59.059 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:59.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:59.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:59.429 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:15:59.900 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:15:59.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:59.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:59.942 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:59.942 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:59.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:15:59.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:15:59.963 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:15:59.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:59.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:15:59.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:15:59.965 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:15:59.965 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:15:59.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:15:59.999 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:15:59.999 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:15:59.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:15:59.999 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:00.371 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:16:00.844 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:16:01.316 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:16:01.771 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:01.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:01.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:01.776 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:01.776 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:01.788 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:16:01.794 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:01.794 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:01.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:01.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:01.795 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:01.795 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:01.795 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:01.795 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:01.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:01.841 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:01.841 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:01.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:01.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:02.259 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:16:02.733 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:16:03.205 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:16:03.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:03.663 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:03.665 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:03.665 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:03.666 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:03.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:03.674 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:03.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:03.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:03.675 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:03.675 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:03.675 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:03.675 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:03.675 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:16:03.675 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:03.675 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:08.682 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:08.682 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:08.682 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:08.682 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:08.682 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:08.682 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:08.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:08.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:08.692 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:08.693 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:08.693 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:16:08.697 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:16:08.698 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:16:08.698 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:08.698 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:08.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:08.699 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:16:08.700 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:08.700 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:16:08.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:08.701 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:16:08.701 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:16:08.702 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:08.702 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:08.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:08.702 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:16:08.702 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:08.702 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:16:08.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:08.704 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:16:08.705 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:16:08.705 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:08.705 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:08.705 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:08.705 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:16:08.705 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:08.705 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:16:08.705 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:08.708 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:16:08.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:16:08.708 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:16:08.708 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:16:08.708 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:16:08.708 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:16:08.709 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:16:08.709 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:16:08.709 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.709 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:08.710 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:08.714 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:16:09.191 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:16:09.235 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:16:09.237 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:16:09.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.239 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:16:09.263 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:09.263 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:09.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:09.268 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.268 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:09.268 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:09.268 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:09.268 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:09.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.297 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:09.297 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:09.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.414 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:09.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:09.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:09.430 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:09.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:09.431 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.431 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:09.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:09.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:09.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:09.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.479 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:09.479 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:16:09.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.610 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:09.612 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:09.612 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:09.630 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:09.630 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:09.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:09.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:09.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:09.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:09.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:09.658 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:16:09.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.671 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:09.671 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:09.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.711 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:09.712 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:09.712 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:09.712 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:09.885 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.888 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:09.888 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:09.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:09.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:09.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:09.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.898 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:09.898 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:09.898 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:09.898 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:09.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:09.947 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:09.947 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:09.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:09.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:10.129 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:16:10.601 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:16:10.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:10.713 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:10.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:10.713 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:10.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:10.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:10.758 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:10.758 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:10.758 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:10.763 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:10.764 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:10.764 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:16:15.771 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:15.771 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:15.771 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:15.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:15.771 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:15.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:15.783 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:15.784 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:15.784 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:15.785 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:15.785 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:16:15.789 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:16:15.789 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:16:15.789 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:15.789 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:15.790 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:15.790 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:16:15.790 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:15.790 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:16:15.790 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:15.793 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:16:15.793 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:16:15.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:15.793 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:15.793 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:15.793 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:16:15.793 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:15.793 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:16:15.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:15.795 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:16:15.795 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:16:15.795 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:15.795 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:15.796 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:15.796 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:16:15.796 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:15.796 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:16:15.796 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:15.801 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:16:15.801 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:16:15.801 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:16:15.801 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:16:15.801 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:15.802 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.803 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:16:15.803 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:16:15.803 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:16:15.803 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:16:15.803 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.803 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.803 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.804 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:15.808 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:16:16.285 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:16:16.335 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:16:16.337 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:16:16.339 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:16:16.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:16.363 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:16.363 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:16.363 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:16.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.367 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:16.367 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:16.367 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:16.367 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:16.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:16.383 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:16.383 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:16.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.384 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:16.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.492 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:16.492 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:16.508 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:16.508 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:16.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:16.509 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.509 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:16.509 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:16.509 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:16.509 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:16.518 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:16.520 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:16.520 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:16:16.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:16.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.669 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:16.669 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:16.669 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:16.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:16.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:16.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:16.689 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.689 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:16.689 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:16.689 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:16.689 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:16.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:16.708 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:16.708 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:16.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.752 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:16:16.807 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:16.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:16.808 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:16.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:16.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:16.977 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:16.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:16.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:17.001 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:17.001 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:17.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:17.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:17.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:17.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:17.003 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:17.003 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:17.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:17.039 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:17.039 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:17.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:17.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:17.223 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:16:17.695 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:16:17.809 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:17.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:17.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:17.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:17.848 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:17.851 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:17.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:17.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:17.852 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:17.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:17.857 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:17.857 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:17.857 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:17.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:17.858 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:17.858 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:17.858 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:17.858 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:16:17.858 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:17.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:22.866 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:22.867 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:22.867 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:22.867 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:22.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:22.868 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:22.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:22.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:22.876 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:22.876 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:22.876 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:16:22.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:16:22.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:16:22.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:22.881 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:22.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:22.881 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:16:22.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:22.881 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:16:22.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:22.885 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:16:22.885 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:16:22.885 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:22.885 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:22.885 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:22.886 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:16:22.886 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:22.886 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:16:22.886 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:22.889 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:16:22.889 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:16:22.890 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:22.890 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:22.890 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:22.890 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:16:22.890 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:22.890 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:16:22.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:22.895 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:16:22.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:16:22.895 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:16:22.895 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:16:22.895 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:16:22.895 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.896 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:16:22.896 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:16:22.896 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:16:22.896 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.897 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:22.901 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:16:23.379 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:16:23.426 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:16:23.428 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:16:23.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:23.430 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:16:23.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:23.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:23.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:23.457 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.457 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:23.458 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:23.458 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:23.458 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:23.476 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:23.481 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:23.482 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:23.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:23.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.583 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:23.583 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:23.600 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:23.601 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:23.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:23.602 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:23.602 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:23.602 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:23.602 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:23.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:23.614 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:23.615 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:16:23.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.759 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:23.762 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:23.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:23.764 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:23.782 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:23.782 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:23.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:23.783 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.783 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:23.783 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:23.783 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:23.783 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:23.798 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:23.802 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:23.802 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:23.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.802 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:23.851 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:16:23.900 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:23.900 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:23.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:23.901 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:24.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:24.079 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:24.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:24.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:24.099 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:24.099 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:24.099 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:24.101 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:24.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:24.101 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:24.101 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:24.101 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:24.154 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:24.161 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:24.161 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:24.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:24.162 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:24.322 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:16:24.796 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:16:24.901 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:24.901 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:24.901 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:24.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:24.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:24.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:24.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:24.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:24.949 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:24.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:24.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:24.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:24.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:24.961 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:24.961 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:24.961 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:24.961 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:24.961 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:24.961 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:24.961 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:16:29.966 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:29.966 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:29.966 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:29.966 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:29.966 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:29.966 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:29.974 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:29.975 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:29.975 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:29.975 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:29.975 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:16:29.978 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:16:29.978 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:16:29.978 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:29.978 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:29.979 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:29.979 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:16:29.979 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:29.979 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:16:29.979 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:29.980 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:16:29.980 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:16:29.981 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:29.981 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:29.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:29.981 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:16:29.981 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:29.981 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:16:29.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:29.983 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:16:29.983 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:16:29.983 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:29.983 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:29.983 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:29.983 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:16:29.983 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:29.983 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:16:29.983 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:16:29.986 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:16:29.986 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:16:29.986 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:29.991 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:16:30.469 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:16:30.512 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:16:30.514 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:16:30.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:30.516 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:16:30.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:30.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:30.541 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:30.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:30.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:30.544 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:30.544 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:30.566 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:30.574 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:30.574 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:30.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.575 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.688 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:30.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.692 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:30.692 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:30.710 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:30.710 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:30.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:30.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:30.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:30.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:30.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:30.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:30.761 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:30.761 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:16:30.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:30.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:30.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:30.932 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:30.935 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:16:30.948 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:30.948 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:30.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:30.949 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.949 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:30.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:30.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:30.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:30.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:30.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:30.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:30.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:30.988 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:30.988 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:30.988 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:30.988 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:31.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:31.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:31.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:31.164 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:31.182 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:31.182 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:31.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:31.184 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:31.184 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:31.184 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:31.184 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:31.184 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:31.215 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:31.219 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:31.219 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:31.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:31.220 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:31.405 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:16:31.878 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:16:31.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:31.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:31.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:31.990 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:32.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:32.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:32.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:32.038 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:32.038 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:32.046 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:32.046 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:32.047 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:32.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:32.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:32.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:32.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:32.048 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:32.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:32.048 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:16:37.053 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:37.054 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:37.054 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:37.054 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:37.054 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:37.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:37.061 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:37.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:37.063 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:37.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:37.063 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:16:37.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:16:37.069 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:16:37.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:37.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:37.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:37.070 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:16:37.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:37.070 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:16:37.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:37.072 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:16:37.072 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:16:37.072 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:37.072 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:37.072 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:37.072 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:16:37.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:37.073 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:16:37.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:37.075 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:16:37.075 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:16:37.075 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:37.075 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:37.075 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:37.075 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:16:37.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:37.076 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:16:37.076 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.080 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:16:37.081 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:16:37.081 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:16:37.081 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:37.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:37.085 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:16:37.564 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:16:37.609 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:16:37.611 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:16:37.612 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:16:37.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:37.628 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:37.628 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:37.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:37.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:37.636 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:37.636 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:37.637 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:37.637 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:37.660 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:37.669 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:37.669 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:37.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:37.669 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:37.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:37.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:37.982 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:37.983 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:38.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:38.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:38.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:38.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:38.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:38.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:38.003 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:38.003 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:38.036 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:16:38.037 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:38.039 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:38.039 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:16:38.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:38.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:38.085 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:38.085 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:38.085 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:38.085 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:38.509 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:16:38.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:38.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:38.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:38.524 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:38.524 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:38.542 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:38.542 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:38.542 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:38.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:38.544 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:38.545 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:38.545 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:38.545 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:38.549 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:38.550 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:38.551 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:38.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:38.551 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:38.982 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:16:39.086 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:39.086 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:39.087 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:39.087 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:39.454 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:16:39.609 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:39.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:39.612 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:39.613 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:39.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:39.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:39.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:39.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:39.631 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:39.631 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:39.631 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:39.631 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:39.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:39.635 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:39.635 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:39.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:39.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:39.925 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:16:40.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:40.088 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:40.088 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:40.088 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:40.398 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:16:40.870 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:16:41.088 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:41.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:41.089 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:41.089 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:41.343 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:16:41.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:41.661 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:41.663 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:41.663 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:41.663 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:41.672 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:41.672 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:41.672 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:41.672 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:41.674 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:41.674 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:41.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:41.674 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:41.674 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:41.674 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:41.674 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:16:41.675 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:41.675 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:41.675 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:41.675 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:41.675 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:41.675 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:46.678 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:46.678 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:46.678 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:46.679 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:46.679 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:46.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:46.688 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:46.690 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:46.690 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:46.691 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:46.691 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:16:46.696 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:16:46.697 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:16:46.697 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:46.697 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:46.698 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:46.698 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:16:46.699 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:46.699 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:16:46.700 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:46.701 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:16:46.702 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:16:46.702 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:46.702 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:46.702 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:46.703 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:16:46.703 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:46.703 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:16:46.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:46.706 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:16:46.706 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:16:46.707 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:46.707 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:46.707 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:46.707 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:16:46.707 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:46.707 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:16:46.708 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:46.712 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:16:46.712 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:16:46.712 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:16:46.712 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.713 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.714 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:16:46.714 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:16:46.714 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:16:46.714 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:16:46.714 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:16:46.714 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.714 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.715 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:46.716 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:46.719 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:16:47.196 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:16:47.253 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:16:47.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:47.256 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:16:47.258 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:16:47.283 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:47.283 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:47.284 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:47.291 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:47.291 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:47.291 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:47.291 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:47.291 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:47.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:47.346 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:47.346 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:47.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:47.346 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:47.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:47.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:47.656 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:47.656 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:47.666 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:16:47.674 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:47.674 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:47.674 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:47.677 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:47.677 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:47.677 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:47.677 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:47.677 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:47.712 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:47.717 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:47.717 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:16:47.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:47.718 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:47.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:47.719 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:47.720 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:47.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:48.139 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:16:48.236 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:48.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:48.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:48.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:48.241 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:48.258 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:48.258 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:48.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:48.261 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:48.261 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:48.261 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:48.261 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:48.261 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:48.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:48.280 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:48.280 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:48.280 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:48.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:48.611 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:16:48.719 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:48.720 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:48.721 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:48.721 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:49.082 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:16:49.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:49.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:49.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:49.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:49.256 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:49.256 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:49.256 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:49.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:49.258 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:49.258 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:49.258 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:49.258 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:49.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:49.264 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:49.264 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:49.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:49.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:49.553 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:16:49.721 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:49.721 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:49.723 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:49.723 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:50.027 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:16:50.499 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:16:50.722 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:50.722 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:50.724 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:50.724 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:50.971 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:16:51.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:51.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:51.291 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:51.291 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:51.291 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:51.300 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:51.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:51.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:51.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:51.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:51.303 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:51.303 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:51.303 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:16:51.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:51.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:51.303 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:51.303 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:51.303 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:51.303 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:51.303 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:51.303 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:51.303 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:51.303 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:16:56.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:16:56.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:16:56.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:56.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:56.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:56.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:56.315 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:16:56.317 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:56.317 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:56.317 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:16:56.317 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:16:56.321 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:16:56.322 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:16:56.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:56.322 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:56.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:16:56.323 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:16:56.324 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:16:56.324 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:16:56.325 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:56.327 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:16:56.327 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:16:56.327 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:56.328 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:56.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:16:56.328 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:16:56.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:16:56.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:16:56.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:56.331 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:16:56.332 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:16:56.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:56.332 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:16:56.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:16:56.332 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:16:56.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:16:56.332 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:16:56.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:56.336 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:16:56.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:16:56.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:16:56.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:16:56.336 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:16:56.337 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:16:56.337 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:16:56.337 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.338 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:16:56.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:16:56.342 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:16:56.819 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:16:56.865 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:16:56.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:56.868 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:16:56.871 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:16:56.892 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:56.892 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:56.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:56.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:56.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:56.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:56.900 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:56.900 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:56.915 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:56.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:56.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:56.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:56.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.234 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:57.236 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:57.238 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:57.252 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:57.252 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:57.252 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:57.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:57.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:57.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:57.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:57.291 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:16:57.293 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:57.296 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:57.296 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:16:57.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.296 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:57.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:57.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:57.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:57.763 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:16:57.775 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:57.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:57.780 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:57.780 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:16:57.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:57.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:57.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:57.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.804 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:57.804 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:57.804 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:57.804 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:57.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:57.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:57.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:57.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:57.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:58.236 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:16:58.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:58.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:58.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:58.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:58.709 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:16:58.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:58.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:58.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:58.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:58.887 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:16:58.887 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:16:58.887 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:16:58.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:58.889 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:16:58.889 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:16:58.889 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:16:58.889 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:16:58.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:16:58.953 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:16:58.953 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:16:58.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:58.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:16:59.180 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:16:59.343 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:16:59.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:16:59.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:16:59.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:16:59.652 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:17:00.126 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:17:00.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:00.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:00.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:00.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:00.598 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:17:00.916 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:00.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:00.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:00.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:00.920 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:00.930 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:00.930 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:00.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:00.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:00.932 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:00.932 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:00.932 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:00.932 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:17:00.932 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:00.932 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:00.932 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:00.932 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:00.932 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:00.932 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:00.932 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:00.932 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:00.932 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:05.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:05.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:05.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:05.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:05.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:05.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:05.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:05.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:05.945 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:05.945 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:05.945 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:17:05.948 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:17:05.948 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:17:05.948 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:05.948 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:05.949 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:05.949 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:17:05.949 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:05.949 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:17:05.949 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:05.950 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:17:05.950 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:17:05.951 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:05.951 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:05.951 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:05.951 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:17:05.951 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:05.951 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:17:05.951 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:05.952 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:17:05.953 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:17:05.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:05.953 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:05.953 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:05.953 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:17:05.953 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:05.953 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:17:05.953 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.955 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:17:05.956 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:17:05.956 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:17:05.956 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:05.960 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:17:06.439 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:17:06.478 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:17:06.480 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:17:06.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:06.483 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:17:06.502 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:06.502 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:06.503 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:06.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:06.510 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:06.510 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:06.510 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:06.510 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:06.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:06.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:06.544 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:06.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:06.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:06.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:06.857 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:06.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:06.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:06.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:06.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:06.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:06.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:06.880 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:06.880 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:06.880 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:06.880 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:06.910 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:17:06.912 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:06.917 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:06.917 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:17:06.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:06.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:06.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:06.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:06.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:06.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:07.383 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:17:07.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:07.398 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:07.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:07.399 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:07.399 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:07.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:07.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:07.418 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:07.420 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:07.420 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:07.420 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:07.420 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:07.420 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:07.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:07.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:07.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:07.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:07.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:07.855 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:17:07.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:07.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:07.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:07.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:08.326 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:17:08.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:08.483 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:08.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:08.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:08.498 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:08.499 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:08.499 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:08.501 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:08.501 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:08.501 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:08.501 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:08.501 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:08.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:08.510 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:08.510 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:08.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:08.510 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:08.798 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:17:08.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:08.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:08.962 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:08.962 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:09.272 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:17:09.745 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:17:09.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:09.963 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:09.963 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:09.963 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:10.218 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:17:10.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:10.538 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:10.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:10.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:10.539 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:10.548 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:10.548 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:10.548 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:10.549 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:10.551 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:10.551 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:10.551 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:10.551 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:10.551 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:17:10.551 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:10.551 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:10.551 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:10.551 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:10.551 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:10.551 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:10.551 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:10.551 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=992 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:15.555 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:15.555 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:15.555 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:15.555 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:15.555 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:15.555 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:15.563 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:15.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:15.563 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:15.564 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:15.564 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:17:15.567 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:17:15.567 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:17:15.568 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:15.568 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:15.568 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:15.569 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:17:15.569 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:15.570 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:17:15.570 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:15.571 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:17:15.572 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:17:15.572 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:15.572 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:15.572 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:15.572 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:17:15.573 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:15.573 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:17:15.573 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:15.575 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:17:15.575 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:17:15.575 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:15.576 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:15.576 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:15.576 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:17:15.576 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:15.576 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:17:15.576 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.581 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:17:15.582 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:17:15.582 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:17:15.582 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.582 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.584 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:15.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:15.586 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:17:16.064 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:17:16.112 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:17:16.113 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:17:16.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:16.115 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:17:16.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:16.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:16.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:16.148 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:16.148 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:16.149 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:16.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:16.152 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:16.152 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:16.153 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:16.153 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:16.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:16.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:16.153 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:17:16.153 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:16.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:16.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:16.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:16.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:16.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:16.154 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=123 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:21.155 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:21.155 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:21.156 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:21.156 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:21.156 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:21.156 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:21.163 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:21.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:21.164 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:21.164 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:21.164 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:17:21.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:17:21.167 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:17:21.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:21.167 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:21.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:21.167 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:17:21.167 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:21.167 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:17:21.168 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:21.171 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:17:21.171 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:17:21.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:21.172 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:21.172 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:21.172 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:17:21.172 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:21.172 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:17:21.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:21.176 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:17:21.176 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:17:21.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:21.176 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:21.176 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:21.176 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:17:21.176 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:21.176 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:17:21.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:21.182 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:17:21.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:17:21.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:17:21.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:17:21.182 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:17:21.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.183 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:17:21.183 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:17:21.183 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:17:21.183 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:21.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:21.188 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:17:21.667 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:17:21.717 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:17:21.719 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:17:21.720 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:21.721 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:17:21.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:21.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:21.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:21.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:21.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:21.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:21.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:21.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:21.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:21.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:21.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:21.785 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:21.785 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:21.785 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:21.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:21.785 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:21.785 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:21.785 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:17:21.785 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=129 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:26.792 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:26.792 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:26.792 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:26.792 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:26.792 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:26.792 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:26.800 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:26.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:26.802 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:26.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:26.803 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:17:26.808 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:17:26.808 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:17:26.808 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:26.808 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:26.809 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:26.809 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:17:26.809 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:26.809 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:17:26.809 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:26.812 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:17:26.813 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:17:26.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:26.813 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:26.813 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:26.813 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:17:26.813 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:26.813 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:17:26.813 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:26.816 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:17:26.816 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:17:26.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:26.816 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:26.816 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:26.816 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:17:26.816 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:26.816 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:17:26.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.820 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:17:26.820 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:17:26.820 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:17:26.821 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.821 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.822 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:26.822 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:26.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.822 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:26.825 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:17:27.303 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:17:27.350 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:17:27.352 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:17:27.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:27.354 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:17:27.379 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:27.379 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:27.380 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:27.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:27.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:27.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:27.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:27.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:27.400 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:27.400 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:27.400 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:27.400 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:27.400 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:27.400 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:17:32.405 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:32.405 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:32.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:32.406 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:32.406 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:32.406 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:32.420 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:32.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:32.422 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:32.423 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:32.423 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:17:32.424 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:17:32.424 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:17:32.424 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:32.424 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:32.424 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:32.425 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:17:32.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:32.425 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:17:32.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:32.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:17:32.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:17:32.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:32.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:32.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:32.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:17:32.428 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:32.428 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:17:32.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:32.430 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:17:32.430 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:17:32.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:32.430 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:32.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:32.430 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:17:32.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:32.430 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:17:32.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:32.433 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:17:32.434 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:17:32.434 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:17:32.434 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:17:32.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:32.436 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:32.436 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:17:32.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:37.444 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:37.444 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:37.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:37.444 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:37.444 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:37.444 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:37.467 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:37.469 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:37.469 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:37.470 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:37.470 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:17:37.475 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:17:37.476 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:17:37.476 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:37.476 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:37.477 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:37.477 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:17:37.478 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:37.478 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:17:37.479 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:37.481 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:17:37.481 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:17:37.482 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:37.482 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:37.482 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:37.482 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:17:37.483 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:37.483 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:17:37.483 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:37.484 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:17:37.484 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:17:37.484 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:37.484 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:37.484 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:37.484 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:17:37.485 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:37.485 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:17:37.485 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:37.487 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:17:37.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:17:37.488 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:17:37.488 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:17:37.488 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:17:37.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:37.493 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:17:37.971 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:17:38.013 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:17:38.015 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:17:38.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:38.018 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:17:38.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:38.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:38.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:38.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:38.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:38.049 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:38.049 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:38.050 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:38.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:38.072 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:38.072 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:38.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:38.072 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:38.442 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:17:38.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:38.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:38.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:38.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:38.914 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:17:39.023 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:39.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:39.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:39.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:39.044 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:39.044 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:39.044 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:39.046 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:39.046 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:39.046 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:39.046 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:39.046 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:39.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:39.051 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:39.051 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:39.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:39.051 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:39.386 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:17:39.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:39.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:39.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:39.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:39.859 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:17:39.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:39.986 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:39.987 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:39.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:40.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:40.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:40.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:40.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:40.004 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:40.004 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:40.004 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:40.004 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:40.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:40.049 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:40.050 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:40.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:40.050 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:40.331 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:17:40.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:40.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:40.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:40.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:40.804 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:17:40.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:40.960 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:40.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:40.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:40.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:40.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:40.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:40.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:40.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:40.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:40.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:40.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:41.039 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:41.041 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:41.041 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:41.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:41.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:41.275 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:17:41.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:41.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:41.495 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:41.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:41.748 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:17:41.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:41.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:41.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:41.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:41.940 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:41.940 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:41.940 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:41.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:41.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:41.942 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:41.942 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:41.942 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:41.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:41.990 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:41.990 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:41.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:41.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:42.221 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:17:42.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:42.496 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:42.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:42.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:42.540 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:42.541 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:42.541 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:42.559 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:42.559 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:42.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:42.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:42.561 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:42.561 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:42.561 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:42.561 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:42.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:42.605 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:42.605 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:17:42.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:42.605 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:42.693 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:17:43.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:43.165 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:43.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:43.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:43.166 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:43.167 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:17:43.183 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:43.183 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:43.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:43.185 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:43.185 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:43.185 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:43.185 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:43.185 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:43.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:43.217 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:43.217 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=3, maio=3, ma_len=4
2026-03-01 03:17:43.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:43.217 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:43.639 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:17:43.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:43.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:43.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:43.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:43.772 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:43.787 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:43.787 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:43.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:43.788 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:43.788 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:43.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:43.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:43.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:43.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:43.826 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:43.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:43.833 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:43.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:43.833 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:44.110 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:17:44.423 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:44.426 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:44.427 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:44.427 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:44.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:44.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:44.442 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:44.443 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:44.444 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:44.444 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:44.444 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:44.444 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:44.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:44.494 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:44.495 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:44.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:44.495 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:44.582 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:17:45.053 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:17:45.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:45.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:45.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:45.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:45.124 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:45.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:45.125 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.126 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:45.126 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:45.126 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:45.126 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:45.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:45.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:45.149 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:45.149 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:45.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.149 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.524 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:17:45.687 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:45.690 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.690 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:45.690 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:45.706 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:45.706 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:45.707 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:45.709 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.709 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:45.709 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:45.709 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:45.709 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:45.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:45.768 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:45.768 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:17:45.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:45.997 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:17:46.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:46.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:46.384 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:46.384 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:46.384 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:46.399 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:46.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:46.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:46.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:46.401 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:46.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:46.402 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:46.402 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:46.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:46.413 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:46.414 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:17:46.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:46.414 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:46.469 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:17:46.943 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:17:47.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:47.035 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:47.036 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:47.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:47.036 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:47.055 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:47.055 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:47.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:47.057 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:47.057 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:47.057 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:47.057 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:47.057 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:47.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:47.088 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:47.088 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:47.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:47.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:47.417 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:17:47.888 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:17:47.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:47.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:47.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:47.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:47.899 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:47.918 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:47.918 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:47.918 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:47.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:47.920 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:47.920 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:47.920 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:47.920 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:47.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:47.935 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:47.935 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:47.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:47.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:48.360 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:17:48.833 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:17:48.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:48.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:48.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:48.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:48.859 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:48.877 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:48.877 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:48.877 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:48.879 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:48.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:48.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:48.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:48.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:48.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:48.924 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:48.924 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:48.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:48.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:49.306 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:17:49.777 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:17:49.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:49.825 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:49.826 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:49.826 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:49.826 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:49.845 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:49.845 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:49.846 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:49.847 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:49.848 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:49.848 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:49.848 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:49.848 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:49.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:49.873 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:49.873 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:49.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:49.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:50.248 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:17:50.720 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:17:50.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:50.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:50.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:50.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:50.785 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:50.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:50.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:50.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:50.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:50.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:50.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:50.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:50.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:50.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:50.814 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:50.814 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:50.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:50.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:51.193 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:17:51.666 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:17:51.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:51.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:51.750 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:51.750 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:51.751 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:51.759 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:51.759 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:51.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:51.760 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:51.760 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:51.760 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:51.760 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:51.760 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:51.806 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:51.808 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:51.808 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:51.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:51.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:52.138 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:17:52.609 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:17:52.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:52.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:52.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:52.712 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:52.712 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:52.720 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:52.720 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:52.721 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:52.722 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:52.722 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:52.722 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:52.722 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:52.722 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:52.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:52.748 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:52.748 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:52.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:52.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:53.080 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:17:53.553 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:17:53.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:53.676 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:53.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:53.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:53.677 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:53.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:53.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:53.687 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:17:53.688 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:53.688 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:17:53.688 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:17:53.688 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:17:53.688 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:17:53.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:53.743 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:17:53.744 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:17:53.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:53.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:54.025 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:17:54.497 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:17:54.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:17:54.635 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:17:54.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:17:54.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:17:54.636 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:17:54.645 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:54.645 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:54.646 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:54.646 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:54.648 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:54.648 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:54.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:54.648 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:17:54.648 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:54.648 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:54.648 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:54.648 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:54.648 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:54.649 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:54.649 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:54.649 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:54.649 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:17:59.652 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:17:59.652 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:17:59.652 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:59.652 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:59.652 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:59.652 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:59.660 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:17:59.661 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:59.661 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:59.662 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:17:59.662 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:17:59.665 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:17:59.666 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:17:59.666 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:59.666 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:59.667 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:17:59.667 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:17:59.668 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:17:59.668 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:17:59.668 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:17:59.669 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:17:59.669 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:17:59.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:59.670 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:59.670 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:17:59.670 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:17:59.670 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:17:59.670 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:17:59.670 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:17:59.672 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:17:59.673 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:17:59.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:59.673 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:17:59.673 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:17:59.673 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:17:59.673 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:17:59.673 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:17:59.673 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:17:59.676 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:17:59.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:17:59.676 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:17:59.676 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:17:59.676 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:17:59.676 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:17:59.677 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:17:59.677 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:17:59.677 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.677 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:17:59.678 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:17:59.682 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:18:00.159 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:18:00.202 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:18:00.204 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:18:00.205 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:00.206 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:18:00.224 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:00.224 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:00.225 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:18:00.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:00.231 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:00.231 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:18:00.231 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:18:00.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:00.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:00.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:00.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.264 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:00.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.507 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:00.507 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:00.520 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:00.520 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:00.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:18:00.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.522 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:00.522 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:00.522 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:18:00.522 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:18:00.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:00.533 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:00.533 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:00.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.533 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.630 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:18:00.679 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:18:00.679 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:18:00.680 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:18:00.680 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:18:00.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:00.756 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.757 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:00.757 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:00.776 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:00.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:00.777 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:18:00.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.778 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:00.778 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:00.778 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:18:00.778 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:18:00.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:00.819 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:00.820 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:00.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:00.820 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:01.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:01.019 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:01.020 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:01.020 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:01.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:01.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:01.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:18:01.030 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:01.030 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:01.030 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:01.030 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:18:01.030 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:18:01.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:01.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:18:01.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:18:01.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:01.049 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:01.102 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:18:01.276 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:18:01.279 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:18:01.279 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:18:01.279 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:18:01.287 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:18:01.287 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:18:01.287 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:18:01.288 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:18:01.288 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:18:01.288 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:18:01.288 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:18:01.288 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:18:01.288 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:18:01.288 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:18:01.288 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:18:06.294 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:18:06.294 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:18:06.294 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:18:06.294 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:18:06.294 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:18:06.294 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:18:06.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:18:06.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:18:06.305 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:06.306 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:18:06.306 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:18:06.310 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:18:06.310 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:18:06.311 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:18:06.311 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:06.311 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:18:06.312 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:18:06.312 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:18:06.313 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:18:06.313 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:18:06.315 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:18:06.315 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:18:06.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:18:06.316 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:06.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:18:06.317 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:18:06.317 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:18:06.317 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:18:06.318 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:18:06.319 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:18:06.319 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:18:06.320 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:18:06.320 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:06.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:18:06.320 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:18:06.320 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:18:06.320 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:18:06.320 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:18:06.325 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:18:06.325 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:18:06.327 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:18:06.327 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:18:06.327 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.329 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:06.329 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:06.329 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:06.332 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:18:06.810 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:18:07.282 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:18:07.757 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:18:08.229 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:18:08.704 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:18:09.176 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:18:09.652 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:18:10.124 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:18:10.599 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:18:11.071 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:18:11.546 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:18:12.018 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:18:12.494 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:18:12.966 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:18:13.441 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:18:13.913 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:18:14.388 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:18:14.860 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:18:15.336 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:18:15.808 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:18:16.283 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:18:16.755 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:18:17.230 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:18:17.702 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:18:18.178 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:18:18.650 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:18:19.125 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:18:19.597 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:18:20.072 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:18:20.544 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:18:21.020 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:18:21.492 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:18:21.966 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:18:22.438 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:18:22.910 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:18:23.385 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:18:23.857 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:18:24.333 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:18:24.805 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:18:25.280 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:18:25.752 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:18:26.228 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:18:26.699 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:18:27.175 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:18:27.647 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:18:28.122 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:18:28.594 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:18:29.070 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:18:29.542 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:18:30.017 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:18:30.350 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:18:30.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:18:30.351 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:18:30.351 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:18:30.351 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:18:30.351 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:18:30.352 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:18:30.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5174 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:18:30.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5174 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:18:30.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5174 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:18:30.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5174 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:18:30.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5174 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:18:30.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5174 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:18:30.352 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=5174 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:18:35.357 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:18:35.357 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:18:35.357 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:18:35.357 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:18:35.357 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:18:35.357 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:18:35.362 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:18:35.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:18:35.363 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:35.363 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:18:35.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:18:35.366 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:18:35.366 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:18:35.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:18:35.367 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:35.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:18:35.367 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:18:35.368 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:18:35.368 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:18:35.368 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:18:35.369 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:18:35.369 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:18:35.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:18:35.369 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:35.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:18:35.369 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:18:35.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:18:35.369 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:18:35.370 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:18:35.371 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:18:35.372 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:18:35.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:18:35.372 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:18:35.372 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:18:35.372 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:18:35.372 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:18:35.372 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:18:35.372 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:18:35.374 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:18:35.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:18:35.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:18:35.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:18:35.374 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:18:35.375 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:18:35.375 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:18:35.375 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:18:35.376 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:18:35.380 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:18:35.858 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:18:36.330 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:18:36.804 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:18:37.276 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:18:37.748 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:18:38.222 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:18:38.694 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:18:39.166 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:18:39.641 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:18:40.113 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:18:40.589 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:18:41.061 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:18:41.536 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:18:42.008 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:18:42.483 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:18:42.955 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:18:43.431 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:18:43.907 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:18:44.379 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:18:44.854 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:18:45.326 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:18:45.801 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:18:46.275 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:18:46.749 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:18:47.221 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:18:47.696 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:18:48.168 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:18:48.643 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:18:49.115 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:18:49.591 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:18:50.063 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:18:50.538 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:18:51.010 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:18:51.484 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:18:51.956 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:18:52.428 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:18:52.902 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:18:53.374 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:18:53.846 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:18:54.321 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:18:54.793 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:18:55.269 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:18:55.733 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:18:56.196 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:18:56.664 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:18:57.127 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:18:57.591 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:18:58.054 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:18:58.517 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:18:58.980 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:18:59.444 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:18:59.907 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:19:00.370 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:19:00.833 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:19:01.297 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:19:01.760 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:19:02.223 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:19:02.692 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:19:03.167 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:19:03.639 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:19:04.114 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:19:04.588 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:19:05.062 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:19:05.531 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:19:06.004 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:19:06.476 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:19:06.952 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:19:07.426 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:19:07.899 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:19:08.371 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:19:08.846 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:19:09.318 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:19:09.789 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 03:19:10.265 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 03:19:10.736 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 03:19:11.211 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 03:19:11.683 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 03:19:12.154 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 03:19:12.401 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:12.628 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 03:19:13.101 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 03:19:13.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:13.572 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 03:19:14.046 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 03:19:14.404 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:14.519 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 03:19:14.990 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 03:19:15.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:15.461 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 03:19:15.935 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 03:19:16.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:16.408 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 03:19:16.879 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 03:19:17.353 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 03:19:17.406 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:17.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:19:17.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:19:17.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:19:17.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:19:17.408 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:19:17.408 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:19:17.409 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:19:22.414 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:19:22.415 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:19:22.415 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:19:22.415 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:19:22.415 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:19:22.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:19:22.421 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:19:22.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:19:22.422 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:22.422 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:19:22.422 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:19:22.425 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:19:22.425 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:19:22.425 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:19:22.425 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:22.425 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:19:22.426 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:19:22.426 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:19:22.426 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:19:22.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:22.427 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:19:22.427 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:19:22.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:19:22.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:22.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:19:22.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:19:22.428 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:19:22.428 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:19:22.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:22.429 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:19:22.429 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:19:22.429 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:19:22.429 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:22.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:19:22.429 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:19:22.429 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:19:22.430 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:19:22.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:19:22.432 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:19:22.432 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:19:22.432 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:19:22.432 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:22.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:22.437 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:19:22.916 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:19:22.951 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:19:22.952 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:22.954 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:19:22.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:22.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:22.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:22.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:19:22.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:22.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:22.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:22.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:19:22.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:19:23.009 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:23.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:23.022 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:23.022 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:23.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:23.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:23.388 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:19:23.435 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:23.435 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:23.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:23.435 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:23.860 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:19:23.874 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:19:24.333 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:19:24.436 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:24.436 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:24.436 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:24.437 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:24.806 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:19:25.278 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:19:25.437 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:25.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:25.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:25.438 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:25.751 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:19:26.224 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:19:26.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:26.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:26.439 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:26.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:26.696 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:19:27.167 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:19:27.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:27.251 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:27.251 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:27.251 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:27.269 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:27.269 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:27.269 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:19:27.271 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:27.271 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:27.271 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:27.271 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:19:27.271 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:19:27.305 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:27.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:27.319 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:19:27.319 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:19:27.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:27.319 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:27.440 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:27.440 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:27.440 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:27.440 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:27.640 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:19:28.113 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:19:28.586 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:19:29.059 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:19:29.532 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:19:30.004 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:19:30.478 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:19:30.950 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:19:31.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:31.350 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:31.351 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:31.351 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:31.351 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:19:31.368 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:31.368 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:31.368 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:19:31.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:31.370 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:31.370 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:31.370 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:19:31.370 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:19:31.422 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:19:31.423 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:31.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:31.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:31.435 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:31.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:31.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:31.857 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:19:31.893 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:19:32.364 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:19:32.837 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:19:33.309 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:19:33.781 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:19:34.252 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:19:34.725 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:19:35.160 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:35.163 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:35.163 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:35.163 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:35.180 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:35.180 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:35.181 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:19:35.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:35.182 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:35.182 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:35.182 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:19:35.182 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:19:35.189 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:35.191 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:35.192 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:19:35.192 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:19:35.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:35.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:35.197 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:19:35.669 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:19:36.143 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:19:36.528 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:19:36.616 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:19:37.088 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:19:37.477 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:19:37.559 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:19:37.947 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:19:38.032 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:19:38.505 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:19:38.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:38.900 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:38.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:38.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:38.901 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:19:38.911 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:38.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:38.912 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:38.912 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:38.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:19:38.914 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:19:38.914 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:19:38.915 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:19:38.915 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:19:38.915 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:19:38.915 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:19:43.918 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:19:43.918 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:19:43.918 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:19:43.918 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:19:43.918 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:19:43.918 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:19:43.926 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:19:43.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:19:43.927 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:43.927 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:19:43.927 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:19:43.930 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:19:43.930 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:19:43.931 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:19:43.931 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:43.931 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:19:43.931 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:19:43.932 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:19:43.932 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:19:43.932 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:43.933 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:19:43.933 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:19:43.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:19:43.933 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:43.933 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:19:43.933 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:19:43.933 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:19:43.933 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:19:43.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:43.935 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:19:43.935 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:19:43.935 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:19:43.935 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:19:43.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:19:43.935 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:19:43.936 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:19:43.936 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:19:43.936 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:19:43.938 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:19:43.939 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:19:43.939 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:19:43.939 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.940 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:19:43.940 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:19:43.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.940 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:19:43.943 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:19:44.421 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:19:44.463 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:19:44.465 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:44.468 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:19:44.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:44.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:44.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:44.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:19:44.496 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:44.496 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:44.496 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:44.496 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:19:44.496 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:19:44.515 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:44.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:44.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:44.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:44.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:44.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:44.894 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:19:44.900 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:44.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:44.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:44.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:44.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:45.367 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:19:45.379 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:45.382 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:19:45.840 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:19:45.865 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:45.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:45.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:45.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:45.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:46.313 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:19:46.345 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:46.786 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:19:46.825 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:46.944 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:46.944 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:46.944 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:46.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:47.259 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:19:47.312 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:47.731 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:19:47.791 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:47.945 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:47.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:47.945 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:47.945 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:48.202 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:19:48.271 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:48.675 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:19:48.751 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:48.946 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:19:48.947 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:19:48.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:19:48.947 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:19:49.148 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:19:49.238 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:49.621 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:19:49.718 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:50.094 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:19:50.198 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:50.567 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:19:50.684 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:51.039 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:19:51.164 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:51.512 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:19:51.644 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:51.985 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:19:52.130 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:52.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:52.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:52.137 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:52.138 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:52.153 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:19:52.153 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:19:52.153 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:19:52.155 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:52.155 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:19:52.155 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:19:52.155 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:19:52.155 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:19:52.167 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:52.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:19:52.179 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:19:52.179 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:19:52.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:52.179 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:19:52.458 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:19:52.851 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:52.931 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:19:53.330 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:53.404 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:19:53.816 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:53.875 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:19:54.296 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:54.346 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:19:54.777 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:54.819 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:19:55.257 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:55.293 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:19:55.743 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:55.764 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:19:56.222 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:56.237 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:19:56.703 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:56.710 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:19:57.183 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:19:57.188 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:57.657 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:19:57.673 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:58.130 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:19:58.154 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:58.604 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:19:58.638 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:59.076 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:19:59.118 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:19:59.550 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:19:59.599 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:00.023 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:20:00.085 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:00.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:00.091 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:00.091 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:00.091 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:00.091 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:20:00.106 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:00.106 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:00.106 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:00.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:00.108 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:00.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:00.108 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:00.108 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:00.112 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:00.114 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:00.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:00.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:00.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:00.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:00.459 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:00.495 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:20:00.930 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:00.932 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:20:00.966 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:20:01.400 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:01.437 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:20:01.871 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:01.908 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:20:02.342 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:02.381 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:20:02.813 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:02.854 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:20:03.289 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:03.326 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:20:03.760 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:03.797 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:20:04.231 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:04.270 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:20:04.702 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:04.742 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:20:05.178 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:05.214 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:20:05.649 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:05.685 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:20:06.120 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:06.156 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:20:06.590 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:06.629 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:20:07.061 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:07.102 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:20:07.538 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:07.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:07.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:07.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:07.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:07.561 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:07.561 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:07.562 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:07.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:07.563 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:07.563 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:07.563 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:07.563 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:07.569 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:07.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:07.573 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:20:07.573 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:20:07.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:07.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:07.573 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:20:07.963 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:08.046 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:20:08.434 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:08.519 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:20:08.909 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:08.911 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:20:08.991 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:20:09.380 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:09.464 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:20:09.850 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:09.937 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:20:10.327 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:10.409 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:20:10.797 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:10.800 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:20:10.882 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:20:11.268 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:11.355 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:20:11.745 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:11.748 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:20:11.827 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:20:12.215 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:12.300 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:20:12.686 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:12.689 [DEBUG] fake_trx.py:269 (MS@172.18.36.22:6700) Recv SETTA cmd
2026-03-01 03:20:12.773 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:20:13.162 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:13.246 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:20:13.634 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:13.719 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:20:14.109 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:14.191 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:20:14.580 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:14.664 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:20:15.051 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:15.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:15.058 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:15.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:15.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:15.059 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:20:15.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:15.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:15.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:15.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:15.072 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:15.072 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:15.072 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:15.072 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:20:15.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:15.072 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:15.072 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:15.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:15.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:15.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:15.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:15.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:15.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=6721 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:20.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:20.077 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:20.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:20.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:20.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:20.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:20.084 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:20.086 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:20.086 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:20.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:20.087 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:20:20.092 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:20:20.093 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:20:20.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:20.093 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:20.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:20.093 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:20:20.093 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:20.093 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:20:20.094 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:20.097 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:20:20.098 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:20:20.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:20.098 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:20.098 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:20.098 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:20:20.098 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:20.098 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:20:20.099 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:20.102 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:20:20.102 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:20:20.102 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:20.102 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:20.102 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:20.102 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:20:20.103 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:20.103 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:20:20.103 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:20.108 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:20:20.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:20:20.108 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:20:20.108 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:20:20.108 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:20:20.108 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:20:20.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:20:20.109 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:20:20.109 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:20:20.109 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.111 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:20.114 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:20:20.592 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:20:20.637 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:20:20.638 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:20.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:20.639 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:20:20.650 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:20.650 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:20.650 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:20.652 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:20.652 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:20.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:20.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:20.653 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:20.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:20.696 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:20.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:20.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:20.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:21.062 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:20:21.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:21.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:21.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:21.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:21.535 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:20:22.008 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:20:22.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:22.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:22.115 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:22.115 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:22.479 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:20:22.790 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:22.792 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:22.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:22.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:22.815 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:22.815 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:22.815 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:22.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:22.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:22.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:22.816 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:22.816 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:22.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:22.858 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:22.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:22.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:22.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:22.951 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:20:23.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:23.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:23.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:23.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:23.424 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:20:23.897 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:20:24.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:24.117 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:24.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:24.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:24.368 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:20:24.841 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:20:24.956 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:24.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:24.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:24.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:24.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:24.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:24.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:24.983 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:24.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:24.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:24.983 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:24.983 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:25.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:25.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:25.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:25.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:25.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:25.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:25.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:25.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:25.118 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:25.314 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:20:25.786 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:20:26.257 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:20:26.730 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:20:27.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:27.124 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:27.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:27.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:27.138 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:27.138 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:27.138 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:27.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:27.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:27.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:27.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:27.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:27.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:27.143 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:27.143 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:20:27.143 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:27.143 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:27.143 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:27.143 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:27.144 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:27.144 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:32.144 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:32.144 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:32.144 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:32.144 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:32.144 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:32.144 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:32.151 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:32.152 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:32.152 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:32.153 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:32.153 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:20:32.157 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:20:32.157 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:20:32.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:32.158 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:32.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:32.159 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:20:32.159 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:32.160 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:20:32.160 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:32.162 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:20:32.162 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:20:32.163 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:32.163 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:32.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:32.164 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:20:32.164 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:32.164 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:20:32.164 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:32.166 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:20:32.166 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:20:32.166 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:32.166 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:32.166 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:32.166 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:20:32.167 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:32.167 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:20:32.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:32.170 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:20:32.170 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:20:32.170 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:20:32.170 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:20:32.170 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:20:32.171 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:20:32.171 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:20:32.171 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.171 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.172 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:32.176 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:20:32.652 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:20:32.698 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:20:32.701 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:32.702 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:32.703 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:20:32.728 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:32.728 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:32.728 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:32.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:32.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:32.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:32.732 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:32.732 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:32.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:32.751 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:20:32.751 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:20:32.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:32.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:33.124 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:20:33.175 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:33.175 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:33.175 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:33.175 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:33.597 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:20:34.071 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:20:34.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:34.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:34.176 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:34.176 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:34.543 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:20:34.851 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:34.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:34.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:34.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:34.858 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:20:34.876 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:34.876 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:34.876 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:34.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:34.878 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:34.878 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:34.878 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:34.878 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:34.923 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:34.931 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:20:34.931 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:20:34.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:34.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:35.014 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:20:35.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:35.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:35.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:35.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:35.486 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:20:35.960 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:20:36.179 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:36.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:36.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:36.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:36.432 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:20:36.906 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:20:37.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:37.020 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:37.025 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:37.026 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:37.026 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:20:37.035 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:37.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:37.035 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:37.035 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:37.039 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:37.039 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:37.039 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:37.039 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:37.040 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:20:37.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:37.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:37.040 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:37.040 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:37.040 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:37.040 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:37.040 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:37.040 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1051 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:42.040 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:42.040 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:42.040 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:42.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:42.040 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:42.040 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:42.047 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:42.047 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:42.047 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:42.048 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:42.048 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:20:42.051 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:20:42.051 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:20:42.051 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:42.051 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:42.051 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:42.051 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:20:42.052 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:42.052 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:20:42.052 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:42.055 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:20:42.056 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:20:42.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:42.056 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:42.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:42.056 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:20:42.056 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:42.056 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:20:42.056 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:42.060 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:20:42.060 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:20:42.060 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:42.060 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:42.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:42.060 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:20:42.060 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:42.060 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:20:42.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:20:42.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:20:42.067 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:20:42.067 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:20:42.067 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.068 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:42.069 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:42.072 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:20:42.550 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:20:42.597 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:20:42.598 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:42.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:42.600 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:20:42.621 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:42.621 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:42.621 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:42.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:42.628 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:42.628 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:42.628 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:42.628 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:42.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:42.657 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:42.657 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:42.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:42.658 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:43.020 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:20:43.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:43.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:43.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:43.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:43.493 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:20:43.966 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:20:44.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:44.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:44.072 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:44.072 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:44.438 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:20:44.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:44.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:44.756 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:44.756 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:44.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:44.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:44.772 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:44.774 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:44.774 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:44.774 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:44.774 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:44.774 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:44.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:44.816 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:44.816 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:44.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:44.816 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:44.911 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:20:45.071 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:45.072 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:45.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:45.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:45.383 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:20:45.854 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:20:46.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:46.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:46.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:46.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:46.325 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:20:46.798 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:20:46.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:46.899 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:46.903 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:46.903 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:46.919 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:46.919 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:46.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:46.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:46.921 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:46.921 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:46.921 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:46.921 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:46.930 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:46.932 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:46.932 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:46.932 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:46.933 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:47.075 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:47.075 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:47.075 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:47.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:47.270 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:20:47.743 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:20:48.216 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:20:48.689 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:20:49.008 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:49.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:49.015 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:49.015 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:49.022 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:49.023 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:49.023 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:49.023 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:20:54.030 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:54.030 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:54.030 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:54.030 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:54.030 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:54.030 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:54.042 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:54.043 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:54.044 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:54.044 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:20:54.044 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:20:54.048 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:20:54.048 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:20:54.048 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:54.049 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:54.049 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:54.049 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:20:54.050 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:20:54.050 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:20:54.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:54.052 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:20:54.052 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:20:54.053 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:54.053 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:54.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:54.054 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:20:54.054 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:20:54.054 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:20:54.054 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:54.056 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:20:54.056 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:20:54.056 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:54.056 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:20:54.056 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:54.057 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:20:54.057 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:20:54.057 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:20:54.057 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.061 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:20:54.061 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:20:54.061 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:20:54.062 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:20:54.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:20:54.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:20:54.066 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:20:54.544 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:20:54.584 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:20:54.585 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:20:54.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:54.587 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:20:54.596 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:54.596 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:54.596 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:54.599 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:54.599 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:54.599 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:54.599 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:54.599 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:54.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:54.649 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:20:54.649 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:20:54.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:54.649 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:55.013 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:20:55.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:55.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:55.065 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:55.065 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:55.487 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:20:55.959 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:20:56.066 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:56.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:56.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:56.067 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:56.433 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:20:56.758 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:56.760 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:56.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:56.768 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:56.768 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:20:56.786 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:56.786 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:56.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:20:56.787 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:56.787 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:20:56.788 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:20:56.788 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:20:56.788 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:20:56.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:56.805 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:20:56.805 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:20:56.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:56.806 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:56.903 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:20:57.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:57.067 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:57.067 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:57.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:57.375 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:20:57.849 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:20:58.068 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:58.068 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:58.068 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:58.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:58.322 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:20:58.794 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:20:58.892 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:20:58.894 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:20:58.899 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:20:58.899 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:20:58.899 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:20:58.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:20:58.908 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:20:58.909 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:20:58.909 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:20:58.913 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:20:58.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:20:58.913 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:20:58.913 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:20:58.913 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:20:58.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:20:58.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:20:58.913 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1048 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:58.913 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1048 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:58.913 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1048 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:58.913 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1048 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:58.913 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1048 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:58.913 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1048 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:20:58.913 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1048 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:03.915 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:03.916 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:03.916 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:03.916 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:03.916 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:03.916 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:03.919 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:03.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:03.919 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:03.919 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:03.919 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:03.920 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:03.920 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:03.920 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:03.920 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:03.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:03.920 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:03.921 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:03.921 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:03.921 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:03.921 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:03.922 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:03.923 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:03.923 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:03.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:03.923 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:03.923 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:03.923 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:03.923 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:03.923 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:03.923 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:03.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:03.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:03.925 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:03.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:03.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:04.407 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:04.452 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:04.454 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:04.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:04.456 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:04.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:04.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:04.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:04.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:04.485 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:04.485 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:04.485 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:04.485 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:04.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:04.513 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:04.514 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:04.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:04.514 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:04.878 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:04.928 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:04.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:04.928 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:04.928 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:05.351 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:21:05.823 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:21:05.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:05.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:05.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:05.929 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:06.297 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:21:06.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:06.669 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:06.673 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:06.673 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:06.680 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:06.681 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:06.681 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:06.681 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:11.689 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:11.689 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:11.689 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:11.689 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:11.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:11.689 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:11.692 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:11.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:11.692 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:11.692 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:11.692 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:11.693 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:11.693 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:11.693 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:11.693 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:11.693 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:11.694 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:11.694 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:11.694 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:11.694 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:11.695 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:11.696 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:11.696 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:11.696 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:11.696 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:11.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:11.696 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:11.696 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:11.696 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:11.696 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:11.698 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:11.698 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:11.698 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.698 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:11.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.699 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:11.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.699 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:11.699 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:11.703 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:12.182 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:12.220 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:12.221 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:12.222 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:12.222 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:12.241 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:12.241 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:12.241 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:12.247 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:12.247 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:12.247 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:12.247 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:12.247 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:12.281 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:12.289 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:21:12.289 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:21:12.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:12.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:12.652 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:12.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:12.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:12.702 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:12.702 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:13.125 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:21:13.597 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:21:13.702 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:13.702 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:13.703 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:13.703 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:14.068 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:21:14.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:14.479 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:14.482 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:14.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:14.482 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:21:14.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:14.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:14.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:14.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:14.495 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:14.495 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:14.495 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:14.495 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:14.495 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:14.495 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:14.495 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:19.498 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:19.498 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:19.498 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:19.498 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:19.498 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:19.498 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:19.507 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:19.509 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:19.509 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:19.510 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:19.510 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:19.514 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:19.515 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:19.515 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:19.515 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:19.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:19.516 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:19.517 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:19.517 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:19.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:19.519 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:19.519 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:19.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:19.520 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:19.520 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:19.520 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:19.520 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:19.520 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:19.521 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:19.522 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:19.522 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:19.522 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:19.522 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:19.522 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:19.523 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:19.523 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:19.523 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:19.523 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.526 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:19.527 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:19.527 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:19.527 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.527 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:19.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:19.531 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:20.010 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:20.050 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:20.052 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:20.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:20.054 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:20.084 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:20.084 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:20.085 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:20.131 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.131 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:20.131 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:20.131 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:20.131 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:20.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:20.157 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:20.158 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:20.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.158 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.478 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:20.522 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:20.529 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:20.529 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:20.530 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:20.530 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:20.531 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:20.531 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:20.546 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:20.546 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:20.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:20.556 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.556 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:20.556 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:20.556 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:20.556 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:20.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:20.570 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:20.570 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:20.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.570 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.942 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:20.944 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:20.949 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:21:20.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:20.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:20.961 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:20.961 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:20.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:20.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:20.962 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:20.962 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:20.962 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:20.962 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:20.962 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:20.962 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:20.962 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:20.962 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:20.962 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:20.962 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:20.962 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:20.962 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:20.962 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:25.969 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:25.969 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:25.969 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:25.969 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:25.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:25.969 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:25.976 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:25.977 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:25.977 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:25.978 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:25.978 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:25.981 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:25.981 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:25.981 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:25.981 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:25.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:25.982 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:25.982 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:25.982 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:25.983 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:25.983 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:25.984 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:25.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:25.984 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:25.984 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:25.984 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:25.984 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:25.984 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:25.984 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:25.986 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:25.986 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:25.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:25.986 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:25.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:25.986 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:25.986 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:25.986 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:25.986 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:25.989 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:25.989 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:25.989 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.990 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:25.994 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:26.473 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:26.507 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:26.509 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:26.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:26.510 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:26.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:26.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:26.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:26.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:26.592 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:26.592 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:26.592 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:26.592 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:26.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:26.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:26.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:26.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:26.623 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:26.946 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:26.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:26.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:26.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:26.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:26.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:26.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:26.999 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:26.999 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:27.013 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:27.013 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:27.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:27.023 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:27.023 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:27.023 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:27.023 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:27.023 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:27.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:27.038 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:27.038 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:27.038 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:27.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:27.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:27.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:27.417 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:21:27.418 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:27.418 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:27.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:27.428 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:27.428 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:27.428 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:27.430 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:27.430 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:27.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:27.430 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:27.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:27.430 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:27.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:27.431 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:27.431 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:27.431 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:27.431 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:27.431 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:27.431 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=311 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:32.435 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:32.435 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:32.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:32.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:32.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:32.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:32.445 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:32.446 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:32.447 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:32.447 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:32.447 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:32.450 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:32.450 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:32.451 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:32.451 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:32.451 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:32.451 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:32.452 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:32.452 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:32.452 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:32.453 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:32.453 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:32.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:32.453 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:32.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:32.454 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:32.454 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:32.454 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:32.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:32.456 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:32.456 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:32.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:32.456 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:32.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:32.456 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:32.456 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:32.456 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:32.456 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.459 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:32.459 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:32.459 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:32.460 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:32.460 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:32.464 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:32.942 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:32.984 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:32.986 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:32.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:32.989 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:33.012 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:33.012 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:33.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:33.060 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:33.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:33.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:33.061 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:33.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:33.089 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:33.089 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:33.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.410 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:33.453 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:33.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:33.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:33.463 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:33.463 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:33.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:33.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:33.481 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:33.482 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:33.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:33.491 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.492 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:33.492 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:33.492 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:33.492 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:33.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:33.500 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:33.500 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:33.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.881 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:21:33.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:33.917 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:33.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:33.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:33.932 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:33.933 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:33.933 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:33.933 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:33.935 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:33.935 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:33.935 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:33.935 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:33.935 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:33.935 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:33.935 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:33.935 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=320 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:33.935 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=320 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:33.935 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=320 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:33.935 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=320 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:33.935 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=320 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:33.935 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=320 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:33.935 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=320 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:38.941 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:38.941 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:38.941 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:38.941 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:38.941 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:38.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:38.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:38.949 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:38.949 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:38.950 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:38.950 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:38.952 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:38.953 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:38.953 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:38.953 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:38.953 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:38.954 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:38.954 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:38.954 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:38.954 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:38.956 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:38.956 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:38.956 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:38.956 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:38.956 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:38.956 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:38.956 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:38.956 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:38.957 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:38.958 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:38.958 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:38.958 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:38.958 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:38.958 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:38.958 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:38.959 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:38.959 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:38.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:38.961 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:38.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:38.961 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:38.961 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:38.961 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:38.961 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:38.962 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:38.962 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:38.962 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.962 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:38.967 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:39.444 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:39.487 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:39.489 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:39.491 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:39.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:39.515 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:39.515 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:39.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:39.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:39.557 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:39.558 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:39.558 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:39.558 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:39.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:39.591 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:21:39.592 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:21:39.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:39.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:39.917 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:39.965 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:39.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:39.965 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:39.965 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:40.392 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:21:40.863 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:21:40.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:40.966 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:41.337 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:21:41.810 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:21:41.966 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:41.967 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:41.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:41.967 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:42.282 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:21:42.755 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:21:42.967 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:42.968 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:42.968 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:42.968 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:43.228 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:21:43.601 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:43.601 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:43.601 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:43.601 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:43.602 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:43.602 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:43.602 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:43.602 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:43.602 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:43.602 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:43.602 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1000 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.602 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:43.602 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:43.602 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:21:43.602 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1000 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1000 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:43.603 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1001 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:21:48.609 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:48.609 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:48.609 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:48.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:48.609 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:48.609 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:48.612 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:48.612 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:48.612 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:48.612 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:48.612 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:48.613 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:48.613 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:48.613 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:48.613 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:48.613 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:48.614 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:48.614 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:48.614 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:48.614 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:48.615 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:48.616 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:48.616 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:48.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:48.616 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:48.616 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:48.616 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:48.616 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:48.616 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:48.616 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:48.618 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:48.618 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:48.618 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.618 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:48.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:48.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:48.623 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:49.101 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:49.141 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:49.142 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:49.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:49.145 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:49.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:49.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:49.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:49.206 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.206 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:49.206 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:49.206 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:49.206 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:49.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:49.248 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:49.249 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:49.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.249 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.455 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.457 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:49.464 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:49.464 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:49.479 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:49.479 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:49.480 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:49.489 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.490 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:49.490 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:49.490 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:49.490 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:49.522 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:49.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:49.530 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:49.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.530 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.573 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:49.622 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:49.622 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:49.622 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:49.622 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:49.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:49.740 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:49.747 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:49.747 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:49.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:49.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:49.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:49.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:49.760 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:49.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:49.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:49.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:49.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:49.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:49.760 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:54.765 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:54.765 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:54.765 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:54.765 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:54.765 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:54.765 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:54.778 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:54.779 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:54.779 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:54.779 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:21:54.779 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:21:54.781 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:21:54.782 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:21:54.782 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:54.782 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:54.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:54.782 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:21:54.783 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:21:54.783 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:21:54.783 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:54.783 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:21:54.784 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:21:54.784 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:54.784 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:54.784 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:54.784 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:21:54.784 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:21:54.784 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:21:54.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:54.785 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:21:54.785 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:21:54.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:54.785 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:21:54.785 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:21:54.785 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:21:54.785 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:21:54.785 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:21:54.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:21:54.788 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:21:54.788 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:21:54.788 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:21:54.788 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:21:54.792 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:21:55.270 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:21:55.308 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:21:55.310 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:21:55.311 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:21:55.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:55.326 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:55.326 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:55.327 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:21:55.351 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:55.351 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:21:55.352 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:21:55.352 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:21:55.352 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:21:55.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:21:55.370 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:21:55.370 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:21:55.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:55.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:21:55.742 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:21:55.790 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:55.791 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:55.791 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:55.791 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:56.214 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:21:56.688 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:21:56.791 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:56.792 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:56.792 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:56.792 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:57.160 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:21:57.634 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:21:57.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:57.793 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:57.793 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:57.793 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:58.106 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:21:58.579 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:21:58.793 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:58.794 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:58.794 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:58.794 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:59.052 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:21:59.375 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:21:59.375 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:21:59.376 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:21:59.379 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:21:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:21:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:21:59.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:21:59.379 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:21:59.379 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:21:59.380 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:21:59.380 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:21:59.380 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:21:59.380 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:21:59.380 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:04.386 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:04.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:04.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:04.386 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:04.389 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:04.389 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:04.389 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:04.390 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:04.390 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:04.390 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:04.391 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:04.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:04.391 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:04.391 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:04.391 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:04.391 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:04.391 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:04.391 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:04.392 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:04.392 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:04.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:04.392 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:04.392 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:04.392 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:04.392 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:04.392 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:04.392 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:04.393 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:04.393 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:04.393 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:04.393 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:04.393 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:04.393 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:04.393 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:04.393 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:04.393 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.395 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:04.396 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:04.396 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:04.396 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.396 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:04.400 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:04.878 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:04.920 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:04.922 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:04.924 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:04.924 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:04.941 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:04.941 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:04.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:04.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:04.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:04.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:04.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:04.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:05.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:05.024 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:05.024 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:05.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:05.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:05.348 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:05.398 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:05.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:05.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:05.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:05.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:05.733 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:05.740 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:05.740 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:05.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:05.752 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:05.752 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:05.753 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:05.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:05.757 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:05.757 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:05.757 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:22:05.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:05.757 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:05.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:05.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=295 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:05.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=295 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:05.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=295 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:05.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=295 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:05.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=295 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:05.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=295 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:05.758 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=295 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:10.760 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:10.760 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:10.760 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:10.760 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:10.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:10.761 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:10.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:10.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:10.770 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:10.770 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:10.770 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:10.773 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:10.773 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:10.774 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:10.774 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:10.774 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:10.775 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:10.775 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:10.775 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:10.775 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:10.776 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:10.776 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:10.776 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:10.776 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:10.777 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:10.777 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:10.777 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:10.777 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:10.777 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:10.779 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:10.779 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:10.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:10.779 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:10.779 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:10.779 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:10.779 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:10.779 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:10.779 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:10.782 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:10.782 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:10.782 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.783 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:10.787 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:11.264 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:11.311 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:11.313 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:11.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:11.315 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:11.341 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:11.341 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:11.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:11.385 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:11.385 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:11.385 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:11.386 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:11.386 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:11.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:11.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:11.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:11.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:11.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:11.734 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:11.784 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:11.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:11.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:11.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:12.117 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:12.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:12.124 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:12.125 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:12.133 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:12.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:12.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:12.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:12.134 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:12.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:12.134 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:12.134 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:12.134 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:22:12.134 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:12.134 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:17.142 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:17.142 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:17.142 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:17.142 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:17.142 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:17.142 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:17.145 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:17.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:17.145 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:17.145 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:17.145 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:17.146 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:17.146 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:17.146 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:17.146 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:17.146 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:17.146 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:17.147 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:17.147 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:17.147 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:17.147 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:17.147 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:17.147 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:17.147 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:17.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:17.148 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:17.148 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:17.148 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:17.148 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:17.149 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:17.149 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:17.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:17.149 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:17.149 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:17.149 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:17.149 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:17.149 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:17.149 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:17.151 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:17.151 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:17.151 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.151 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.152 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:17.156 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:17.633 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:17.675 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:17.677 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:17.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:17.680 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:17.705 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:17.705 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:17.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:17.732 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:17.732 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:17.732 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:17.732 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:17.732 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:17.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:17.779 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:17.779 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:17.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:17.780 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:18.102 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:18.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:18.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:18.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:18.155 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:18.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:18.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:18.494 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:18.494 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:18.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:18.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:18.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:18.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:18.508 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:18.508 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:18.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:18.508 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:22:18.508 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:18.508 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:18.508 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:18.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:18.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:18.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:18.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:18.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:18.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:18.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:23.513 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:23.513 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:23.513 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:23.513 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:23.513 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:23.513 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:23.521 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:23.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:23.523 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:23.523 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:23.523 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:23.528 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:23.528 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:23.528 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:23.528 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:23.529 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:23.529 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:23.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:23.529 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:23.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:23.531 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:23.531 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:23.531 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:23.531 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:23.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:23.532 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:23.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:23.532 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:23.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:23.535 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:23.535 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:23.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:23.535 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:23.535 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:23.535 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:23.535 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:23.535 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:23.535 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:23.539 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:23.539 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:23.539 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:23.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.540 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:23.541 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:23.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.541 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:23.544 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:24.023 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:24.071 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:24.073 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:24.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:24.075 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:24.095 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:24.095 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:24.095 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:24.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:24.111 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:24.111 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:24.111 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:24.111 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:24.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:24.169 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:22:24.169 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:22:24.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:24.170 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:24.493 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:24.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:24.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:24.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:24.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:24.966 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:22:25.016 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:25.018 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:25.026 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:25.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:25.027 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:22:25.036 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:25.036 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:25.036 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:25.037 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:25.040 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:25.041 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:25.041 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:25.041 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:22:25.041 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:25.041 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:25.041 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:25.042 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:25.042 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:25.042 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:25.042 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:25.042 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:25.042 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:25.042 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:30.043 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:30.044 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:30.044 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:30.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:30.044 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:30.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:30.057 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:30.058 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:30.058 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:30.058 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:30.058 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:30.060 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:30.060 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:30.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:30.061 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:30.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:30.061 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:30.061 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:30.061 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:30.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:30.062 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:30.063 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:30.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:30.063 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:30.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:30.063 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:30.063 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:30.063 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:30.063 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:30.064 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:30.064 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:30.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:30.064 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:30.064 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:30.064 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:30.064 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:30.064 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:30.064 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:30.066 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:30.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:30.066 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:30.066 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:30.066 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:30.066 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:30.067 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:30.067 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:30.067 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.067 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:30.071 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:30.550 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:30.587 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:30.588 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:30.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:30.589 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:30.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:30.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:30.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:30.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:30.646 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:30.647 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:30.647 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:30.647 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:30.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:30.696 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:30.696 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:30.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:30.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:31.020 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:31.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:31.070 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:31.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:31.071 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:31.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:31.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:31.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:31.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:31.421 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:31.421 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:31.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:31.422 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:31.425 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:31.426 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:31.426 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:31.426 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:31.426 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:31.426 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:31.426 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:22:31.427 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:31.427 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:31.427 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:31.427 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:31.427 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:31.427 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=294 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:36.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:36.429 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:36.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:36.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:36.429 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:36.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:36.437 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:36.438 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:36.439 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:36.439 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:36.439 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:36.443 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:36.443 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:36.444 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:36.444 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:36.444 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:36.445 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:36.445 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:36.445 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:36.445 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:36.447 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:36.447 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:36.447 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:36.447 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:36.447 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:36.447 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:36.448 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:36.448 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:36.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:36.450 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:36.450 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:36.450 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:36.450 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:36.450 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:36.450 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:36.451 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:36.451 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:36.451 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.454 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:36.454 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:36.454 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:36.455 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.455 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:36.456 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:36.459 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:36.937 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:36.979 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:36.981 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:36.983 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:36.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:37.003 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:37.003 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:37.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:37.048 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:37.048 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:37.048 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:37.049 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:37.049 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:37.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:37.084 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:22:37.084 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:22:37.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:37.084 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:37.406 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:37.457 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:37.472 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:37.472 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:37.472 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:37.880 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:22:37.930 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:37.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:37.938 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:37.938 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:37.938 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:22:37.949 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:37.950 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:37.950 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:37.950 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:37.954 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:37.954 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:37.954 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:37.954 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:37.954 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:37.954 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:37.954 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:22:37.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=323 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=323 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=323 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=323 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.955 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.956 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.956 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.956 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.956 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.956 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:37.956 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=324 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:42.957 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:42.957 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:42.957 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:42.957 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:42.957 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:42.957 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:42.965 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:42.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:42.966 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:42.966 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:42.967 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:42.969 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:42.970 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:42.970 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:42.970 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:42.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:42.971 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:42.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:42.971 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:42.971 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:42.972 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:42.972 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:42.973 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:42.973 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:42.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:42.973 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:42.973 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:42.973 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:42.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:42.975 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:42.975 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:42.975 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:42.975 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:42.975 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:42.975 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:42.975 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:42.975 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:42.975 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.978 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:42.978 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:42.978 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:42.978 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:42.979 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:42.983 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:43.462 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:43.502 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:43.504 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:43.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:43.506 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:43.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:43.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:43.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:43.532 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:43.532 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:43.532 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:43.533 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:43.533 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:43.934 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:43.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:43.981 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:43.981 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:43.981 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:44.405 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:22:44.571 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:44.676 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:44.679 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:44.679 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:44.695 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:44.695 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:44.695 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:44.696 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:44.696 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:44.697 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:44.697 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:44.697 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:44.878 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:22:44.981 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:44.982 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:44.982 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:44.982 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:45.351 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:22:45.744 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 03:22:45.823 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:22:45.858 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 03:22:45.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:45.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:45.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:45.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:45.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:45.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:45.873 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:45.873 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:45.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:45.873 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:22:45.873 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:45.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:45.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:45.873 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:45.874 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:45.874 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:45.874 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:45.874 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:45.874 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=625 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:22:50.878 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:50.878 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:50.878 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:50.878 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:50.878 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:50.878 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:50.887 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:50.888 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:50.888 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:50.889 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:22:50.889 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:22:50.893 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:22:50.893 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:22:50.893 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:50.893 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:50.893 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:50.893 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:22:50.894 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:22:50.894 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:22:50.894 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:50.897 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:22:50.897 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:22:50.897 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:50.898 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:50.898 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:50.898 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:22:50.898 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:22:50.898 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:22:50.898 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:50.901 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:22:50.901 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:22:50.901 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:50.902 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:22:50.902 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:50.902 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:22:50.902 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:22:50.902 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:22:50.902 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:22:50.908 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:22:50.908 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:22:50.908 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.908 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.909 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:22:50.910 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:22:50.913 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:22:51.389 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:22:51.440 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:22:51.442 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:22:51.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:22:51.446 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:22:51.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:51.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:51.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:22:51.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:51.472 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:51.472 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:51.472 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:22:51.472 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:22:51.859 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:22:51.912 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:51.912 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:51.913 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:51.913 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:52.332 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:22:52.804 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:22:52.913 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:52.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:52.914 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:52.914 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:53.275 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:22:53.748 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:22:53.914 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:53.915 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:53.915 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:53.915 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:54.220 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:22:54.693 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:22:54.915 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:54.916 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:54.916 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:54.916 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:55.166 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:22:55.638 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:22:55.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:55.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:55.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:55.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:56.111 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:22:56.366 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 03:22:56.373 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:22:56.373 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:22:56.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:56.373 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:22:56.584 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:22:57.056 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:22:57.529 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:22:58.003 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:22:58.475 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:22:58.949 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:22:59.337 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:22:59.337 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:22:59.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:22:59.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:22:59.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:22:59.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:22:59.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:22:59.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:22:59.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:22:59.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:22:59.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:22:59.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:22:59.343 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:23:04.349 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:04.349 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:04.349 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:04.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:04.349 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:04.349 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:04.356 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:04.357 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:04.357 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:04.357 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:04.357 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:23:04.361 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:23:04.361 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:23:04.362 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:04.362 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:04.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:04.363 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:23:04.363 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:04.363 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:23:04.363 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:04.365 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:23:04.365 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:23:04.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:04.365 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:04.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:04.365 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:23:04.366 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:04.366 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:23:04.366 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:04.368 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:23:04.368 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:23:04.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:04.368 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:04.369 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:04.369 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:23:04.369 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:04.369 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:23:04.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:04.372 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:23:04.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:23:04.372 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:23:04.372 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:23:04.372 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:23:04.372 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:23:04.373 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:23:04.373 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:23:04.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:23:04.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:04.378 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:23:04.855 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:23:04.898 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:23:04.901 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:23:04.902 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:23:04.903 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:23:04.922 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:04.922 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:04.923 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:23:04.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:04.928 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:04.928 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:04.929 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:23:04.929 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:23:05.328 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:23:05.375 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:05.376 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:05.376 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:05.376 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:05.799 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:23:06.272 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:23:06.377 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:06.377 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:06.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:06.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:06.744 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:23:07.217 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:23:07.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:07.378 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:07.378 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:07.378 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:07.690 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:23:08.162 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:23:08.378 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:08.379 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:08.379 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:08.379 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:08.635 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:23:09.108 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:23:09.380 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:09.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:09.380 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:09.381 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:09.580 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:23:09.837 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 03:23:09.842 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:09.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:09.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:09.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:10.052 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:23:10.516 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:23:10.983 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:23:11.447 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:23:11.911 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:23:12.381 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:23:12.807 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:12.807 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:12.810 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:12.810 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:12.810 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:12.810 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:12.811 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:12.811 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:12.811 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:12.811 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:23:12.811 [WARNING] transceiver.py:257 (TRX1@172.18.36.20:5700/1) RX TRXD message (ver=1 fn=1830 tn=0 bl=148 pwr=8), but transceiver is not running => dropping...
2026-03-01 03:23:12.811 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:12.811 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:12.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:12.811 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1830 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:12.811 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1830 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:12.811 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1830 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:12.811 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1830 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:12.811 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1830 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:12.811 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1830 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:17.821 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:17.821 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:17.821 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:17.821 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:17.822 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:17.822 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:17.831 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:17.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:17.833 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:17.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:17.834 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:23:17.837 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:23:17.838 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:23:17.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:17.838 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:17.838 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:17.838 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:23:17.838 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:17.838 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:23:17.838 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:17.842 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:23:17.842 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:23:17.842 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:17.842 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:17.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:17.843 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:23:17.843 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:17.843 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:23:17.843 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:17.845 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:23:17.845 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:23:17.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:17.846 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:17.846 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:17.846 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:23:17.846 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:17.846 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:23:17.846 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:17.851 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:23:17.851 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.852 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.853 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:23:17.853 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:23:17.853 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:23:17.853 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:23:17.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.853 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.853 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.853 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:23:17.853 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.855 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:17.855 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:17.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.855 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:17.858 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:23:18.336 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:23:18.386 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:23:18.388 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:23:18.390 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:23:18.390 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:23:18.415 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:18.415 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:18.416 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:23:18.421 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:18.421 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:18.421 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:18.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:23:18.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:23:18.807 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:23:18.857 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:18.860 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:18.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:18.861 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:19.279 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:23:19.752 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:23:19.860 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:19.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:19.861 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:19.862 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:20.225 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:23:20.697 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:23:20.862 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:20.862 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:20.862 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:20.863 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:21.168 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:23:21.639 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:23:21.864 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:21.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:21.864 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:21.864 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:22.111 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:23:22.584 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:23:22.865 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:22.865 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:22.865 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:22.866 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:23.056 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:23:23.316 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 03:23:23.323 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:23.323 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:23.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:23.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:23.528 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:23:24.002 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:23:24.474 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:23:24.948 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:23:25.420 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:23:25.893 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:23:26.287 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:26.288 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:26.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:26.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:26.292 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:26.292 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:26.297 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:26.297 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:26.297 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:26.297 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:26.297 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:26.297 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:26.297 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1823 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (TRX1@172.18.36.20:5700/1) RX TRXD message (ver=1 fn=1824 tn=0 bl=148 pwr=4), but transceiver is not running => dropping...
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1823 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1823 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1823 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1823 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1823 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.298 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.299 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.299 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.299 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.299 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.299 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.299 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:26.299 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1824 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:31.298 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:31.298 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:31.298 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:31.298 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:31.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:31.298 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:31.303 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:31.304 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:31.304 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:31.305 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:31.305 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:23:31.308 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:23:31.308 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:23:31.308 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:31.308 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:31.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:31.309 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:23:31.309 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:31.309 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:23:31.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:31.311 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:23:31.311 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:23:31.312 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:31.312 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:31.312 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:31.312 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:23:31.312 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:31.312 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:23:31.312 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:31.314 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:23:31.314 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:23:31.314 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:31.314 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:31.314 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:31.315 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:23:31.315 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:31.315 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:23:31.315 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:31.317 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:23:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:23:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:23:31.317 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:23:31.317 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:23:31.318 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:23:31.318 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:23:31.318 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.318 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:31.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:31.323 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:23:31.801 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:23:31.843 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:23:31.845 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:23:31.847 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:23:31.848 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:23:31.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:31.867 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:31.867 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:23:31.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:31.870 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:31.870 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:31.871 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:23:31.871 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:23:32.272 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:23:32.321 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:32.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:32.321 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:32.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:32.743 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:23:33.215 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:23:33.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:33.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:33.322 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:33.322 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:33.686 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:23:34.159 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:23:34.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:34.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:34.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:34.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:34.632 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:23:35.122 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:23:35.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:35.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:35.594 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:23:36.065 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:23:36.325 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:36.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:36.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:36.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:36.539 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:23:36.791 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 03:23:36.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:36.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:36.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:36.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:37.011 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:23:37.485 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:23:37.958 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:23:38.430 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:23:38.904 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:23:39.378 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:23:39.762 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:39.763 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:39.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:39.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:39.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:39.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:39.768 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:39.768 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:39.768 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:39.768 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:39.768 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:23:39.768 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:39.768 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:44.773 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:44.773 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:44.773 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:44.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:44.773 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:44.773 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:44.798 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:44.800 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:44.800 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:44.801 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:44.801 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:23:44.809 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:23:44.809 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:23:44.810 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:44.810 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:44.810 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:44.811 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:23:44.811 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:44.811 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:23:44.812 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:44.814 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:23:44.815 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:23:44.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:44.815 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:44.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:44.815 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:23:44.815 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:44.815 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:23:44.816 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:44.818 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:23:44.818 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:23:44.819 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:44.819 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:44.819 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:44.820 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:23:44.820 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:44.820 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:23:44.820 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.823 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:23:44.823 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:23:44.823 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:23:44.823 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.824 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:44.825 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:44.828 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:23:45.306 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:23:45.350 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:23:45.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:23:45.354 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:23:45.357 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:23:45.382 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:45.383 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:45.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:23:45.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:45.387 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:45.387 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:45.387 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:23:45.387 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:23:45.778 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:23:45.826 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:45.826 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:45.827 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:45.827 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:46.249 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:23:46.720 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:23:46.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:46.828 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:46.828 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:46.828 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:47.194 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:23:47.666 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:23:47.828 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:47.829 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:47.829 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:47.829 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:48.137 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:23:48.609 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:23:48.829 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:48.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:48.830 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:48.830 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:49.082 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:23:49.555 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:23:49.830 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:49.830 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:49.831 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:49.831 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:50.027 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:23:50.282 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD NOHANDOVER
2026-03-01 03:23:50.289 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:23:50.289 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:23:50.289 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:50.290 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:23:50.501 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:23:50.973 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:23:51.445 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:23:51.919 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:23:52.391 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:23:52.863 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:23:53.253 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:23:53.253 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:23:53.257 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:53.258 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:53.258 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:53.258 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:53.259 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:53.259 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:53.259 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:53.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:53.259 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:53.259 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:53.259 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:23:53.259 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1822 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:53.259 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1822 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:53.259 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1822 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:53.259 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1822 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:53.259 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1822 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:53.259 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1822 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:23:58.264 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:23:58.264 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:23:58.264 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:58.264 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:58.264 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:58.264 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:58.272 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:23:58.273 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:58.273 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:58.274 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:23:58.274 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:23:58.277 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:23:58.278 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:23:58.278 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:58.278 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:58.279 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:23:58.279 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:23:58.280 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:23:58.280 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:23:58.280 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:58.282 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:23:58.282 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:23:58.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:58.282 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:58.282 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:23:58.282 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:23:58.282 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:23:58.283 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:23:58.283 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:58.285 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:23:58.285 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:23:58.285 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:58.285 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:23:58.285 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:23:58.285 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:23:58.285 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:23:58.285 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:23:58.285 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:23:58.289 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:23:58.289 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:23:58.289 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:23:58.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:23:58.294 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:23:58.772 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:23:58.817 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:23:58.820 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:23:58.821 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:23:58.822 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:23:59.244 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:23:59.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:23:59.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:23:59.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:23:59.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:23:59.720 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:24:00.186 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:24:00.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:00.295 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:00.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:00.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:00.658 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:24:01.133 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:24:01.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:01.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:01.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:01.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:01.605 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:24:02.074 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:24:02.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:02.298 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:02.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:02.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:02.546 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:24:03.010 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:24:03.299 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:03.300 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:03.300 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:03.300 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:03.478 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:24:03.950 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:24:04.414 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:24:04.877 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:24:05.343 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:24:05.814 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:24:06.277 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:24:06.741 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:24:07.204 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:24:07.667 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:24:08.130 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:24:08.594 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:24:08.834 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:08.834 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:08.835 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:08.835 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:08.835 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:08.835 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:08.835 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:08.835 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:08.835 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:08.835 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:08.835 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:24:13.842 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:13.842 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:13.842 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:13.842 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:13.842 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:13.842 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:13.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:13.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:13.851 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:13.851 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:13.851 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:24:13.853 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:24:13.853 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:24:13.853 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:13.853 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:13.854 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:13.854 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:24:13.854 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:13.854 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:24:13.854 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:13.856 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:24:13.856 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:24:13.856 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:13.856 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:13.856 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:13.856 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:24:13.856 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:13.856 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:24:13.856 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:13.858 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:24:13.858 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:24:13.858 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:13.858 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:13.858 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:13.858 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:24:13.858 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:13.858 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:24:13.858 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:24:13.860 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:24:13.861 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:24:13.861 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:24:13.861 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:13.861 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:13.862 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:13.862 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:24:13.862 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:13.862 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:13.862 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.869 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:18.869 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:18.869 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:18.869 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:18.869 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:18.869 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:18.877 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:18.877 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:18.877 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:18.878 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:18.878 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:24:18.880 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:24:18.880 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:24:18.880 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:18.880 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:18.881 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:18.881 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:24:18.881 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:18.881 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:24:18.881 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:18.882 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:24:18.882 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:24:18.882 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:18.882 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:18.883 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:18.883 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:24:18.883 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:18.883 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:24:18.883 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:18.884 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:24:18.884 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:24:18.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:18.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:18.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:18.885 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:24:18.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:18.885 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:24:18.885 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:24:18.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:24:18.888 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:24:18.888 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:18.892 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:24:19.368 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:24:19.414 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:24:19.417 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:24:19.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:24:19.419 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:24:19.423 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:24:19.423 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:24:19.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:24:19.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:24:19.424 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:24:19.424 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:24:19.425 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:24:19.425 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:24:19.840 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:24:19.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:19.891 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:19.891 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:19.891 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:20.312 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:24:20.787 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:24:20.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:20.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:20.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:20.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:21.259 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:24:21.730 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:24:21.892 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:21.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:21.893 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:21.893 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:22.203 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:24:22.676 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:24:22.893 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:22.893 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:22.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:22.894 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:23.148 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:24:23.619 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:24:23.895 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:23.895 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:23.895 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:23.895 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:24.092 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:24:24.565 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:24:25.037 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:24:25.508 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:24:25.978 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:24:26.449 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:24:26.923 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:24:27.395 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:24:27.463 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:24:27.463 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:24:27.468 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:27.468 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:27.469 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:27.469 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:27.470 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:27.470 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:27.470 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:27.470 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:24:27.470 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:27.470 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:27.470 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:27.470 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:27.470 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:27.470 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:27.470 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:27.470 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:27.470 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:32.476 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:32.476 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:32.476 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:32.476 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:32.476 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:32.477 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:32.485 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:32.486 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:32.486 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:32.487 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:32.487 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:24:32.490 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:24:32.490 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:24:32.491 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:32.491 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:32.491 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:32.492 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:24:32.492 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:32.492 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:24:32.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:32.494 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:24:32.494 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:24:32.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:32.494 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:32.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:32.494 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:24:32.494 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:32.494 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:24:32.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:32.496 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:24:32.496 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:24:32.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:32.497 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:32.497 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:32.497 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:24:32.497 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:32.497 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:24:32.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.500 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:24:32.500 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:24:32.500 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:24:32.501 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:24:32.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.501 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:24:32.501 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.501 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.501 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:32.502 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:32.502 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:24:32.502 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:37.509 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:37.509 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:37.509 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:37.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:37.509 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:37.509 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:37.517 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:37.518 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:37.518 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:37.519 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:37.519 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:24:37.523 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:24:37.523 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:24:37.523 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:37.524 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:37.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:37.525 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:24:37.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:37.525 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:24:37.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:37.527 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:24:37.527 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:24:37.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:37.527 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:37.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:37.528 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:24:37.528 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:37.528 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:24:37.528 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:37.530 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:24:37.530 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:24:37.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:37.531 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:37.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:37.531 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:24:37.531 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:37.531 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:24:37.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:37.534 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:24:37.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:24:37.534 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:24:37.534 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:24:37.534 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:24:37.534 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:24:37.535 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:24:37.535 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:24:37.535 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.535 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:37.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:37.540 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:24:38.017 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:24:38.060 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:24:38.062 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:24:38.064 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:24:38.064 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:24:38.069 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:24:38.069 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:24:38.070 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:24:38.071 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:24:38.071 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:24:38.071 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:24:38.071 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:24:38.071 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:24:38.490 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:24:38.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:38.538 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:38.538 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:38.538 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:38.963 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:24:39.436 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:24:39.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:39.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:39.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:39.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:39.908 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:24:40.381 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:24:40.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:40.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:40.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:40.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:40.854 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:24:41.326 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:24:41.542 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:41.542 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:41.542 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:41.542 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:41.799 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:24:42.272 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:24:42.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:42.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:42.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:42.544 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:42.744 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:24:43.217 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:24:43.690 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:24:44.162 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:24:44.633 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:24:45.106 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:24:45.578 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:24:46.051 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:24:46.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:24:46.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:24:46.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:46.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:46.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:46.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:46.114 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:46.114 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:46.114 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:46.114 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:46.115 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:24:46.115 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:46.115 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:46.115 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1852 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:46.115 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1852 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:46.115 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1852 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:46.115 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1852 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:46.115 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1852 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:46.115 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1852 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:24:51.121 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:51.121 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:51.121 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:51.121 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:51.121 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:51.121 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:51.128 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:51.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:51.129 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:51.129 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:51.129 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:24:51.133 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:24:51.133 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:24:51.134 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:51.134 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:51.134 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:51.135 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:24:51.135 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:51.135 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:24:51.136 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:51.137 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:24:51.138 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:24:51.138 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:51.138 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:51.138 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:51.138 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:24:51.139 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:51.139 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:24:51.139 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:51.140 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:24:51.141 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:24:51.141 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:51.141 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:51.141 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:51.141 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:24:51.141 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:51.141 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:24:51.141 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:24:51.145 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:24:51.145 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:24:51.145 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.145 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.146 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:24:51.146 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.146 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.146 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:51.147 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:51.147 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:24:51.147 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:56.153 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:24:56.153 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:24:56.154 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:56.154 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:56.154 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:56.154 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:56.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:24:56.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:56.163 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:56.163 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:24:56.163 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:24:56.166 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:24:56.166 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:24:56.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:56.166 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:56.166 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:24:56.166 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:24:56.166 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:24:56.166 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:24:56.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:56.168 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:24:56.169 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:24:56.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:56.169 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:56.169 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:24:56.169 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:24:56.169 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:24:56.169 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:24:56.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:56.171 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:24:56.171 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:24:56.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:56.171 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:24:56.171 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:24:56.171 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:24:56.171 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:24:56.171 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:24:56.171 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:56.173 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:24:56.173 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:24:56.173 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:24:56.173 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:24:56.174 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:24:56.174 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:24:56.174 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.174 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:24:56.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:24:56.179 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:24:56.658 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:24:56.700 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:24:56.703 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:24:56.704 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:24:56.707 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:24:56.711 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:24:56.711 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:24:56.711 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:24:56.712 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:24:56.712 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:24:56.712 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:24:56.712 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:24:56.712 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:24:57.129 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:24:57.176 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:57.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:57.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:57.177 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:57.601 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:24:58.074 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:24:58.177 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:58.177 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:58.178 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:58.178 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:58.547 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:24:59.019 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:24:59.178 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:24:59.179 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:24:59.179 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:24:59.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:24:59.490 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:24:59.963 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:25:00.180 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:00.180 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:00.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:00.180 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:00.436 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:25:00.911 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:25:01.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:01.181 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:01.181 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:01.181 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:01.383 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:25:01.854 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:25:02.328 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:25:02.800 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:25:03.272 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:25:03.743 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:25:04.217 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:25:04.689 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:25:04.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:25:04.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:25:04.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:04.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:04.754 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:04.754 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:04.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:04.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:04.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:04.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:04.755 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:04.755 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:04.755 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:25:09.762 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:09.762 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:09.762 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:09.762 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:09.762 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:09.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:09.771 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:09.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:09.772 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:09.772 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:09.772 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:25:09.775 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:25:09.776 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:25:09.776 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:09.776 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:09.776 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:09.777 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:25:09.777 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:09.777 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:25:09.777 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:09.779 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:25:09.779 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:25:09.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:09.779 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:09.779 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:09.779 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:25:09.779 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:09.780 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:25:09.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:09.781 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:25:09.781 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:25:09.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:09.782 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:09.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:09.782 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:25:09.782 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:09.782 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:25:09.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:25:09.785 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:25:09.785 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:25:09.785 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:25:09.785 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:25:09.786 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.786 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.786 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.786 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:09.787 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:09.787 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:25:09.787 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:14.794 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:14.794 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:14.794 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:14.794 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:14.794 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:14.794 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:14.802 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:14.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:14.803 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:14.803 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:14.803 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:25:14.806 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:25:14.806 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:25:14.806 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:14.806 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:14.807 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:14.807 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:25:14.807 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:14.807 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:25:14.808 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:14.809 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:25:14.809 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:25:14.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:14.809 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:14.809 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:14.809 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:25:14.809 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:14.809 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:25:14.809 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:14.811 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:25:14.811 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:25:14.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:14.811 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:14.811 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:14.811 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:25:14.811 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:14.811 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:25:14.811 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:25:14.814 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:25:14.814 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:25:14.814 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.814 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.815 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:14.819 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:25:15.298 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:25:15.339 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:25:15.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:25:15.341 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:25:15.341 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:25:15.342 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:25:15.342 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:25:15.342 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:25:15.343 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:25:15.343 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:25:15.343 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:25:15.343 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:25:15.343 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:25:15.770 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:25:15.816 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:15.817 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:15.817 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:15.817 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:16.242 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:25:16.715 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:25:16.817 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:16.818 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:16.818 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:16.818 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:17.187 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:25:17.659 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:25:17.819 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:17.819 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:17.819 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:17.819 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:18.130 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:25:18.603 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:25:18.820 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:18.820 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:18.820 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:18.821 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:19.076 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:25:19.548 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:25:19.822 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:19.822 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:19.822 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:19.822 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:20.021 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:25:20.494 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:25:20.965 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:25:21.437 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:25:21.910 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:25:22.382 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:25:22.855 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:25:23.328 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:25:23.393 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:25:23.393 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:25:23.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:23.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:23.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:23.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:23.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:23.402 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:23.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:23.402 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:23.402 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:23.402 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:23.402 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:25:23.402 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:23.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:23.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:23.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:23.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:23.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:23.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:23.403 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1855 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:28.407 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:28.407 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:28.407 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:28.407 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:28.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:28.407 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:28.415 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:28.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:28.416 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:28.416 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:28.416 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:25:28.419 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:25:28.419 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:25:28.420 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:28.420 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:28.420 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:28.420 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:25:28.421 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:28.421 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:25:28.421 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:28.422 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:25:28.422 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:25:28.422 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:28.422 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:28.422 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:28.422 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:25:28.423 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:28.423 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:25:28.423 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:28.424 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:25:28.425 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:25:28.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:28.425 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:28.425 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:28.425 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:25:28.425 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:28.425 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:25:28.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:28.427 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:25:28.428 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:25:28.428 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:25:28.428 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.428 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:28.429 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:28.430 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:28.430 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:25:28.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:33.436 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:33.436 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:33.436 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:33.436 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:33.436 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:33.436 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:33.443 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:33.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:33.444 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:33.444 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:33.445 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:25:33.448 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:25:33.448 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:25:33.448 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:33.448 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:33.448 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:33.449 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:25:33.449 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:33.449 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:25:33.449 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:33.452 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:25:33.452 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:25:33.452 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:33.453 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:33.453 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:33.453 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:25:33.453 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:33.453 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:25:33.454 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:33.458 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:25:33.458 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:25:33.458 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:33.458 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:33.458 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:33.459 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:25:33.459 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:33.459 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:25:33.459 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:33.465 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:25:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:25:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:25:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:25:33.465 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:25:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:25:33.465 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:25:33.466 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:25:33.466 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:25:33.466 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:25:33.466 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:33.471 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:25:33.949 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:25:33.994 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:25:33.996 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:25:33.997 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:25:33.998 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:25:34.000 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:25:34.000 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:25:34.000 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:25:34.001 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:25:34.001 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:25:34.001 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:25:34.001 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:25:34.001 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:25:34.421 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:25:34.470 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:34.470 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:34.470 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:34.471 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:34.892 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:25:35.363 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:25:35.472 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:35.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:35.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:35.491 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:35.834 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:25:36.305 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:25:36.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:36.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:36.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:36.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:36.778 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:25:37.250 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:25:37.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:37.492 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:37.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:37.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:37.723 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:25:38.196 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:25:38.493 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:38.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:38.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:38.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:38.668 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:25:39.141 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:25:39.614 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:25:40.087 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:25:40.559 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:25:41.030 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:25:41.503 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:25:41.975 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:25:42.447 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:25:42.918 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:25:43.391 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:25:43.863 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:25:44.335 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:25:44.806 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:25:45.280 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:25:45.752 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:25:46.224 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:25:46.695 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:25:47.168 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:25:47.641 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:25:48.043 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:25:48.043 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:25:48.048 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:48.049 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:48.049 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:48.049 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:48.051 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:48.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:48.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:48.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:48.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:48.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:48.052 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:25:48.052 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3151 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:48.052 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3151 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:48.052 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3151 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:48.052 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3151 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:48.052 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3151 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:48.052 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3151 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:25:53.055 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:53.055 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:53.055 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:53.055 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:53.055 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:53.055 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:53.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:53.064 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:53.065 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:53.065 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:53.065 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:25:53.069 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:25:53.069 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:25:53.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:53.070 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:53.070 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:53.071 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:25:53.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:53.071 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:25:53.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:53.073 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:25:53.073 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:25:53.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:53.073 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:53.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:53.073 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:25:53.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:53.074 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:25:53.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:53.076 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:25:53.076 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:25:53.076 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:53.076 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:53.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:53.077 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:25:53.077 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:53.077 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:25:53.077 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.080 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:25:53.081 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:25:53.081 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:25:53.081 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.081 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:53.082 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:53.082 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:53.083 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:25:58.090 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:25:58.090 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:25:58.091 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:58.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:58.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:58.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:58.098 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:25:58.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:58.099 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:58.099 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:25:58.099 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:25:58.102 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:25:58.102 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:25:58.102 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:58.102 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:58.102 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:25:58.103 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:25:58.103 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:25:58.103 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:25:58.103 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:58.104 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:25:58.104 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:25:58.105 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:58.105 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:58.105 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:25:58.105 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:25:58.105 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:25:58.105 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:25:58.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:58.106 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:25:58.106 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:25:58.107 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:58.107 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:25:58.107 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:25:58.107 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:25:58.107 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:25:58.107 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:25:58.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.109 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:25:58.110 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:25:58.110 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:25:58.110 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:25:58.110 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:25:58.114 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:25:58.593 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:25:58.629 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:25:58.630 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:25:58.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:25:58.632 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:25:58.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:25:58.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:25:58.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:25:58.634 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:25:58.635 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:25:58.635 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:25:58.635 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:25:58.635 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:25:59.065 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:25:59.112 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:25:59.112 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:25:59.112 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:25:59.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:25:59.536 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:26:00.010 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:26:00.113 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:00.113 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:00.113 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:00.113 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:00.482 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:26:00.954 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:26:01.114 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:01.114 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:01.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:01.114 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:01.425 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:26:01.898 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:26:02.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:02.115 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:02.116 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:02.116 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:02.371 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:26:02.843 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:26:03.116 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:03.116 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:03.117 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:03.117 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:03.316 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:26:03.789 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:26:04.261 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:26:04.732 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:26:05.206 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:26:05.678 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:26:06.150 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:26:06.621 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:26:06.687 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:26:06.687 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:26:06.692 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:06.693 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:06.693 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:06.693 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:06.695 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:06.695 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:06.695 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:06.695 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:26:06.695 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:06.695 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:06.695 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:06.695 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:06.695 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:06.695 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:06.695 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:06.695 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:06.695 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:11.699 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:11.699 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:11.699 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:11.699 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:11.699 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:11.699 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:11.706 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:11.707 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:11.707 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:11.707 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:11.707 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:26:11.709 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:26:11.710 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:26:11.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:11.710 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:11.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:11.710 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:26:11.711 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:11.711 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:26:11.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:11.712 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:26:11.712 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:26:11.712 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:11.712 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:11.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:11.713 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:26:11.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:11.713 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:26:11.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:11.714 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:26:11.715 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:26:11.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:11.715 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:11.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:11.715 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:26:11.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:11.715 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:26:11.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:11.717 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:26:11.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:26:11.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:26:11.718 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:26:11.718 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:26:11.718 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:11.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:11.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:11.719 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:26:16.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:16.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:16.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:16.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:16.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:16.728 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:16.735 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:16.736 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:16.736 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:16.737 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:16.737 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:26:16.740 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:26:16.741 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:26:16.741 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:16.741 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:16.741 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:16.742 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:26:16.742 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:16.742 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:26:16.743 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:16.744 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:26:16.745 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:26:16.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:16.745 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:16.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:16.746 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:26:16.746 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:16.746 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:26:16.746 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:16.747 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:26:16.747 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:26:16.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:16.748 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:16.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:16.748 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:26:16.748 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:16.748 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:26:16.748 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:26:16.751 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:26:16.752 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:26:16.752 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:26:16.752 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.753 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:16.757 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:26:17.233 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:26:17.275 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:26:17.278 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:26:17.279 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:26:17.280 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:26:17.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:26:17.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:26:17.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:26:17.283 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:26:17.283 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:26:17.284 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:26:17.284 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:26:17.284 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:26:17.705 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:26:17.754 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:17.754 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:17.755 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:17.755 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:18.176 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:26:18.647 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:26:18.756 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:18.756 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:18.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:18.756 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:19.121 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:26:19.593 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:26:19.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:19.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:19.757 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:19.757 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:20.065 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:26:20.536 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:26:20.757 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:20.758 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:20.758 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:20.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:21.009 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:26:21.482 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:26:21.758 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:21.759 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:21.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:21.759 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:21.954 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:26:22.427 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:26:22.900 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:26:23.372 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:26:23.843 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:26:24.315 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:26:24.788 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:26:25.260 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:26:25.733 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:26:26.206 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:26:26.678 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:26:27.149 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:26:27.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:26:27.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:26:27.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:27.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:27.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:27.336 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:27.338 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:27.338 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:27.338 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:27.338 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:26:27.338 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:27.338 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:27.338 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:27.339 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:27.339 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:27.339 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:27.339 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:27.339 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:27.339 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2287 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:32.343 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:32.343 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:32.343 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:32.343 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:32.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:32.343 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:32.351 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:32.353 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:32.353 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:32.354 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:32.354 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:26:32.359 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:26:32.359 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:26:32.360 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:32.360 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:32.360 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:32.361 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:26:32.361 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:32.361 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:26:32.361 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:32.364 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:26:32.364 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:26:32.364 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:32.364 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:32.365 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:32.365 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:26:32.365 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:32.365 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:26:32.365 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:32.368 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:26:32.368 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:26:32.368 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:32.368 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:32.368 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:32.368 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:26:32.369 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:32.369 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:26:32.369 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.373 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:26:32.373 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:26:32.373 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:26:32.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:26:32.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:26:32.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:32.375 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:32.375 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:26:32.375 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:37.383 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:37.383 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:37.383 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:37.383 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:37.383 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:37.383 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:37.391 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:37.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:37.392 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:37.392 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:37.392 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:26:37.397 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:26:37.397 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:26:37.397 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:37.397 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:37.397 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:37.397 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:26:37.398 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:37.398 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:26:37.398 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:37.402 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:26:37.402 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:26:37.402 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:37.402 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:37.402 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:37.402 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:26:37.402 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:37.402 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:26:37.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:37.406 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:26:37.406 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:26:37.406 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:37.406 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:37.407 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:37.407 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:26:37.407 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:37.407 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:26:37.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:37.411 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:26:37.411 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.412 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:26:37.412 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:26:37.412 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:26:37.413 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.413 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.414 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:37.417 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:26:37.896 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:26:37.939 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:26:37.941 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:26:37.942 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:26:37.943 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:26:37.946 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:26:37.946 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:26:37.947 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:26:37.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:26:37.948 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:26:37.949 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:26:37.949 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:26:37.949 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:26:38.368 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:26:38.416 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:38.416 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:38.416 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:38.416 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:38.839 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:26:39.312 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:26:39.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:39.417 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:39.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:39.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:39.784 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:26:40.256 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:26:40.418 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:40.418 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:40.418 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:40.418 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:40.730 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:26:41.202 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:26:41.419 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:41.419 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:41.419 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:41.419 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:41.674 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:26:42.145 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:26:42.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:42.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:42.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:42.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:42.616 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:26:43.087 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:26:43.560 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:26:44.032 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:26:44.504 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:26:44.975 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:26:45.449 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:26:45.921 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:26:46.393 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:26:46.867 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:26:47.339 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:26:47.812 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:26:48.285 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:26:48.757 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:26:48.990 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:26:48.990 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:26:48.995 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:48.995 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:48.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:48.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:48.999 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:48.999 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:49.000 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:49.000 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:26:49.000 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:49.000 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:49.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:49.000 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:49.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:49.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:49.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:49.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:49.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:49.001 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2502 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:26:54.001 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:54.001 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:54.001 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:54.001 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:54.001 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:54.001 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:54.025 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:54.028 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:54.028 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:54.028 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:54.028 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:26:54.036 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:26:54.036 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:26:54.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:54.037 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:54.037 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:54.037 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:26:54.037 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:54.037 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:26:54.038 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:54.043 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:26:54.043 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:26:54.043 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:54.043 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:54.044 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:54.044 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:26:54.044 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:54.044 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:26:54.044 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:54.049 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:26:54.049 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:26:54.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:54.049 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:54.049 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:54.049 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:26:54.049 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:54.049 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:26:54.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:54.055 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:26:54.055 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:26:54.055 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:26:54.055 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.056 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:26:54.057 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:26:54.057 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:26:54.057 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.057 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:26:54.058 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.058 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.058 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:54.060 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:54.060 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:54.060 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:26:59.067 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:26:59.067 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:26:59.067 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:59.067 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:59.067 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:59.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:59.095 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:26:59.097 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:59.098 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:59.098 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:26:59.098 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:26:59.106 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:26:59.106 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:26:59.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:59.106 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:59.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:26:59.107 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:26:59.107 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:26:59.107 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:26:59.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:26:59.112 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:26:59.113 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:26:59.113 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:59.113 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:59.113 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:26:59.113 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:26:59.114 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:26:59.114 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:26:59.114 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:26:59.118 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:26:59.118 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:26:59.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:59.118 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:26:59.118 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:26:59.118 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:26:59.118 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:26:59.118 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:26:59.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:26:59.124 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:26:59.124 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:26:59.124 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.125 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:26:59.126 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:26:59.126 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:26:59.126 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.126 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.127 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:26:59.128 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:26:59.131 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:26:59.608 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:26:59.661 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:26:59.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:26:59.664 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:26:59.667 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:26:59.670 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:26:59.670 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:26:59.671 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:26:59.672 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:26:59.672 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:26:59.672 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:26:59.672 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:26:59.672 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:27:00.080 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:27:00.130 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:00.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:00.131 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:00.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:00.552 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:27:01.025 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:27:01.131 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:01.131 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:01.132 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:01.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:01.497 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:27:01.969 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:27:02.132 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:02.133 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:02.133 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:02.133 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:02.440 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:27:02.914 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:27:03.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:03.134 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:03.134 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:03.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:03.386 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:27:03.858 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:27:04.135 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:04.135 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:04.135 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:04.135 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:04.329 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:27:04.802 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:27:05.275 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:27:05.747 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:27:06.218 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:27:06.691 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:27:07.164 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:27:07.635 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:27:08.107 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:27:08.578 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:27:09.051 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:27:09.523 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:27:09.995 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:27:10.466 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:27:10.940 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:27:11.412 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:27:11.884 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:27:12.357 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:27:12.830 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:27:13.302 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:27:13.773 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:27:14.247 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:27:14.719 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:27:15.191 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:27:15.662 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:27:16.135 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:27:16.608 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:27:17.080 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:27:17.551 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:27:18.024 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:27:18.496 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:27:18.969 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:27:19.442 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:27:19.709 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:27:19.709 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:27:19.714 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:19.714 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:19.714 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:19.714 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:19.716 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:19.716 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:19.716 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:19.716 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:19.716 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:19.716 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:19.716 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:27:19.716 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4448 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:19.716 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4448 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:19.716 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4448 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:19.716 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4448 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:19.716 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4448 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:19.716 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4448 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:19.716 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4448 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:24.721 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:24.721 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:24.721 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:24.721 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:24.721 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:24.721 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:24.729 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:24.730 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:24.730 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:24.731 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:24.731 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:27:24.734 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:27:24.735 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:27:24.735 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:24.735 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:24.736 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:24.736 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:27:24.736 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:24.736 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:27:24.737 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:24.738 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:27:24.739 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:27:24.739 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:24.739 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:24.739 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:24.740 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:27:24.740 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:24.740 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:27:24.740 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:24.742 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:27:24.742 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:27:24.742 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:24.742 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:24.742 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:24.742 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:27:24.742 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:24.742 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:27:24.742 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.746 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:27:24.746 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:27:24.746 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:27:24.746 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:27:24.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.747 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:27:24.747 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.747 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.747 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:24.748 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:24.748 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:24.748 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:27:29.755 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:29.755 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:29.755 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:29.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:29.755 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:29.755 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:29.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:29.764 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:29.764 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:29.764 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:29.765 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:27:29.767 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:27:29.768 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:27:29.768 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:29.768 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:29.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:29.769 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:27:29.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:29.769 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:27:29.770 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:29.771 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:27:29.771 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:27:29.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:29.771 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:29.771 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:29.771 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:27:29.771 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:29.772 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:27:29.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:29.774 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:27:29.774 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:27:29.774 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:29.774 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:29.774 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:29.774 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:27:29.774 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:29.774 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:27:29.774 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.777 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:27:29.778 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:27:29.778 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:27:29.778 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.778 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:29.779 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:29.782 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:27:30.260 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:27:30.306 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:27:30.309 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:27:30.311 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:27:30.311 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:27:30.732 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:27:30.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:30.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:30.781 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:30.781 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:31.207 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:27:31.679 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:27:31.782 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:31.782 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:31.782 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:31.782 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:32.155 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:27:32.626 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:27:32.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:32.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:32.784 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:32.784 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:33.101 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:27:33.573 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:27:33.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:33.785 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:33.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:33.785 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:34.044 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:27:34.520 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:27:34.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:34.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:34.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:34.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:34.991 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:27:35.467 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:27:35.939 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:27:36.414 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:27:36.886 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:27:37.357 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:27:37.832 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:27:38.304 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:27:38.779 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:27:39.250 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:27:39.722 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:27:40.198 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:27:40.324 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:40.324 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:40.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:40.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:40.328 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:40.328 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:40.328 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:40.328 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:27:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:40.329 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:40.329 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2274 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:40.329 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2274 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:40.329 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2274 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:40.330 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2274 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:40.330 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2274 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:40.330 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2274 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:40.330 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2274 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:27:45.331 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:45.331 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:45.331 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:45.331 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:45.331 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:45.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:45.340 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:45.340 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:45.341 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:45.341 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:45.341 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:27:45.344 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:27:45.344 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:27:45.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:45.345 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:45.345 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:45.345 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:27:45.345 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:45.345 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:27:45.345 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:45.349 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:27:45.349 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:27:45.349 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:45.349 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:45.349 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:45.350 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:27:45.350 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:45.350 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:27:45.350 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:45.353 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:27:45.353 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:27:45.353 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:45.353 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:45.354 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:45.354 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:27:45.354 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:45.354 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:27:45.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:27:45.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:27:45.360 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:27:45.360 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:27:45.360 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:45.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:27:45.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.361 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.361 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:45.361 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.361 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:45.362 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:45.363 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:45.363 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:27:45.363 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.370 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:27:50.370 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:27:50.370 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:50.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:50.370 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:50.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:50.380 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:27:50.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:50.383 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:50.383 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:27:50.383 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:27:50.389 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:27:50.389 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:27:50.389 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:50.389 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:50.389 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:27:50.389 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:27:50.390 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:27:50.390 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:27:50.390 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:50.394 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:27:50.394 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:27:50.394 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:50.394 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:50.394 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:27:50.394 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:27:50.395 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:27:50.395 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:27:50.395 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:50.398 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:27:50.398 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:27:50.398 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:50.398 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:27:50.398 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:27:50.398 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:27:50.398 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:27:50.398 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:27:50.399 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:50.402 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:27:50.403 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:27:50.403 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:27:50.403 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:27:50.403 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.405 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:27:50.405 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:27:50.405 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:27:50.408 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:27:50.886 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:27:50.929 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:27:50.930 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:27:50.932 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:27:50.932 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:27:51.351 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:27:51.407 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:51.407 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:51.407 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:51.407 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:51.814 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:27:52.278 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:27:52.409 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:52.409 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:52.409 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:52.409 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:52.747 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:27:53.211 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:27:53.410 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:53.410 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:53.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:53.410 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:53.680 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:27:54.151 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:27:54.411 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:54.412 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:54.412 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:54.412 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:54.626 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:27:55.098 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:27:55.413 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:27:55.414 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:27:55.414 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:27:55.414 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:27:55.574 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:27:56.046 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:27:56.521 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:27:56.991 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:27:57.463 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:27:57.935 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:27:58.409 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:27:58.881 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:27:59.353 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:27:59.827 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:28:00.300 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:28:00.771 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:28:01.245 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:28:01.718 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:28:02.189 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:28:02.665 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:28:02.943 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:02.943 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:02.943 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:02.943 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:02.944 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:02.944 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:02.944 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:02.944 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:02.944 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:28:02.944 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:02.944 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:07.952 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:07.952 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:07.952 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:07.952 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:07.952 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:07.952 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:07.960 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:07.961 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:07.961 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:07.961 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:07.961 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:28:07.964 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:28:07.964 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:28:07.964 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:07.964 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:07.965 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:07.965 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:28:07.965 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:07.965 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:28:07.965 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:07.966 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:28:07.966 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:28:07.966 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:07.966 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:07.967 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:07.967 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:28:07.967 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:07.967 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:28:07.967 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:07.968 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:28:07.968 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:28:07.968 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:07.968 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:07.969 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:07.969 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:28:07.969 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:07.969 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:28:07.969 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:28:07.971 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:28:07.971 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:28:07.971 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.971 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.972 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:07.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:07.972 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:07.972 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:07.973 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:07.973 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:07.973 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:07.973 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:07.973 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:07.973 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:28:12.980 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:12.980 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:12.980 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:12.981 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:12.981 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:12.981 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:12.988 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:12.988 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:12.988 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:12.989 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:12.989 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:28:12.991 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:28:12.991 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:28:12.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:12.992 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:12.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:12.992 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:28:12.992 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:12.992 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:28:12.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:12.993 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:28:12.994 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:28:12.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:12.994 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:12.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:12.994 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:28:12.994 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:12.994 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:28:12.994 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:12.996 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:28:12.996 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:28:12.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:12.996 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:12.996 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:12.996 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:28:12.996 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:12.996 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:28:12.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:12.998 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:28:12.998 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:28:12.998 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:28:12.998 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:28:12.998 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:28:12.999 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:28:12.999 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:28:12.999 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:12.999 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:13.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:13.004 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:28:13.482 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:28:13.522 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:28:13.524 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:28:13.525 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:28:13.525 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:28:13.528 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:28:13.528 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:28:13.528 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:28:13.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:13.529 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:28:13.529 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:28:13.529 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:28:13.529 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:28:13.573 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:28:13.573 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:28:13.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:13.573 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:13.952 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:28:14.001 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:14.001 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:14.002 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:14.002 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:14.425 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:28:14.897 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:28:15.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:15.003 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:15.003 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:15.003 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:15.369 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:28:15.842 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:28:16.004 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:16.004 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:16.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:16.005 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:16.314 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:28:16.786 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:28:17.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:17.006 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:17.006 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:17.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:17.259 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:28:17.732 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:28:18.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:18.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:18.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:18.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:18.204 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:28:18.677 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:28:19.149 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:28:19.621 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:28:20.092 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:28:20.566 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:28:21.038 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:28:21.511 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:28:21.578 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:28:21.578 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:28:21.578 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:28:21.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:21.583 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:21.583 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:21.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:21.587 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:21.587 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:21.587 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:21.587 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:28:21.587 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:21.587 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:21.587 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:21.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:21.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:21.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:21.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:21.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:21.587 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1854 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:26.589 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:26.589 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:26.589 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:26.589 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:26.590 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:26.590 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:26.598 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:26.599 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:26.599 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:26.599 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:26.599 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:28:26.603 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:28:26.604 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:28:26.604 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:26.604 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:26.604 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:26.604 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:28:26.604 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:26.604 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:28:26.605 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:26.608 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:28:26.609 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:28:26.609 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:26.609 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:26.609 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:26.609 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:28:26.609 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:26.609 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:28:26.609 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:26.613 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:28:26.613 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:28:26.613 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:26.613 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:26.613 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:26.613 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:28:26.614 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:26.614 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:28:26.614 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:28:26.619 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:28:26.620 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:28:26.620 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:28:26.620 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.620 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.621 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:28:26.621 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.621 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.621 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.622 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.622 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.622 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:26.623 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:26.623 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:28:26.623 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:31.629 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:31.629 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:31.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:31.629 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:31.629 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:31.629 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:31.638 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:31.640 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:31.640 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:31.641 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:31.641 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:28:31.644 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:28:31.645 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:28:31.645 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:31.645 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:31.646 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:31.646 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:28:31.646 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:31.646 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:28:31.647 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:31.648 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:28:31.648 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:28:31.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:31.649 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:31.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:31.649 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:28:31.649 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:31.649 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:28:31.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:31.651 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:28:31.651 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:28:31.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:31.651 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:31.651 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:31.651 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:28:31.651 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:31.651 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:28:31.651 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:31.654 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:28:31.654 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:28:31.654 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:28:31.654 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:28:31.654 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:28:31.655 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:28:31.655 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:28:31.655 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:31.660 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:28:32.138 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:28:32.184 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:28:32.186 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:28:32.188 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:28:32.189 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:28:32.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:28:32.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:28:32.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:28:32.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:32.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:28:32.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:28:32.192 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:28:32.192 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:28:32.228 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:28:32.228 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:28:32.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:32.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:32.609 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:28:32.658 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:32.658 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:32.658 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:32.659 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:33.081 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:28:33.553 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:28:33.659 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:33.660 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:33.660 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:33.660 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:34.025 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:28:34.499 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:28:34.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:34.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:34.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:34.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:34.972 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:28:35.445 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:28:35.662 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:35.662 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:35.663 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:35.663 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:35.918 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:28:36.391 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:28:36.663 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:36.664 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:36.664 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:36.664 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:36.863 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:28:37.335 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:28:37.807 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:28:38.280 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:28:38.753 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:28:39.224 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:28:39.698 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:28:40.170 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:28:40.233 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:28:40.233 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:28:40.233 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:28:40.237 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:40.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:40.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:40.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:40.241 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:40.241 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:40.241 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:40.241 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:40.241 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:40.241 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:40.241 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:28:40.241 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:40.241 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:40.241 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:40.241 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:40.241 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:40.241 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:45.243 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:45.243 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:45.243 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:45.243 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:45.243 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:45.243 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:45.249 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:45.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:45.250 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:45.250 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:45.250 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:28:45.253 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:28:45.253 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:28:45.254 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:45.254 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:45.254 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:45.254 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:28:45.255 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:45.255 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:28:45.255 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:45.256 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:28:45.256 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:28:45.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:45.256 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:45.256 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:45.256 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:28:45.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:45.256 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:28:45.257 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:45.258 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:28:45.258 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:28:45.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:45.259 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:45.259 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:45.259 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:28:45.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:45.259 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:28:45.259 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:45.261 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:28:45.261 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:28:45.261 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:28:45.261 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:28:45.261 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:28:45.262 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:28:45.262 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:28:45.262 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.262 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:45.263 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:45.263 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:28:45.263 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:50.271 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:50.271 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:50.271 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:50.271 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:50.271 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:50.271 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:50.279 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:50.280 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:50.280 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:50.280 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:28:50.280 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:28:50.282 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:28:50.282 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:28:50.283 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:50.283 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:50.283 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:50.283 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:28:50.284 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:28:50.284 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:28:50.284 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:50.285 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:28:50.285 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:28:50.285 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:50.285 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:50.285 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:50.285 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:28:50.285 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:28:50.285 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:28:50.285 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:50.287 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:28:50.287 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:28:50.287 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:50.287 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:28:50.287 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:50.287 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:28:50.287 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:28:50.287 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:28:50.287 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:50.289 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:28:50.289 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:28:50.290 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:28:50.290 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:28:50.290 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.290 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:28:50.295 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:28:50.773 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:28:50.815 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:28:50.817 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:28:50.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:28:50.819 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:28:50.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:28:50.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:28:50.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:28:50.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:50.824 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:28:50.824 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:28:50.824 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:28:50.824 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:28:50.863 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:28:50.863 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:28:50.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:50.864 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:28:51.245 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:28:51.292 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:51.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:51.293 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:51.293 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:51.718 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:28:52.191 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:28:52.293 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:52.293 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:52.294 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:52.294 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:52.664 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:28:53.137 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:28:53.294 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:53.294 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:53.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:53.295 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:53.609 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:28:54.082 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:28:54.295 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:54.295 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:54.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:54.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:54.555 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:28:55.028 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:28:55.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:55.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:55.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:55.297 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:55.499 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:28:55.971 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:28:56.444 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:28:56.916 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:28:57.388 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:28:57.862 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:28:58.334 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:28:58.806 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:28:58.868 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:28:58.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:28:58.868 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:28:58.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:28:58.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:28:58.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:28:58.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:28:58.876 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:28:58.876 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:28:58.876 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:28:58.876 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:28:58.876 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:28:58.876 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:28:58.876 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:28:58.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:58.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:58.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:58.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:58.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:58.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:28:58.876 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1853 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:29:03.879 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:03.879 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:03.879 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:03.879 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:03.879 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:03.879 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:03.886 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:03.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:03.887 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:03.887 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:03.888 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:29:03.889 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:29:03.890 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:29:03.890 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:03.890 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:03.891 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:03.891 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:29:03.891 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:03.891 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:29:03.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:03.893 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:29:03.893 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:29:03.893 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:03.893 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:03.894 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:03.894 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:29:03.894 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:03.894 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:29:03.894 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:03.897 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:29:03.897 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:29:03.897 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:03.897 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:03.897 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:03.898 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:29:03.898 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:03.898 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:29:03.898 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:29:03.903 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:29:03.904 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:29:03.904 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:29:03.904 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.904 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.905 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:29:03.905 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.905 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.905 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:03.907 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:03.907 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:03.907 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:29:08.913 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:08.913 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:08.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:08.913 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:08.913 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:08.914 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:08.922 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:08.923 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:08.923 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:08.923 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:08.923 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:29:08.926 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:29:08.926 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:29:08.926 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:08.927 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:08.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:08.927 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:29:08.927 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:08.927 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:29:08.928 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:08.929 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:29:08.929 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:29:08.929 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:08.929 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:08.929 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:08.929 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:29:08.929 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:08.929 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:29:08.929 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:08.931 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:29:08.931 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:29:08.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:08.931 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:08.931 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:08.931 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:29:08.931 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:08.931 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:29:08.932 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.934 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:29:08.935 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:29:08.935 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:29:08.935 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.935 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:08.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.936 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:08.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:08.936 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:08.939 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:29:09.417 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:29:09.463 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:29:09.466 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:29:09.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:29:09.469 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:29:09.472 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:29:09.472 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:29:09.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:29:09.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:09.473 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:29:09.473 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:29:09.473 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:29:09.473 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:29:09.508 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:29:09.508 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:29:09.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:09.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:09.890 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:29:09.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:09.938 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:09.938 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:09.938 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:10.363 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:29:10.836 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:29:10.938 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:10.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:10.939 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:10.939 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:11.309 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:29:11.782 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:29:11.939 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:11.939 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:11.940 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:11.940 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:12.254 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:29:12.728 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:29:12.941 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:12.941 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:12.941 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:12.941 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:13.200 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:29:13.672 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:29:13.942 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:13.942 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:13.942 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:13.942 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:14.144 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:29:14.617 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:29:15.090 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:29:15.564 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:29:16.035 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:29:16.508 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:29:16.981 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:29:17.453 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:29:17.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:29:17.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:29:17.512 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:29:17.517 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:17.517 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:17.517 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:17.518 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:17.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:17.519 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:17.519 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:17.519 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:17.520 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:17.520 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:17.520 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:29:22.525 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:22.525 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:22.525 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:22.525 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:22.525 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:22.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:22.532 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:22.534 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:22.534 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:22.534 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:22.534 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:29:22.539 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:29:22.539 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:29:22.540 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:22.540 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:22.540 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:22.540 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:29:22.540 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:22.540 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:29:22.541 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:22.545 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:29:22.545 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:29:22.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:22.545 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:22.545 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:22.545 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:29:22.545 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:22.545 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:29:22.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:22.549 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:29:22.549 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:29:22.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:22.550 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:22.550 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:22.550 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:29:22.550 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:22.550 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:29:22.550 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:22.555 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:29:22.555 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:29:22.555 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:29:22.555 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:29:22.555 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:29:22.556 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:29:22.556 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:29:22.556 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:29:22.556 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:29:22.557 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.557 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.557 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:22.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:22.559 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:22.559 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:22.559 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:22.559 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:22.559 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:22.559 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:29:27.566 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:27.566 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:27.566 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:27.567 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:27.567 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:27.567 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:27.573 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:27.574 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:27.574 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:27.574 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:27.574 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:29:27.577 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:29:27.577 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:29:27.577 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:27.577 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:27.577 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:27.577 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:29:27.578 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:27.578 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:29:27.578 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:27.580 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:29:27.580 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:29:27.580 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:27.580 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:27.581 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:27.581 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:29:27.581 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:27.581 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:29:27.581 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:27.583 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:29:27.583 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:29:27.583 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:27.583 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:27.583 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:27.583 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:29:27.583 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:27.583 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:29:27.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.586 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:29:27.587 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:29:27.587 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:29:27.587 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.587 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:27.588 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:27.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:27.591 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:29:28.070 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:29:28.111 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:29:28.113 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:29:28.115 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:29:28.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:29:28.116 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:29:28.116 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:29:28.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:29:28.116 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:28.116 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:29:28.116 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:29:28.116 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:29:28.116 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:29:28.160 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:29:28.160 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:29:28.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:28.161 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:28.542 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:29:28.589 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:28.589 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:28.589 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:28.589 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:29.014 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:29:29.488 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:29:29.590 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:29.590 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:29.590 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:29.590 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:29.960 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:29:30.434 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:29:30.592 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:30.592 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:30.592 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:30.592 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:30.906 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:29:31.378 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:29:31.593 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:31.593 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:31.593 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:31.593 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:31.850 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:29:32.324 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:29:32.594 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:32.594 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:32.594 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:32.594 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:32.796 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:29:33.270 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:29:33.742 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:29:34.214 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:29:34.687 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:29:35.160 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:29:35.632 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:29:36.103 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:29:36.577 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:29:37.049 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:29:37.521 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:29:37.995 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:29:38.467 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:29:38.939 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:29:39.413 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:29:39.885 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:29:40.357 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:29:40.831 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:29:41.303 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:29:41.775 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:29:42.166 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:29:42.166 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:29:42.166 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:29:42.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:42.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:42.171 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:42.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:42.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:42.173 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:42.173 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:42.173 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:42.173 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:42.173 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:42.173 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:29:47.177 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:47.177 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:47.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:47.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:47.177 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:47.177 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:47.185 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:47.187 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:47.187 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:47.187 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:47.187 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:29:47.190 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:29:47.190 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:29:47.190 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:47.190 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:47.191 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:47.191 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:29:47.191 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:47.191 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:29:47.192 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:47.192 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:29:47.193 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:29:47.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:47.193 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:47.193 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:47.193 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:29:47.193 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:47.193 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:29:47.193 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:47.195 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:29:47.195 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:29:47.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:47.195 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:47.195 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:47.195 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:29:47.195 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:47.195 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:29:47.195 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:29:47.198 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:29:47.198 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:29:47.198 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:29:47.198 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.199 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:47.200 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:47.200 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:47.200 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:29:52.207 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:29:52.207 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:29:52.207 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:52.207 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:52.207 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:52.208 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:52.215 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:29:52.215 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:52.216 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:52.216 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:29:52.216 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:29:52.219 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:29:52.219 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:29:52.220 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:52.220 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:52.220 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:29:52.220 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:29:52.221 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:29:52.221 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:29:52.221 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:52.222 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:29:52.223 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:29:52.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:52.223 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:52.223 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:29:52.223 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:29:52.223 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:29:52.223 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:29:52.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:52.225 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:29:52.225 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:29:52.226 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:52.226 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:29:52.226 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:29:52.226 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:29:52.226 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:29:52.226 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:29:52.226 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.229 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:29:52.230 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:29:52.230 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:29:52.230 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.230 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:29:52.231 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:29:52.234 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:29:52.713 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:29:52.766 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:29:52.768 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:29:52.769 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:29:52.771 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:29:52.775 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:29:52.775 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:29:52.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:29:52.776 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:52.776 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:29:52.776 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:29:52.776 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:29:52.776 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:29:52.803 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:29:52.803 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:29:52.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:52.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:29:53.185 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:29:53.233 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:53.233 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:53.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:53.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:53.658 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:29:54.131 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:29:54.234 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:54.234 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:54.234 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:54.238 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:54.603 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:29:55.077 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:29:55.235 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:55.235 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:55.235 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:55.239 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:55.549 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:29:56.021 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:29:56.236 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:56.237 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:56.237 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:56.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:56.494 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:29:56.967 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:29:57.238 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:29:57.238 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:29:57.238 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:29:57.241 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:29:57.439 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:29:57.913 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:29:58.384 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:29:58.856 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:29:59.328 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:29:59.801 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:30:00.273 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:30:00.745 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:30:00.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:30:00.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:30:00.808 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:30:00.813 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:00.813 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:00.814 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:00.814 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:00.815 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:00.815 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:00.815 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:00.815 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:00.815 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:30:00.815 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:00.815 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:05.824 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:05.824 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:05.824 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:05.825 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:05.825 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:05.825 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:05.833 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:05.833 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:05.834 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:05.834 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:05.834 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:30:05.836 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:30:05.836 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:30:05.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:05.836 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:05.836 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:05.836 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:30:05.836 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:05.836 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:30:05.836 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:05.838 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:30:05.838 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:30:05.838 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:05.838 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:05.838 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:05.839 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:30:05.839 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:05.839 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:30:05.839 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:05.839 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:30:05.840 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:30:05.840 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:05.840 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:05.840 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:05.840 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:30:05.840 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:05.840 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:30:05.840 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:30:05.842 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:30:05.842 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:30:05.842 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.842 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:05.843 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:05.843 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:05.843 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:30:10.850 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:10.850 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:10.850 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:10.850 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:10.850 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:10.850 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:10.858 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:10.859 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:10.859 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:10.859 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:10.859 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:30:10.862 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:30:10.862 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:30:10.863 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:10.863 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:10.863 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:10.864 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:30:10.864 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:10.864 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:30:10.864 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:10.865 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:30:10.865 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:30:10.865 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:10.865 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:10.865 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:10.865 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:30:10.866 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:10.866 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:30:10.866 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:10.867 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:30:10.867 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:30:10.867 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:10.867 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:10.867 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:10.867 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:30:10.868 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:10.868 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:30:10.868 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:30:10.870 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:30:10.871 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:30:10.871 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:30:10.871 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:10.871 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:10.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:10.875 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:30:11.349 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:30:11.399 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:30:11.401 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:30:11.403 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:30:11.403 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:30:11.406 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:30:11.407 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:30:11.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:30:11.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:30:11.408 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:30:11.408 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:30:11.408 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:30:11.408 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:30:11.817 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:30:11.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:11.873 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:11.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:11.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:12.288 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:30:12.757 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:30:12.873 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:12.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:12.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:12.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:13.227 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:30:13.692 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:30:13.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:13.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:13.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:13.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:14.158 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:30:14.622 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:30:14.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:14.876 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:14.876 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:14.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:15.090 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:30:15.557 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:30:15.877 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:15.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:15.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:15.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:16.019 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:30:16.482 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:30:16.945 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:30:17.408 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:30:17.870 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:30:18.338 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:30:18.809 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:30:19.275 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:30:19.740 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:30:20.207 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:30:20.677 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:30:21.145 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:30:21.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:30:21.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:30:21.447 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:21.448 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:21.448 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:21.448 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:21.449 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:21.449 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:21.449 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:21.449 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:30:21.449 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:21.449 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:21.449 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:21.449 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2312 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:21.449 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2312 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:21.449 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2312 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:21.449 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2312 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:21.449 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2312 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:21.449 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2312 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:26.454 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:26.454 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:26.454 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:26.454 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:26.454 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:26.454 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:26.465 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:26.466 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:26.466 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:26.466 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:26.466 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:30:26.468 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:30:26.469 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:30:26.469 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:26.469 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:26.469 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:26.470 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:30:26.470 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:26.470 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:30:26.471 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:26.472 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:30:26.473 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:30:26.473 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:26.473 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:26.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:26.474 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:30:26.474 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:26.474 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:30:26.474 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:26.477 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:30:26.477 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:30:26.478 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:26.478 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:26.478 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:26.478 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:30:26.478 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:26.478 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:30:26.478 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:30:26.484 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:30:26.485 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:30:26.485 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:30:26.485 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.485 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:30:26.486 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.486 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.486 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.487 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.487 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.487 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:26.488 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:26.488 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:26.488 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:30:31.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:31.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:31.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:31.511 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:31.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:31.511 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:31.519 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:31.520 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:31.520 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:31.520 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:31.521 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:30:31.523 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:30:31.523 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:30:31.524 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:31.524 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:31.524 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:31.524 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:30:31.525 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:31.525 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:30:31.525 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:31.526 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:30:31.526 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:30:31.526 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:31.526 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:31.527 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:31.527 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:30:31.527 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:31.527 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:30:31.527 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:31.530 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:30:31.530 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:30:31.530 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:31.530 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:31.531 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:31.531 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:30:31.531 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:31.531 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:30:31.531 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:31.536 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.537 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:30:31.537 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:30:31.538 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:30:31.538 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.539 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:31.540 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:31.542 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:30:32.007 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:30:32.072 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:30:32.074 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:30:32.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:30:32.076 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:30:32.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:30:32.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:30:32.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:30:32.081 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:30:32.081 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:30:32.082 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:30:32.082 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:30:32.082 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:30:32.097 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:30:32.097 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=2, maio=0, ma_len=2
2026-03-01 03:30:32.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:30:32.097 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:30:32.473 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:30:32.543 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:32.543 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:32.543 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:32.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:32.938 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:30:33.408 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:30:33.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:33.544 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:33.544 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:33.545 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:33.873 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:30:34.340 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:30:34.544 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:34.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:34.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:34.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:34.806 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:30:35.271 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:30:35.545 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:35.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:35.545 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:35.546 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:35.734 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:30:36.200 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:30:36.546 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:36.546 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:36.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:36.547 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:36.664 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:30:37.129 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:30:37.599 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:30:38.073 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:30:38.545 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:30:39.018 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:30:39.491 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:30:39.962 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:30:40.433 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:30:40.903 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:30:41.375 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:30:41.848 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:30:42.321 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:30:42.791 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:30:43.101 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:30:43.101 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:30:43.101 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:30:43.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:43.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:43.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:43.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:43.111 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:43.112 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:43.112 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:43.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:43.112 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:43.112 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:43.112 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2519 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2519 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2519 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.113 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:43.114 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2520 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:30:48.118 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:48.118 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:48.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:48.118 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:48.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:48.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:48.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:48.126 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:48.126 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:48.127 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:48.127 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:30:48.128 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:30:48.129 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:30:48.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:48.129 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:48.129 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:48.129 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:30:48.129 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:48.129 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:30:48.129 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:48.130 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:30:48.130 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:30:48.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:48.130 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:48.130 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:48.130 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:30:48.130 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:48.130 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:30:48.130 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:48.131 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:30:48.131 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:30:48.131 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:48.131 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:48.131 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:48.131 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:30:48.132 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:48.132 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:30:48.132 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:48.133 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:30:48.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:30:48.133 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:30:48.133 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:30:48.133 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:30:48.133 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:30:48.134 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:30:48.134 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:30:48.134 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.134 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:48.135 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:48.135 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:48.135 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:30:53.147 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:30:53.148 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:30:53.148 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:53.148 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:53.148 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:53.148 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:53.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:30:53.155 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:53.155 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:53.155 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:30:53.155 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:30:53.157 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:30:53.157 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:30:53.157 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:53.158 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:53.158 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:30:53.158 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:30:53.158 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:30:53.158 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:30:53.158 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:53.159 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:30:53.160 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:30:53.160 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:53.160 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:53.160 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:30:53.160 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:30:53.160 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:30:53.160 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:30:53.160 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:53.161 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:30:53.161 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:30:53.161 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:53.161 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:30:53.162 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:30:53.162 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:30:53.162 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:30:53.162 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:30:53.162 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:30:53.164 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:30:53.164 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:30:53.164 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.164 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:30:53.165 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:30:53.169 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:30:53.641 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:30:53.679 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:30:53.679 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:30:53.680 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:30:53.680 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:30:54.110 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:30:54.166 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:54.167 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:54.167 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:54.167 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:54.583 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:30:55.055 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:30:55.168 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:55.169 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:55.169 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:55.169 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:55.519 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:30:55.982 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:30:56.170 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:56.170 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:56.170 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:56.170 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:56.453 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:30:56.924 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:30:57.171 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:57.171 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:57.172 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:57.172 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:57.390 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:30:57.853 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:30:58.173 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:30:58.173 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:30:58.173 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:30:58.173 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:30:58.319 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:30:58.789 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:30:59.254 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:30:59.720 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:31:00.183 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:31:00.649 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:31:01.115 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:31:01.586 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:31:02.060 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:31:02.524 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:31:02.992 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:31:03.464 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:31:03.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:03.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:03.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:03.689 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:03.690 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:03.690 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:03.690 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:03.690 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:03.690 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:03.690 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:31:03.690 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:08.696 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:08.696 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:08.696 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:08.696 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:08.696 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:08.696 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:08.704 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:08.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:08.706 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:08.706 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:08.706 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:31:08.709 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:31:08.710 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:31:08.710 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:08.710 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:08.710 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:08.711 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:31:08.711 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:08.711 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:31:08.711 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:08.712 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:31:08.712 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:31:08.712 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:08.712 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:08.712 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:08.712 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:31:08.713 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:08.713 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:31:08.713 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:08.714 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:31:08.715 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:31:08.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:08.715 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:08.715 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:08.715 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:31:08.715 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:08.715 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:31:08.715 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:08.717 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:31:08.717 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:31:08.717 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:31:08.717 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:31:08.717 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:31:08.718 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:31:08.718 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:31:08.718 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.718 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:08.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:08.719 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:31:08.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:13.727 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:13.727 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:13.727 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:13.727 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:13.727 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:13.727 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:13.744 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:13.746 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:13.746 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:13.746 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:13.747 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:31:13.750 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:31:13.751 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:31:13.751 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:13.751 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:13.752 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:13.752 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:31:13.752 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:13.752 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:31:13.753 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:13.754 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:31:13.755 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:31:13.755 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:13.755 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:13.755 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:13.756 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:31:13.756 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:13.756 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:31:13.756 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:13.757 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:31:13.758 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:31:13.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:13.758 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:13.758 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:13.758 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:31:13.758 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:13.758 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:31:13.758 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.761 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:31:13.762 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:31:13.762 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:31:13.762 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:13.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:13.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:13.766 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:31:14.245 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:31:14.288 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:31:14.289 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:31:14.291 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:31:14.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:31:14.717 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:31:14.765 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:14.765 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:14.765 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:14.766 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:15.193 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:31:15.664 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:31:15.766 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:15.766 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:15.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:15.767 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:16.135 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:31:16.609 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:31:16.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:16.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:16.768 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:16.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:17.082 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:31:17.553 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:31:17.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:17.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:17.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:17.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:18.022 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:31:18.495 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:31:18.771 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:18.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:18.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:18.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:18.967 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:31:19.442 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:31:19.914 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:31:20.390 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:31:20.862 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:31:21.334 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:31:21.808 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:31:22.280 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:31:22.755 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:31:23.227 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:31:23.697 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:31:24.169 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:31:24.642 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:31:25.115 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:31:25.586 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:31:26.057 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:31:26.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:26.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:26.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:26.306 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:26.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:26.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:26.308 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:26.308 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:26.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:26.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:26.308 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2707 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2707 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2707 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2707 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:26.308 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2708 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:31.317 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:31.317 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:31.317 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:31.317 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:31.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:31.317 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:31.325 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:31.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:31.325 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:31.325 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:31.325 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:31:31.327 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:31:31.327 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:31:31.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:31.327 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:31.327 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:31.327 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:31:31.327 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:31.327 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:31:31.327 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:31.329 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:31:31.329 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:31:31.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:31.329 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:31.329 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:31.329 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:31:31.329 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:31.329 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:31:31.329 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:31.332 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:31:31.332 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:31:31.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:31.332 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:31.332 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:31.332 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:31:31.332 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:31.332 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:31:31.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.336 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:31:31.336 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:31:31.336 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:31:31.336 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.337 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:31.341 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:31:31.813 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:31:31.855 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:31:31.856 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:31:31.857 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:31:31.857 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:31:31.858 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:31:31.858 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:31:31.858 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:31:31.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:31:31.859 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:31:31.859 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:31:31.859 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:31:31.859 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:31:32.280 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:31:32.338 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:32.339 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:32.339 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:32.339 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:32.751 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:31:33.223 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:31:33.340 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:33.340 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:33.340 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:33.340 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:33.696 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:31:34.169 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:31:34.341 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:34.341 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:34.341 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:34.341 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:34.641 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:31:35.115 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:31:35.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:35.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:35.342 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:35.342 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:35.586 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:31:36.058 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:31:36.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:36.343 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:36.343 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:36.343 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:36.529 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:31:37.003 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:31:37.474 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:31:37.946 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:31:38.418 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:31:38.891 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:31:39.363 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:31:39.836 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:31:40.306 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:31:40.777 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:31:41.248 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:31:41.721 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:31:42.194 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:31:42.666 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:31:42.911 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:31:42.911 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:31:42.916 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:42.917 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:42.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:42.917 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:42.920 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:42.920 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:42.920 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:42.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:42.920 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:42.920 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:42.920 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:42.920 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2505 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:31:47.927 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:31:47.927 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:31:47.927 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:47.927 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:47.927 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:47.928 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:47.941 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:31:47.942 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:47.942 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:47.942 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:31:47.942 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:31:47.944 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:31:47.944 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:31:47.944 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:47.944 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:47.945 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:31:47.945 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:31:47.945 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:31:47.945 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:31:47.945 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:47.946 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:31:47.946 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:31:47.946 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:47.946 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:47.946 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:31:47.946 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:31:47.947 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:31:47.947 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:31:47.947 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:47.948 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:31:47.948 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:31:47.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:47.948 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:31:47.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:31:47.948 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:31:47.948 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:31:47.948 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:31:47.949 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.951 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:31:47.951 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:31:47.951 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:31:47.951 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:31:47.952 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:31:47.956 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:31:48.427 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:31:48.466 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:31:48.467 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:31:48.467 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:31:48.468 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:31:48.468 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:31:48.468 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:31:48.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:31:48.468 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:31:48.468 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:31:48.468 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:31:48.468 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:31:48.468 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:31:48.895 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:31:48.954 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:48.955 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:48.955 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:48.955 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:49.366 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:31:49.839 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:31:49.956 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:49.956 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:49.956 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:49.956 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:50.312 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:31:50.782 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:31:50.958 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:50.958 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:50.958 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:50.958 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:51.249 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:31:51.721 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:31:51.959 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:51.959 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:51.959 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:51.959 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:52.192 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:31:52.665 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:31:52.960 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:31:52.960 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:31:52.961 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:31:52.961 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:31:53.138 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:31:53.608 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:31:54.076 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:31:54.547 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:31:55.017 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:31:55.488 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:31:55.962 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:31:56.432 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:31:56.897 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:31:57.362 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:31:57.836 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:31:58.308 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:31:58.780 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:31:59.251 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:31:59.725 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:32:00.197 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:32:00.665 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:32:01.137 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:32:01.610 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:32:02.083 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:32:02.554 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:32:03.027 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:32:03.475 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:03.475 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:03.482 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:03.482 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:03.482 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:03.482 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:03.483 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:03.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:03.483 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:03.483 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:03.483 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:03.483 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:03.483 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:32:08.493 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:08.493 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:08.494 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:08.494 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:08.494 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:08.494 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:08.504 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:08.504 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:08.505 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:08.505 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:08.505 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:32:08.507 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:32:08.507 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:32:08.507 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:08.507 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:08.507 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:08.508 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:32:08.508 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:08.508 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:32:08.508 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:08.509 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:32:08.509 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:32:08.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:08.509 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:08.509 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:08.509 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:32:08.509 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:08.509 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:32:08.509 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:08.511 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:32:08.511 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:32:08.511 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:08.511 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:08.511 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:08.511 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:32:08.512 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:08.512 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:32:08.512 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:08.514 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:32:08.515 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:32:08.515 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:32:08.515 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.515 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:08.520 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:32:08.993 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:32:09.029 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:32:09.029 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:32:09.029 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:32:09.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:09.031 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:09.031 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:09.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:09.031 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:09.031 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:09.031 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:09.031 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:09.031 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:09.037 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:09.037 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:09.041 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:09.041 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:09.041 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:09.041 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:09.044 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:09.044 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:09.044 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:09.044 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:32:09.045 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:09.045 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:09.045 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:09.045 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:09.045 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:09.045 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:09.045 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:09.045 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:09.045 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=115 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:14.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:14.053 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:14.053 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:14.053 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:14.053 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:14.053 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:14.066 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:14.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:14.066 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:14.066 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:14.066 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:32:14.068 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:32:14.068 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:32:14.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:14.069 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:14.069 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:14.069 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:32:14.069 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:14.069 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:32:14.069 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:14.071 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:32:14.071 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:32:14.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:14.071 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:14.071 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:14.071 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:32:14.071 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:14.071 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:32:14.071 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:14.073 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:32:14.073 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:32:14.073 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:14.073 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:14.073 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:14.073 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:32:14.073 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:14.073 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:32:14.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:32:14.076 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:32:14.076 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:32:14.076 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.076 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:14.081 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:32:14.550 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:32:14.593 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:32:14.593 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:32:14.594 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:32:14.594 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:14.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:14.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:14.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:14.622 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.622 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:14.622 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:14.622 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:14.622 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:14.640 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:14.641 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:14.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.641 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:14.752 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.752 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.764 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.764 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:14.770 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.770 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.770 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:14.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:14.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.771 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:14.771 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:14.771 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:14.771 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:14.782 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:32:14.782 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:32:14.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.782 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.946 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:14.949 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.949 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.949 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:32:14.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:14.973 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:14.973 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:14.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:14.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:14.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:14.974 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:14.974 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:14.974 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:14.974 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:15.016 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:32:15.021 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:15.021 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:15.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:15.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:15.079 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:15.079 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:15.079 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:15.080 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:15.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:15.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:15.408 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:15.408 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:15.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:15.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:15.424 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:15.430 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:15.430 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:15.430 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:15.430 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:15.432 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:15.432 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:15.432 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:15.432 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:15.432 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:15.481 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:32:15.482 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:32:15.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:15.482 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:15.487 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:32:15.959 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:32:16.080 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:16.080 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:16.081 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:16.081 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:16.276 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:16.278 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:16.282 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:16.282 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:16.282 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:32:16.297 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:16.297 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:16.298 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:16.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:16.304 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:16.304 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:16.305 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:16.305 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:16.305 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:16.305 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:16.305 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:32:16.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=483 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=483 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=483 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.306 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=484 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:16.307 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=485 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:21.309 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:21.309 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:21.309 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:21.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:21.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:21.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:21.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:21.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:21.319 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:21.319 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:21.319 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:32:21.320 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:32:21.321 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:32:21.321 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:21.321 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:21.321 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:21.321 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:32:21.321 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:21.321 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:32:21.321 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:21.322 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:32:21.322 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:32:21.322 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:21.322 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:21.322 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:21.322 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:32:21.322 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:21.322 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:32:21.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:21.324 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:32:21.324 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:32:21.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:21.324 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:21.324 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:21.324 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:32:21.324 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:21.324 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:32:21.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:32:21.326 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:32:21.326 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:32:21.326 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.326 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:21.331 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:32:21.803 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:32:21.842 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:32:21.843 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:32:21.843 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:32:21.843 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:21.852 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:21.852 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:21.852 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:21.861 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:21.861 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:21.861 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:21.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:21.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:21.863 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:21.863 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:21.863 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:21.863 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:21.894 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:21.895 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:21.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:21.895 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:22.275 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:32:22.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:22.329 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:22.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:22.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:22.747 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:32:23.217 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:32:23.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:23.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:23.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:23.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:23.688 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:32:24.162 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:32:24.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:24.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:24.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:24.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:24.634 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:32:25.106 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:32:25.334 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:25.334 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:25.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:25.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:25.577 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:32:26.050 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:32:26.335 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:26.335 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:26.335 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:26.335 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:26.523 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:32:26.899 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:26.900 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:26.904 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:26.904 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:26.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:26.915 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:26.915 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:26.920 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:26.920 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:26.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:26.921 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:26.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:26.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:26.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:26.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:26.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:26.941 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:32:26.941 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:32:26.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:26.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:26.995 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:32:27.467 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:32:27.940 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:32:28.412 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:32:28.884 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:32:29.357 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:32:29.830 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:32:30.303 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:32:30.776 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:32:31.248 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:32:31.717 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:32:31.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:31.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:31.951 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:31.951 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:31.951 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:32:31.965 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:31.965 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:31.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:31.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:31.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:31.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:31.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:31.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:31.972 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:31.972 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:31.972 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:31.972 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:31.994 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:31.994 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:31.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:31.994 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:32.184 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:32:32.657 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:32:33.129 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:32:33.600 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:32:34.071 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:32:34.544 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:32:35.017 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:32:35.489 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:32:35.961 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:32:36.435 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:32:36.907 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:32:36.998 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:36.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:37.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:37.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:37.022 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:37.022 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:37.022 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:37.027 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:37.027 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:37.027 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:37.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:37.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:37.029 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:37.029 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:37.029 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:37.029 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:37.041 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:32:37.041 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:32:37.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:37.042 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:37.377 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:32:37.850 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:32:38.323 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:32:38.795 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:32:39.269 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:32:39.742 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:32:40.214 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:32:40.685 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:32:41.158 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:32:41.631 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:32:42.045 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:42.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:42.050 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:42.050 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:42.050 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:32:42.065 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:42.066 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:42.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:42.066 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:42.071 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:42.071 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:42.071 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:42.071 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:32:42.072 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:42.072 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:42.072 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:42.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4483 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:42.072 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4483 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:42.073 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4483 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:42.073 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4483 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:42.073 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4483 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:42.073 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4483 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:32:47.077 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:32:47.077 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:32:47.077 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:47.077 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:47.077 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:47.077 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:47.086 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:32:47.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:47.087 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:47.087 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:32:47.087 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:32:47.089 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:32:47.089 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:32:47.089 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:47.089 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:47.090 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:32:47.090 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:32:47.090 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:32:47.090 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:32:47.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:47.092 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:32:47.092 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:32:47.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:47.092 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:47.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:32:47.092 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:32:47.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:32:47.092 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:32:47.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:47.094 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:32:47.094 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:32:47.094 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:47.094 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:32:47.095 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:32:47.095 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:32:47.095 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:32:47.095 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:32:47.095 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.098 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:32:47.099 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:32:47.099 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:32:47.099 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:32:47.100 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:32:47.103 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:32:47.576 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:32:47.618 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:32:47.618 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:32:47.619 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:47.619 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:32:47.629 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:47.629 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:47.629 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:47.645 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:47.645 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:47.646 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:47.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:47.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:47.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:47.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:47.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:47.653 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:47.667 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:47.668 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:47.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:47.668 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:48.048 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:32:48.102 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:48.102 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:48.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:48.102 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:48.519 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:32:48.990 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:32:49.103 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:49.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:49.104 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:49.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:49.463 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:32:49.936 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:32:50.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:50.104 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:50.105 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:50.105 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:50.408 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:32:50.879 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:32:51.105 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:51.105 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:51.106 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:51.106 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:51.350 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:32:51.823 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:32:52.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:32:52.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:32:52.107 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:32:52.107 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:32:52.296 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:32:52.673 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:52.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:52.677 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:52.677 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:52.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:52.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:52.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:52.703 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:52.703 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:52.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:52.704 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:52.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:52.705 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:52.705 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:52.705 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:52.705 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:52.713 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:32:52.713 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:32:52.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:52.713 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:52.767 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:32:53.239 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:32:53.711 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:32:54.185 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:32:54.659 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:32:55.133 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:32:55.606 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:32:56.079 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:32:56.549 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:32:57.016 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:32:57.484 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:32:57.716 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:57.717 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:57.721 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:57.721 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:57.721 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:32:57.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:57.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:57.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:57.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:32:57.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:32:57.736 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:32:57.737 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:32:57.738 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:57.738 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:57.738 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:57.738 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:32:57.738 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:32:57.763 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:32:57.763 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:32:57.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:57.764 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:32:57.957 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:32:58.429 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:32:58.901 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:32:59.372 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:32:59.846 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:33:00.318 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:33:00.790 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:33:01.261 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:33:01.732 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:33:02.206 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:33:02.678 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:33:02.768 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:02.769 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:02.772 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:02.772 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:02.791 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:02.791 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:02.791 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:02.797 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:02.797 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:02.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:02.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:02.798 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:02.798 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:02.798 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:02.798 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:02.798 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:02.814 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:33:02.814 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:33:02.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:02.814 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:03.149 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:33:03.621 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:33:04.091 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:33:04.564 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:33:05.035 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:33:05.507 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:33:05.971 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:33:06.436 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:33:06.900 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:33:07.365 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:33:07.819 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:07.819 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:07.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:07.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:07.824 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:33:07.833 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:33:07.837 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:07.837 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:07.837 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:07.837 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:07.839 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:33:07.839 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:33:07.839 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:33:07.839 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:33:07.839 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:33:07.839 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:33:07.839 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:33:07.839 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4491 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:07.839 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4491 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:07.839 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4491 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:07.839 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4491 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:07.839 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4491 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:12.848 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:33:12.848 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:33:12.848 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:33:12.848 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:33:12.848 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:33:12.849 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:33:12.857 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:33:12.857 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:33:12.857 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:12.858 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:33:12.858 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:33:12.860 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:33:12.860 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:33:12.860 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:33:12.860 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:12.861 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:33:12.861 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:33:12.861 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:33:12.861 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:33:12.861 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:12.862 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:33:12.862 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:33:12.862 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:33:12.862 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:12.862 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:33:12.863 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:33:12.863 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:33:12.863 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:33:12.863 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:12.864 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:33:12.864 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:33:12.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:33:12.865 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:12.865 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:33:12.865 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:33:12.865 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:33:12.865 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:33:12.865 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.867 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:33:12.868 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:33:12.868 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:33:12.868 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:12.872 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:33:13.348 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:33:13.398 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:33:13.400 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:33:13.402 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:33:13.404 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:13.424 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:13.424 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:13.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:13.443 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:13.443 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:13.444 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:13.446 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:13.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:13.452 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:13.453 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:13.453 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:13.453 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:13.486 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:13.486 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:13.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:13.486 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:13.820 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:33:13.870 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:13.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:13.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:13.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:14.291 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:33:14.762 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:33:14.872 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:14.872 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:14.873 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:14.873 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:15.233 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:33:15.707 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:33:15.874 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:15.874 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:15.874 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:15.874 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:16.179 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:33:16.650 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:33:16.875 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:16.875 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:16.875 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:16.875 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:17.122 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:33:17.593 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:33:17.876 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:17.877 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:17.877 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:17.877 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:18.064 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:33:18.490 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:18.491 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:18.495 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:18.495 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:18.512 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:18.512 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:18.512 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:18.518 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:18.518 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:18.518 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:18.519 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:18.520 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:18.520 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:18.520 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:18.520 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:18.520 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:18.531 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:33:18.531 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:33:18.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:18.531 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:18.534 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:33:19.006 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:33:19.479 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:33:19.951 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:33:20.424 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:33:20.897 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:33:21.370 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:33:21.843 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:33:22.315 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:33:22.786 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:33:23.259 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:33:23.534 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:23.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:23.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:23.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:23.539 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:33:23.557 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:23.557 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:23.557 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:23.563 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:23.563 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:23.563 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:23.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:23.565 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:23.565 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:23.565 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:23.565 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:23.565 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:23.583 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:23.583 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:23.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:23.583 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:23.728 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:33:24.200 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:33:24.670 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:33:25.141 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:33:25.614 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:33:26.087 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:33:26.559 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:33:27.030 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:33:27.501 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:33:27.974 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:33:28.447 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:33:28.589 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:28.590 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:28.593 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:28.593 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:28.609 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:28.609 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:28.609 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:28.615 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:28.615 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:28.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:28.615 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:28.617 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:28.617 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:28.617 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:28.617 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:28.617 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:28.628 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:33:28.628 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:33:28.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:28.628 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:28.914 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:33:29.380 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:33:29.851 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:33:30.325 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:33:30.797 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:33:31.269 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:33:31.740 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:33:32.212 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:33:32.686 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:33:33.156 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:33:33.628 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:33:33.631 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:33.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:33.635 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:33.635 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:33.636 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:33:33.648 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:33.649 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:33.649 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:33.649 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:33.653 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:33:33.654 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:33:33.654 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:33:33.654 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:33:33.654 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:33:33.655 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:33:33.655 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:33:33.655 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4495 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:33.655 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4495 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:33.655 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4495 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:33.655 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4495 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:33.655 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4495 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:33.655 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4495 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:33.655 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4495 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:38.659 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:33:38.659 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:33:38.659 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:33:38.659 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:33:38.659 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:33:38.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:33:38.666 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:33:38.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:33:38.666 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:38.666 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:33:38.666 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:33:38.669 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:33:38.669 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:33:38.670 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:33:38.670 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:38.670 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:33:38.670 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:33:38.671 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:33:38.671 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:33:38.671 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:38.673 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:33:38.673 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:33:38.673 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:33:38.673 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:38.674 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:33:38.674 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:33:38.674 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:33:38.674 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:33:38.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:38.676 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:33:38.677 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:33:38.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:33:38.677 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:33:38.677 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:33:38.677 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:33:38.677 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:33:38.677 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:33:38.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:38.681 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.682 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:33:38.682 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:33:38.682 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:33:38.683 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.683 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.684 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:33:38.687 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:33:39.158 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:33:39.202 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:33:39.202 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:33:39.203 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:33:39.203 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:39.220 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:39.221 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:39.221 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:39.238 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:39.239 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:39.239 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:39.248 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:39.254 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:39.255 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:39.255 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:39.255 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:39.255 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:39.296 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:39.296 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:39.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:39.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:39.631 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:33:39.686 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:39.686 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:39.686 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:39.687 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:40.102 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:33:40.575 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:33:40.687 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:40.687 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:40.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:40.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:41.048 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:33:41.520 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:33:41.688 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:41.688 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:41.688 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:41.688 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:41.993 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:33:42.466 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:33:42.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:42.689 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:42.689 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:42.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:42.939 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:33:43.405 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:33:43.689 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:43.690 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:43.690 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:43.691 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:43.873 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:33:44.300 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:44.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:44.304 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:44.304 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:44.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:44.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:44.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:44.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:44.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:44.330 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:44.331 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:44.333 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:44.333 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:44.333 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:44.333 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:44.333 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:44.336 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:33:44.336 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:33:44.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:44.337 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:44.342 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:33:44.810 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:33:45.283 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:33:45.755 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:33:46.226 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:33:46.699 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:33:47.172 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:33:47.643 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:33:48.115 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:33:48.587 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:33:49.061 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:33:49.339 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:49.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:49.343 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:49.343 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:49.343 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:33:49.357 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:49.357 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:49.357 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:49.364 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:49.364 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:49.364 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:49.364 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:49.366 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:49.366 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:49.366 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:49.366 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:49.366 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:49.388 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:49.388 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:49.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:49.389 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:49.533 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:33:50.004 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:33:50.477 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:33:50.941 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:33:51.412 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:33:51.885 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:33:52.356 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:33:52.828 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:33:53.300 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:33:53.771 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:33:54.244 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:33:54.392 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:54.393 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:54.397 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:54.398 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:54.413 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:54.413 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:54.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:54.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:54.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:54.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:33:54.420 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:54.422 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:54.422 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:33:54.422 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:33:54.422 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:33:54.422 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:33:54.477 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:33:54.477 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:33:54.477 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:54.478 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:54.717 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:33:55.189 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:33:55.662 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:33:56.135 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:33:56.607 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:33:57.074 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:33:57.543 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:33:58.015 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:33:58.487 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:33:58.960 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:33:59.431 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:33:59.481 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:33:59.482 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:33:59.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:33:59.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:33:59.485 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:33:59.499 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:33:59.500 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:33:59.500 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:33:59.500 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:33:59.506 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:33:59.507 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:33:59.507 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:33:59.507 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:33:59.507 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:33:59.508 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:33:59.508 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:33:59.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4505 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4505 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.508 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4506 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.509 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:33:59.510 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4507 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:34:04.511 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:34:04.511 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:34:04.511 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:34:04.512 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:34:04.512 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:34:04.512 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:34:04.525 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:34:04.526 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:34:04.526 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:04.527 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:34:04.527 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:34:04.529 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:34:04.529 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:34:04.529 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:34:04.530 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:04.530 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:34:04.530 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:34:04.530 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:34:04.530 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:34:04.530 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:04.531 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:34:04.531 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:34:04.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:34:04.532 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:04.532 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:34:04.532 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:34:04.532 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:34:04.532 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:34:04.532 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:04.533 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:34:04.533 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:34:04.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:34:04.534 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:04.534 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:34:04.534 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:34:04.534 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:34:04.534 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:34:04.534 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:34:04.536 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:34:04.536 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:34:04.536 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.536 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:04.537 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:04.541 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:34:05.005 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:34:05.056 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:34:05.057 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:34:05.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:05.058 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:34:05.075 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.075 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.076 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:05.088 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.088 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:05.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:05.111 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.112 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:05.112 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:05.112 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:34:05.112 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:34:05.143 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:05.143 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:05.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.144 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.383 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:05.387 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.387 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.405 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.405 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.405 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:05.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.411 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:05.411 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:05.413 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.413 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:05.413 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:05.413 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:34:05.413 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:34:05.423 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:34:05.423 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:34:05.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.423 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.477 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:34:05.538 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:05.539 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:05.804 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:05.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.809 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.809 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:34:05.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:05.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:05.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:05.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:05.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:05.836 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.837 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:05.837 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:05.837 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:34:05.837 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:34:05.847 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:05.847 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:05.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.848 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:05.948 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:34:06.419 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:34:06.539 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:06.540 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:06.540 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:06.540 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:06.574 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:06.575 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:06.580 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:06.580 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:06.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:06.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:06.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:06.604 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:06.604 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:06.604 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:06.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:06.606 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:06.606 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:06.606 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:06.606 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:34:06.606 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:34:06.653 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:34:06.653 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:34:06.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:06.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:06.890 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:34:07.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:07.208 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:07.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:07.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:07.213 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:34:07.223 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:07.223 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:07.223 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:07.223 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:07.223 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:34:07.224 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:34:07.224 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:34:07.224 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:34:07.224 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:34:07.224 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:34:07.224 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:34:12.236 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:34:12.236 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:34:12.236 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:34:12.236 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:34:12.236 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:34:12.236 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:34:12.246 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:34:12.248 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:34:12.248 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:12.248 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:34:12.248 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:34:12.251 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:34:12.251 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:34:12.251 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:34:12.251 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:12.252 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:34:12.252 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:34:12.252 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:34:12.252 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:34:12.252 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:12.255 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:34:12.256 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:34:12.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:34:12.256 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:12.256 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:34:12.256 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:34:12.256 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:34:12.256 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:34:12.256 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:12.259 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:34:12.259 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:34:12.259 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:34:12.259 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:34:12.260 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:34:12.260 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:34:12.260 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:34:12.260 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:34:12.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:34:12.265 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:34:12.266 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:34:12.266 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:34:12.266 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.266 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:34:12.267 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:34:12.271 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:34:12.743 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:34:12.794 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:34:12.795 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:34:12.796 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:34:12.797 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:12.808 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:12.808 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:12.808 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:12.823 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:12.823 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:12.823 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:12.825 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:12.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:12.829 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:12.829 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:12.829 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:34:12.829 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:34:12.833 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:12.834 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:12.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:12.834 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:13.216 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:34:13.270 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:13.271 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:13.271 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:13.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:13.689 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:34:14.162 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:34:14.271 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:14.272 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:14.272 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:14.274 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:14.634 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:34:15.107 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:34:15.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:15.273 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:15.273 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:15.275 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:15.580 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:34:16.053 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:34:16.273 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:16.274 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:16.274 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:16.276 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:16.524 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:34:16.997 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:34:17.275 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:34:17.275 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:34:17.275 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:34:17.277 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:34:17.470 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:34:17.937 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:34:18.407 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:34:18.879 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:34:19.352 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:34:19.825 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:34:20.294 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:34:20.759 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:34:21.230 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:34:21.701 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:34:22.171 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:34:22.642 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:34:23.113 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:34:23.586 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:34:24.059 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:34:24.532 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:34:25.005 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:34:25.478 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:34:25.950 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:34:26.423 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:34:26.895 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:34:27.368 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:34:27.841 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:34:28.314 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:34:28.786 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:34:29.257 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:34:29.730 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:34:30.203 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:34:30.676 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:34:31.146 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:34:31.617 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:34:32.090 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:34:32.563 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:34:32.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:32.837 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:32.844 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:32.844 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:32.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:32.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:32.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:32.859 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:32.859 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:32.859 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:32.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:32.860 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:32.860 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:32.860 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:32.860 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:34:32.860 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:34:32.889 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:34:32.889 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:34:32.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:32.889 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:33.035 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:34:33.508 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:34:33.977 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:34:34.450 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:34:34.923 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:34:35.390 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:34:35.855 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:34:36.320 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:34:36.784 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:34:37.253 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:34:37.726 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:34:38.198 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:34:38.671 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:34:39.140 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:34:39.613 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:34:40.079 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:34:40.551 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:34:41.023 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:34:41.497 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:34:41.969 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:34:42.442 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:34:42.914 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:34:43.383 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:34:43.850 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:34:44.322 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:34:44.793 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:34:45.263 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:34:45.729 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:34:46.192 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:34:46.656 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 03:34:47.119 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 03:34:47.581 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 03:34:48.044 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 03:34:48.508 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 03:34:48.972 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 03:34:49.434 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 03:34:49.898 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 03:34:50.361 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 03:34:50.824 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 03:34:51.288 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 03:34:51.751 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 03:34:52.214 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 03:34:52.677 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 03:34:52.891 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:52.891 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:52.893 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:52.893 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:52.893 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:34:52.901 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:52.901 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:52.901 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:52.907 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:34:52.908 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:34:52.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:34:52.908 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:34:52.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:52.910 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:52.910 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:52.910 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:34:52.910 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:34:52.950 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:34:52.950 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:34:52.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:52.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:34:53.140 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 03:34:53.604 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 03:34:54.068 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 03:34:54.531 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 03:34:54.994 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 03:34:55.461 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 03:34:55.930 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 03:34:56.398 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 03:34:56.864 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 03:34:57.335 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 03:34:57.802 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 03:34:58.272 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 03:34:58.742 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 03:34:59.213 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 03:34:59.681 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 03:35:00.150 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 03:35:00.617 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 03:35:01.084 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 03:35:01.553 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 03:35:02.024 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 03:35:02.495 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 03:35:02.966 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 03:35:03.437 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 03:35:03.949 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 03:35:04.416 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 03:35:04.881 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 03:35:05.345 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 03:35:06.189 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 03:35:06.826 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 03:35:07.293 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 03:35:07.764 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 03:35:08.235 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 03:35:08.705 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 03:35:09.176 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 03:35:09.646 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 03:35:10.117 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 03:35:10.586 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 03:35:11.055 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 03:35:11.526 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 03:35:11.996 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 03:35:12.467 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 03:35:12.935 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 03:35:12.953 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:12.953 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:12.958 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:12.958 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:12.970 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:12.970 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:12.970 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:12.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:12.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:12.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:12.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:12.978 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:12.978 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:12.978 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:12.978 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:12.978 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:13.024 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:35:13.024 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:35:13.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:13.024 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:13.400 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 03:35:13.864 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 03:35:14.334 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 03:35:14.803 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 03:35:15.272 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 03:35:15.744 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 03:35:16.214 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 03:35:16.682 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 03:35:17.146 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 03:35:17.614 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 03:35:18.081 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 03:35:18.549 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 03:35:19.013 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 03:35:19.484 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 03:35:19.955 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 03:35:20.425 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 03:35:20.896 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 03:35:21.365 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 03:35:21.830 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 03:35:22.294 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 03:35:22.765 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 03:35:23.231 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 03:35:23.702 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 03:35:24.173 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 03:35:24.644 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 03:35:25.115 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 03:35:25.587 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 03:35:26.054 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 03:35:26.525 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 03:35:26.998 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 03:35:27.469 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 03:35:27.938 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 03:35:28.405 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 03:35:28.874 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 03:35:29.340 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 03:35:29.811 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 03:35:30.279 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 03:35:30.745 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 03:35:31.215 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 03:35:31.686 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 03:35:32.158 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 03:35:32.628 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 03:35:33.026 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:33.027 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:33.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:33.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:33.034 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:35:33.049 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:33.050 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:33.050 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:33.050 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:33.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:35:33.057 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:35:33.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:35:33.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:35:33.057 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:35:33.057 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:35:33.058 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:35:33.058 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.058 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.058 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.058 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.058 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17434 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.059 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:33.060 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=17435 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:35:38.061 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:35:38.061 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:35:38.061 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:35:38.062 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:35:38.062 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:35:38.062 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:35:38.068 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:35:38.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:35:38.069 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:38.069 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:35:38.069 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:35:38.070 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:35:38.070 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:35:38.070 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:35:38.070 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:38.071 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:35:38.071 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:35:38.071 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:35:38.071 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:35:38.071 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:38.072 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:35:38.072 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:35:38.072 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:35:38.072 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:38.072 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:35:38.072 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:35:38.073 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:35:38.073 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:35:38.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:38.074 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:35:38.074 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:35:38.074 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:35:38.074 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:38.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:35:38.074 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:35:38.075 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:35:38.075 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:35:38.075 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.077 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:35:38.078 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:35:38.078 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:35:38.078 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.078 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:35:38.079 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:35:38.079 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:35:38.079 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:35:43.091 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:35:43.092 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:35:43.092 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:35:43.092 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:35:43.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:35:43.092 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:35:43.103 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:35:43.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:35:43.104 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:43.104 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:35:43.104 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:35:43.106 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:35:43.106 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:35:43.106 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:35:43.106 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:43.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:35:43.107 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:35:43.107 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:35:43.107 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:35:43.107 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:43.109 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:35:43.109 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:35:43.109 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:35:43.109 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:43.109 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:35:43.109 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:35:43.110 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:35:43.110 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:35:43.110 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:43.111 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:35:43.111 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:35:43.111 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:35:43.111 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:35:43.112 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:35:43.112 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:35:43.112 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:35:43.112 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:35:43.112 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:43.114 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:35:43.114 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:35:43.114 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:35:43.115 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:35:43.115 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:35:43.115 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.115 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.116 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:35:43.120 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:35:43.585 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:35:43.637 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:35:43.638 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:35:43.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:43.640 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:35:43.654 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:43.654 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:43.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:43.675 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:43.675 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:43.675 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:43.677 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:43.681 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:43.681 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:43.682 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:43.682 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:43.682 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:43.723 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:43.723 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:43.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:43.724 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:43.920 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:43.922 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:43.923 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:43.923 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:43.929 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:43.929 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:43.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:43.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:43.931 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:43.931 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:43.931 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:43.931 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:43.931 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:43.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:43.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:43.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:43.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.053 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:35:44.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:44.118 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:44.118 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:44.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:44.156 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:44.161 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:44.161 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:44.175 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:44.176 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:44.176 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:44.176 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:44.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.178 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:44.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:44.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:44.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:44.187 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:44.187 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:44.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.187 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.396 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:44.401 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:44.401 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:44.419 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:44.419 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:44.419 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:44.425 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:44.425 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:44.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:44.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:44.427 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.427 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:44.427 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:44.427 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:44.427 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:44.471 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:35:44.471 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:35:44.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.472 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.521 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:35:44.771 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.773 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:44.777 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:44.777 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:44.777 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:35:44.791 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:44.793 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:44.793 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:44.793 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:44.794 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.794 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:44.794 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:44.794 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:44.794 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:44.796 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:35:44.796 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:35:44.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.796 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:44.987 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:35:45.089 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.090 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:45.094 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:45.094 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:45.094 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:35:45.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:45.107 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:45.107 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:45.107 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:45.108 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.108 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:45.108 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:45.108 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:45.108 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:45.118 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:45.119 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:35:45.119 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:35:45.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.119 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:45.119 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:45.119 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:45.407 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.408 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:45.411 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:45.412 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:45.412 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:35:45.429 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:45.429 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:45.429 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:45.435 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:45.435 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:45.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:45.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:45.437 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.437 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:45.437 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:45.437 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:45.437 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:45.451 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:35:45.454 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:45.454 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:45.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.454 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:45.919 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:35:46.119 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:46.120 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:46.120 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:46.120 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:46.391 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:35:46.857 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:35:47.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:47.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:47.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:47.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:47.325 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:35:47.796 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:35:47.951 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:47.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:47.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:47.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:47.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:47.971 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:47.971 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:47.971 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:47.973 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:47.973 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:47.973 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:47.973 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:47.973 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:47.976 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:47.976 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:47.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:47.976 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:48.120 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:35:48.122 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:35:48.122 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:35:48.122 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:35:48.262 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:35:48.728 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:35:49.197 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:35:49.665 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:35:50.135 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:35:50.521 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:50.523 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:50.527 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:50.527 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:50.543 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:50.544 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:50.544 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:50.544 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:50.546 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:50.546 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:50.546 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:50.546 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:50.547 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:50.602 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:35:50.602 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:50.603 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:50.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:50.603 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:51.069 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:35:51.534 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:35:52.001 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:35:52.466 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:35:52.936 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:35:53.088 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:53.089 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:53.093 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:53.093 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:53.103 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:53.103 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:53.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:53.109 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:53.109 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:53.109 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:53.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:53.110 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:53.110 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:53.110 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:53.110 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:53.110 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:53.113 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:35:53.113 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:35:53.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:53.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:53.403 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:35:53.869 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:35:54.340 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:35:54.812 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:35:55.284 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:35:55.749 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:35:55.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:55.831 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:55.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:55.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:55.835 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:35:55.852 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:55.853 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:55.853 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:55.853 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:55.855 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:55.855 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:55.855 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:55.855 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:55.855 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:55.882 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:35:55.882 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:35:55.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:55.882 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:56.217 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:35:56.685 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:35:57.156 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:35:57.622 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:35:58.089 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:35:58.559 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:35:58.640 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:58.641 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:58.644 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:58.644 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:58.644 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:35:58.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:35:58.651 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:35:58.651 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:35:58.651 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:35:58.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:58.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:35:58.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:35:58.653 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:35:58.653 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:35:58.697 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:35:58.697 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:35:58.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:58.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:35:59.026 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:35:59.493 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:35:59.959 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:36:00.423 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:36:00.889 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:36:01.356 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:36:01.436 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:01.438 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:01.442 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:01.442 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:01.442 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:36:01.455 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:01.455 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:01.455 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:01.455 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:01.456 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:01.456 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:01.456 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:01.456 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:01.456 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:36:01.456 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:36:01.456 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:36:06.468 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:36:06.468 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:36:06.468 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:06.468 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:06.468 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:06.468 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:06.478 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:06.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:36:06.479 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:06.479 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:36:06.479 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:36:06.482 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:36:06.482 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:36:06.482 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:36:06.482 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:06.483 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:06.483 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:36:06.483 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:36:06.483 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:36:06.483 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:06.484 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:36:06.484 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:36:06.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:36:06.485 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:06.485 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:06.485 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:36:06.485 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:36:06.485 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:36:06.485 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:06.486 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:36:06.486 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:36:06.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:36:06.486 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:06.486 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:06.486 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:36:06.486 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:36:06.486 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:36:06.486 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:36:06.489 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:36:06.489 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:36:06.489 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:36:06.489 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.490 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:06.494 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:36:06.964 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:36:07.006 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:36:07.007 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:36:07.008 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:36:07.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:07.021 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:07.021 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:07.021 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:07.029 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:07.029 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:07.029 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:07.031 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:07.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:07.033 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:07.033 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:07.033 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:07.033 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:07.055 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:07.055 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:07.055 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:07.056 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:07.434 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:36:07.491 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:07.491 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:07.492 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:07.492 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:07.905 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:36:08.374 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:36:08.492 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:08.493 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:08.493 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:08.493 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:08.843 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:36:09.315 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:36:09.494 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:09.494 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:09.494 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:09.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:09.786 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:36:10.171 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:10.173 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:10.177 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:10.177 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:10.193 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:10.193 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:10.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:10.198 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:10.198 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:10.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:10.199 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:10.201 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:10.201 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:10.201 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:10.201 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:10.201 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:10.255 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:36:10.255 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:36:10.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:10.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:10.257 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:36:10.495 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:10.495 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:10.496 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:10.496 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:10.725 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:36:11.193 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:36:11.496 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:11.497 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:11.497 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:11.497 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:11.662 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:36:12.131 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:36:12.601 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:36:13.067 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:36:13.452 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:13.453 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:13.454 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:13.454 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:13.454 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:36:13.467 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:13.467 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:13.467 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:13.473 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:13.473 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:13.473 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:13.473 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:13.475 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:13.475 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:13.475 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:13.475 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:13.475 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:13.484 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:13.484 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:13.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:13.484 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:13.536 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:36:14.004 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:36:14.472 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:36:14.941 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:36:15.411 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:36:15.882 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:36:16.350 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:36:16.759 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:16.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:16.766 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:16.766 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:16.778 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:16.778 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:16.778 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:16.784 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:16.784 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:16.784 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:16.784 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:16.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:16.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:16.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:16.786 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:16.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:16.817 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:36:16.817 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:36:16.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:16.818 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:16.818 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:36:17.282 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:36:17.751 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:36:18.223 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:36:18.692 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:36:19.159 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:36:19.631 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:36:19.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:19.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:19.977 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:19.977 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:19.977 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:36:19.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:19.991 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:19.991 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:19.991 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:19.992 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:19.992 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:19.992 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:19.992 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:19.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:36:19.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:36:19.992 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:36:24.992 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:36:24.992 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:36:24.993 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:24.993 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:24.993 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:24.993 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:24.996 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:24.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:36:24.996 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:24.996 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:36:24.996 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:36:24.997 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:36:24.997 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:36:24.997 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:36:24.998 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:24.998 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:24.998 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:36:24.998 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:36:24.998 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:36:24.998 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:24.999 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:36:24.999 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:36:24.999 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:36:24.999 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:24.999 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:24.999 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:36:24.999 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:36:24.999 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:36:24.999 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:25.000 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:36:25.000 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:36:25.000 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:36:25.000 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:25.000 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:25.000 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:36:25.000 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:36:25.000 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:36:25.000 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.002 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:36:25.002 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:36:25.002 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:36:25.003 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:25.003 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:25.007 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:36:25.472 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:36:25.526 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:36:25.528 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:36:25.530 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:25.531 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:36:25.547 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:25.547 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:25.547 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:25.560 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:25.560 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:25.561 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:25.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:25.567 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:25.567 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:25.567 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:25.567 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:25.567 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:25.607 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:25.607 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:25.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:25.607 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:25.928 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:25.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:25.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:25.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:25.940 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:36:25.950 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:25.950 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:25.950 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:25.956 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:25.956 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:25.956 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:25.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:25.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:25.958 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:25.958 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:25.958 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:25.958 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:25.984 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:36:25.984 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:36:25.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:25.985 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:26.005 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:26.005 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:26.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:26.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:26.405 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:36:26.460 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:26.461 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:26.465 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:26.465 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:26.465 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:36:26.485 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:26.485 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:26.485 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:26.491 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:26.491 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:26.492 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:26.492 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:26.493 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:26.493 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:26.493 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:26.493 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:26.493 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:26.543 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:26.543 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:26.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:26.543 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:26.871 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:36:27.006 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:27.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:27.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:27.007 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:27.343 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:36:27.813 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:36:28.007 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:28.007 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:28.007 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:28.008 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:28.281 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:36:28.751 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:36:29.009 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:29.009 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:29.009 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:29.009 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:29.222 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:36:29.611 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:29.614 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:29.617 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:29.617 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:29.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:29.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:29.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:29.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:29.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:29.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:29.642 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:29.643 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:29.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:29.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:29.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:29.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:29.691 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:36:29.692 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:36:29.692 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:36:29.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:29.693 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:30.010 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:30.011 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:30.011 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:30.011 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:30.157 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:36:30.627 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:36:31.096 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:36:31.568 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:36:32.037 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:36:32.506 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:36:32.585 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:32.587 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:32.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:32.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:32.592 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:36:32.606 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:32.606 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:32.606 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:32.606 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:32.611 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:32.612 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:32.612 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:32.612 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:32.612 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:36:32.612 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:36:32.612 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:36:32.613 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1657 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:36:32.613 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1657 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:36:32.613 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1657 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:36:32.613 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1657 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:36:32.613 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1657 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:36:32.613 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=1657 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:36:37.617 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:36:37.617 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:36:37.617 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:37.617 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:37.618 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:37.618 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:37.626 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:36:37.626 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:36:37.626 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:37.627 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:36:37.627 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:36:37.629 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:36:37.629 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:36:37.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:36:37.629 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:37.629 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:36:37.629 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:36:37.629 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:36:37.629 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:36:37.629 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:37.631 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:36:37.631 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:36:37.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:36:37.631 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:37.631 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:36:37.631 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:36:37.631 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:36:37.631 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:36:37.631 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:37.632 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:36:37.632 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:36:37.633 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:36:37.633 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:36:37.633 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:36:37.633 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:36:37.633 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:36:37.633 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:36:37.633 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:36:37.635 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:36:37.635 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.635 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:36:37.636 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:36:37.640 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:36:38.107 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:36:38.157 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:36:38.158 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:36:38.159 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:36:38.159 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:38.167 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:38.167 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:38.167 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:38.175 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:38.175 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:38.175 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:38.176 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:38.177 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:38.177 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:38.178 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:38.178 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:38.178 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:38.197 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:38.197 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:38.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:38.198 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:38.574 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:36:38.638 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:38.638 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:38.638 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:38.639 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:39.045 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:36:39.479 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:39.480 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:39.483 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:39.483 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:39.500 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:39.500 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:39.500 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:39.506 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:39.506 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:39.506 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:39.507 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:39.508 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:39.508 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:39.508 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:39.508 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:39.508 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:39.511 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:36:39.511 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:36:39.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:39.511 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:39.513 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:36:39.640 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:39.640 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:39.640 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:39.640 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:39.978 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:36:40.445 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:36:40.641 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:40.641 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:40.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:40.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:40.909 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:36:41.376 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:36:41.615 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:41.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:41.620 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:41.620 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:41.620 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:36:41.636 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:41.636 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:41.636 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:41.642 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:41.642 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:41.642 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:41.642 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:41.642 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:41.642 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:41.642 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:41.643 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:41.644 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:41.644 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:41.644 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:41.644 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:41.644 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:41.653 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:41.653 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:41.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:41.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:41.842 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:36:42.309 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:36:42.643 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:36:42.643 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:36:42.644 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:36:42.644 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:36:42.777 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:36:43.245 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:36:43.716 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:36:44.187 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:36:44.658 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:36:45.124 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:36:45.590 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:36:46.057 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:36:46.515 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:46.516 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:46.517 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:46.517 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:46.524 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:36:46.529 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:46.529 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:46.529 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:46.535 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:36:46.535 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:36:46.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:36:46.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:36:46.537 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:46.537 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:36:46.537 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:36:46.537 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:36:46.537 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:36:46.566 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:36:46.566 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:36:46.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:46.566 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:36:46.988 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:36:47.454 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:36:47.920 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:36:48.386 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:36:48.852 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:36:49.320 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:36:49.788 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:36:50.253 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:36:50.720 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:36:51.184 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:36:51.654 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:36:52.121 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:36:52.591 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:36:53.055 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:36:53.523 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:36:53.992 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:36:54.460 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:36:54.928 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:36:55.392 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:36:55.863 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:36:56.328 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:36:56.796 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:36:57.261 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:36:57.730 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:36:58.201 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:36:58.670 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:36:59.141 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:36:59.610 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:37:00.078 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:37:00.550 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:37:01.018 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:37:01.480 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:37:01.942 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:37:02.410 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:37:02.875 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:37:03.345 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:37:03.817 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:37:04.288 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:37:04.752 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:37:05.220 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:37:05.691 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:37:06.162 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:37:06.532 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:06.532 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:06.532 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:37:06.536 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:06.536 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:06.536 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:06.536 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:06.538 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:37:06.538 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:37:06.538 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:37:06.538 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:37:06.538 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:37:06.538 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:37:06.538 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:37:11.547 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:37:11.547 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:37:11.548 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:37:11.548 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:37:11.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:37:11.548 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:37:11.562 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:37:11.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:37:11.563 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:11.563 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:37:11.563 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:37:11.566 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:37:11.567 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:37:11.567 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:37:11.567 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:11.567 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:37:11.567 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:37:11.567 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:37:11.567 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:37:11.567 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:11.571 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:37:11.571 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:37:11.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:37:11.571 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:11.571 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:37:11.571 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:37:11.571 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:37:11.571 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:37:11.571 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:11.574 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:37:11.574 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:37:11.574 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:37:11.574 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:11.574 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:37:11.574 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:37:11.574 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:37:11.574 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:37:11.575 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:11.578 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:37:11.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:37:11.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:37:11.578 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:37:11.578 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:37:11.578 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:37:11.578 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:37:11.579 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:37:11.579 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:37:11.579 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:37:11.579 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:11.584 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:37:12.054 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:37:12.103 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:37:12.105 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:37:12.107 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:37:12.109 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:12.121 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:12.121 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:12.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:12.132 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:12.132 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:12.132 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:12.152 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:12.154 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:12.154 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:12.154 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:12.154 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:12.154 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:12.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:12.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:12.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:12.193 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:12.522 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:37:12.582 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:12.582 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:12.583 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:12.583 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:12.805 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:12.807 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:12.811 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:12.811 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:12.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:12.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:12.829 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:12.835 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:12.835 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:12.835 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:12.836 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:12.838 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:12.838 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:12.838 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:12.838 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:12.838 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:12.844 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:37:12.844 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:37:12.844 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:12.845 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:12.989 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:37:13.458 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:37:13.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:13.584 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:13.584 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:13.584 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:13.761 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:13.762 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:13.767 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:13.767 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:13.767 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:37:13.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:13.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:13.779 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:13.785 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:13.785 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:13.785 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:13.785 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:13.786 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:13.786 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:13.786 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:13.786 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:13.786 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:13.828 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:13.828 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:13.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:13.828 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:13.925 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:37:14.394 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:37:14.584 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:14.585 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:14.585 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:14.585 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:14.862 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:37:15.332 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:37:15.586 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:15.586 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:15.586 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:15.586 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:15.722 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:15.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:15.727 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:15.727 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:15.741 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:15.741 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:15.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:15.748 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:15.748 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:15.748 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:15.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:15.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:15.750 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:15.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:15.750 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:15.750 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:15.798 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:37:15.799 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:37:15.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:15.799 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:15.801 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:37:16.267 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:37:16.587 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:16.588 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:16.588 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:16.588 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:16.735 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:37:17.206 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:37:17.673 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:37:18.139 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:37:18.607 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:37:19.075 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:37:19.543 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:37:20.013 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:37:20.478 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:37:20.947 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:37:21.412 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:37:21.882 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:37:22.352 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:37:22.823 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:37:23.291 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:37:23.760 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:37:24.230 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:37:24.698 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:37:25.170 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:37:25.640 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:37:26.108 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:37:26.580 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:37:27.045 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:37:27.513 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:37:27.978 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:37:28.444 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:37:28.912 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:37:29.377 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:37:29.845 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:37:30.318 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:37:30.790 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:37:31.258 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:37:31.728 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:37:32.192 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:37:32.655 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:37:33.124 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:37:33.594 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:37:34.064 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:37:34.534 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:37:35.003 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:37:35.467 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:37:35.743 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:35.743 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:35.743 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:37:35.744 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:35.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:35.744 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:35.744 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:35.745 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:37:35.745 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:37:35.745 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:37:35.745 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:37:35.745 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:37:35.745 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:37:35.745 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:37:40.755 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:37:40.755 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:37:40.756 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:37:40.756 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:37:40.756 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:37:40.756 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:37:40.763 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:37:40.763 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:37:40.764 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:40.764 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:37:40.764 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:37:40.768 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:37:40.768 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:37:40.769 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:37:40.769 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:40.769 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:37:40.770 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:37:40.770 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:37:40.770 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:37:40.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:40.772 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:37:40.772 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:37:40.773 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:37:40.773 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:40.773 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:37:40.773 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:37:40.773 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:37:40.773 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:37:40.773 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:40.776 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:37:40.776 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:37:40.776 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:37:40.776 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:37:40.776 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:37:40.776 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:37:40.777 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:37:40.777 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:37:40.777 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:37:40.781 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:37:40.781 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:37:40.781 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.781 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.782 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:37:40.785 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:37:41.256 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:37:41.293 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:37:41.293 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:37:41.294 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:37:41.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:41.299 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:41.299 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:41.299 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:41.305 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:41.305 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:41.305 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:41.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:41.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:41.307 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:41.307 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:41.307 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:41.307 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:41.348 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:41.348 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:41.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:41.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:41.724 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:37:41.783 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:41.784 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:41.785 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:41.786 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:42.195 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:37:42.661 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:37:42.785 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:42.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:42.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:42.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:43.128 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:37:43.594 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:37:43.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:43.776 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:43.779 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:43.779 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:43.786 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:43.786 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:43.786 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:43.787 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:43.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:43.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:43.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:43.801 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:43.801 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:43.801 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:43.801 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:43.803 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:43.803 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:43.803 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:43.803 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:43.803 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:43.826 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:37:43.826 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:37:43.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:43.826 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:44.061 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:37:44.529 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:37:44.787 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:44.787 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:44.787 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:44.788 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:44.999 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:37:45.470 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:37:45.788 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:37:45.788 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:37:45.788 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:37:45.789 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:37:45.936 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:37:46.401 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:37:46.535 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:46.536 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:46.539 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:46.539 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:46.539 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:37:46.552 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:46.552 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:46.552 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:46.558 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:46.558 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:46.558 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:46.558 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:46.559 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:46.560 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:46.560 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:46.560 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:46.560 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:46.581 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:46.582 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:46.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:46.582 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:46.865 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:37:47.335 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:37:47.806 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:37:48.277 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:37:48.747 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:37:49.214 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:37:49.686 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:37:49.840 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:49.842 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:49.846 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:49.846 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:49.865 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:49.865 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:49.865 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:49.870 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:37:49.870 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:37:49.870 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:37:49.871 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:37:49.872 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:49.872 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:37:49.872 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:37:49.872 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:37:49.872 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:37:49.920 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:37:49.921 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:37:49.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:49.921 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:37:50.156 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:37:50.627 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:37:51.092 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:37:51.558 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:37:52.022 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:37:52.486 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:37:52.956 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:37:53.428 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:37:53.900 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:37:54.371 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:37:54.840 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:37:55.306 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:37:55.778 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:37:56.248 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:37:56.713 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:37:57.186 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:37:57.658 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:37:58.131 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:37:58.604 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:37:59.076 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:37:59.548 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:38:00.019 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:38:00.489 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:38:00.961 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:38:01.426 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:38:01.891 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:38:02.354 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:38:02.825 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:38:03.295 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:38:03.762 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:38:04.231 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:38:04.703 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:38:05.170 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:38:05.642 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:38:06.115 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:38:06.586 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:38:07.055 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:38:07.525 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:38:07.998 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:38:08.464 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:38:08.936 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:38:09.403 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:38:09.867 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:09.868 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:09.868 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:38:09.871 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:09.871 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:09.871 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:09.871 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:09.872 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:38:09.872 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:38:09.873 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:38:09.873 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:38:09.873 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:38:09.873 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:38:09.873 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:38:14.874 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:38:14.874 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:38:14.875 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:38:14.875 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:38:14.875 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:38:14.875 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:38:14.881 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:38:14.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:38:14.882 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:14.882 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:38:14.882 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:38:14.883 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:38:14.883 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:38:14.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:38:14.883 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:14.883 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:38:14.883 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:38:14.883 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:38:14.883 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:38:14.883 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:14.884 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:38:14.884 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:38:14.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:38:14.884 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:14.884 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:38:14.884 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:38:14.884 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:38:14.884 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:38:14.884 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:14.885 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:38:14.885 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:38:14.885 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:38:14.885 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:14.885 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:38:14.886 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:38:14.886 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:38:14.886 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:38:14.886 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:14.887 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:38:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:38:14.887 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:38:14.887 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:38:14.888 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:38:14.888 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:38:14.888 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.889 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:14.893 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:38:15.361 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:38:15.410 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:38:15.412 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:38:15.413 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:38:15.415 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:15.428 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:15.428 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:15.428 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:15.438 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:15.438 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:15.438 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:15.439 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:15.441 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:15.441 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:15.441 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:15.441 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:38:15.441 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:38:15.450 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:15.450 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:15.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:15.451 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:15.655 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:15.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:15.660 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:15.660 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:15.678 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:15.678 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:15.678 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:15.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:15.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:15.684 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:15.685 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:15.686 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:15.686 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:15.686 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:15.686 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:38:15.686 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:38:15.734 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:38:15.735 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:38:15.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:15.735 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:15.826 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:38:15.890 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:15.890 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:15.890 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:15.890 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:16.065 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.065 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:16.067 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:16.067 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:16.067 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:38:16.080 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:16.080 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:16.080 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:16.086 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:16.086 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:16.086 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:16.086 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:16.087 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.087 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:16.087 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:16.087 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:38:16.087 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:38:16.101 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:16.102 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:16.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.102 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.293 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:38:16.682 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:16.683 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:16.683 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:16.691 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:16.691 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:16.691 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:16.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:16.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:16.697 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:16.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:16.699 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.699 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:16.699 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:16.699 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:38:16.699 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:38:16.710 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:38:16.710 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:38:16.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:16.761 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:38:16.891 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:16.892 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:16.892 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:16.892 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:17.230 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:38:17.307 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:17.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:17.309 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:17.309 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:17.309 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:38:17.316 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:17.316 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:17.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:17.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:17.319 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:38:17.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:38:17.319 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:38:17.319 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:38:17.319 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:38:17.319 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:38:17.319 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=531 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=531 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=531 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=531 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:17.319 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=532 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:38:22.318 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:38:22.318 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:38:22.318 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:38:22.318 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:38:22.318 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:38:22.318 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:38:22.321 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:38:22.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:38:22.321 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:22.321 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:38:22.321 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:38:22.322 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:38:22.322 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:38:22.322 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:38:22.322 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:22.323 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:38:22.323 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:38:22.323 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:38:22.323 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:38:22.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:22.323 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:38:22.323 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:38:22.324 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:38:22.324 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:22.324 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:38:22.324 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:38:22.324 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:38:22.324 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:38:22.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:22.325 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:38:22.325 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:38:22.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:38:22.325 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:38:22.325 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:38:22.325 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:38:22.325 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:38:22.325 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:38:22.325 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:38:22.327 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:38:22.327 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:38:22.327 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:38:22.332 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:38:22.798 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:38:22.843 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:38:22.844 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:38:22.845 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:22.846 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:38:22.855 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:22.855 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:22.856 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:22.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:22.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:22.863 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:22.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:22.898 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:22.899 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:22.899 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:22.899 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:38:22.899 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:38:22.937 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:22.937 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:22.937 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:22.938 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:23.266 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:38:23.329 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:23.330 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:23.330 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:23.330 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:23.731 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:38:24.195 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:38:24.330 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:24.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:24.331 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:24.331 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:24.662 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:38:25.130 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:38:25.331 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:25.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:25.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:25.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:25.597 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:38:26.067 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:38:26.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:26.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:26.333 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:26.333 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:26.539 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:38:27.004 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:38:27.333 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:38:27.333 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:38:27.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:38:27.334 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:38:27.469 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:38:27.941 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:38:28.407 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:38:28.876 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:38:29.349 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:38:29.817 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:38:30.287 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:38:30.758 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:38:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:38:31.700 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:38:32.171 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:38:32.642 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:38:33.110 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:38:33.582 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:38:34.049 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:38:34.520 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:38:34.991 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:38:35.461 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:38:35.930 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:38:36.399 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:38:36.867 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:38:37.335 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:38:37.805 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:38:38.275 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:38:38.743 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:38:39.212 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:38:39.685 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:38:40.155 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:38:40.626 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:38:41.097 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:38:41.563 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:38:42.033 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:38:42.498 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:38:42.966 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:38:43.437 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:38:43.903 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:38:44.371 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:38:44.835 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:38:45.303 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:38:45.771 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:38:46.240 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:38:46.709 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:38:47.180 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:38:47.650 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:38:48.121 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:38:48.592 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:38:49.063 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:38:49.532 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:38:50.002 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:38:50.472 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:38:50.942 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:38:51.410 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:38:51.878 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:38:52.346 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:38:52.815 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:38:53.281 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:38:53.752 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:38:54.219 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:38:54.689 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:38:55.159 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:38:55.626 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:38:55.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:55.896 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:55.902 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:55.902 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:55.912 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:55.912 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:55.912 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:55.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:38:55.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:38:55.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:38:55.918 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:38:55.919 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:55.919 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:38:55.919 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:38:55.919 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:38:55.919 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:38:55.952 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:38:55.952 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:38:55.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:55.952 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:38:56.092 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:38:56.558 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 03:38:57.023 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 03:38:57.489 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 03:38:57.953 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 03:38:58.419 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 03:38:58.884 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 03:38:59.349 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 03:38:59.814 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 03:39:00.280 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 03:39:00.748 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 03:39:01.217 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 03:39:01.683 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 03:39:02.152 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 03:39:02.618 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 03:39:03.089 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 03:39:03.555 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 03:39:04.018 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 03:39:04.487 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 03:39:04.957 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 03:39:05.428 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 03:39:05.893 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 03:39:06.359 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 03:39:06.823 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 03:39:07.288 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 03:39:07.759 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 03:39:08.226 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 03:39:08.691 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 03:39:09.157 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 03:39:09.624 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 03:39:10.090 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 03:39:10.558 [DEBUG] clck_gen.py:113 IND CLOCK 10506
2026-03-01 03:39:11.026 [DEBUG] clck_gen.py:113 IND CLOCK 10608
2026-03-01 03:39:11.489 [DEBUG] clck_gen.py:113 IND CLOCK 10710
2026-03-01 03:39:11.960 [DEBUG] clck_gen.py:113 IND CLOCK 10812
2026-03-01 03:39:12.499 [DEBUG] clck_gen.py:113 IND CLOCK 10914
2026-03-01 03:39:12.967 [DEBUG] clck_gen.py:113 IND CLOCK 11016
2026-03-01 03:39:13.431 [DEBUG] clck_gen.py:113 IND CLOCK 11118
2026-03-01 03:39:13.896 [DEBUG] clck_gen.py:113 IND CLOCK 11220
2026-03-01 03:39:14.361 [DEBUG] clck_gen.py:113 IND CLOCK 11322
2026-03-01 03:39:14.829 [DEBUG] clck_gen.py:113 IND CLOCK 11424
2026-03-01 03:39:15.295 [DEBUG] clck_gen.py:113 IND CLOCK 11526
2026-03-01 03:39:15.761 [DEBUG] clck_gen.py:113 IND CLOCK 11628
2026-03-01 03:39:16.234 [DEBUG] clck_gen.py:113 IND CLOCK 11730
2026-03-01 03:39:16.733 [DEBUG] clck_gen.py:113 IND CLOCK 11832
2026-03-01 03:39:17.201 [DEBUG] clck_gen.py:113 IND CLOCK 11934
2026-03-01 03:39:17.671 [DEBUG] clck_gen.py:113 IND CLOCK 12036
2026-03-01 03:39:18.139 [DEBUG] clck_gen.py:113 IND CLOCK 12138
2026-03-01 03:39:18.612 [DEBUG] clck_gen.py:113 IND CLOCK 12240
2026-03-01 03:39:19.083 [DEBUG] clck_gen.py:113 IND CLOCK 12342
2026-03-01 03:39:19.554 [DEBUG] clck_gen.py:113 IND CLOCK 12444
2026-03-01 03:39:20.021 [DEBUG] clck_gen.py:113 IND CLOCK 12546
2026-03-01 03:39:20.486 [DEBUG] clck_gen.py:113 IND CLOCK 12648
2026-03-01 03:39:20.951 [DEBUG] clck_gen.py:113 IND CLOCK 12750
2026-03-01 03:39:21.416 [DEBUG] clck_gen.py:113 IND CLOCK 12852
2026-03-01 03:39:21.882 [DEBUG] clck_gen.py:113 IND CLOCK 12954
2026-03-01 03:39:22.348 [DEBUG] clck_gen.py:113 IND CLOCK 13056
2026-03-01 03:39:22.814 [DEBUG] clck_gen.py:113 IND CLOCK 13158
2026-03-01 03:39:23.279 [DEBUG] clck_gen.py:113 IND CLOCK 13260
2026-03-01 03:39:23.744 [DEBUG] clck_gen.py:113 IND CLOCK 13362
2026-03-01 03:39:24.208 [DEBUG] clck_gen.py:113 IND CLOCK 13464
2026-03-01 03:39:24.674 [DEBUG] clck_gen.py:113 IND CLOCK 13566
2026-03-01 03:39:25.139 [DEBUG] clck_gen.py:113 IND CLOCK 13668
2026-03-01 03:39:25.606 [DEBUG] clck_gen.py:113 IND CLOCK 13770
2026-03-01 03:39:26.075 [DEBUG] clck_gen.py:113 IND CLOCK 13872
2026-03-01 03:39:26.539 [DEBUG] clck_gen.py:113 IND CLOCK 13974
2026-03-01 03:39:27.004 [DEBUG] clck_gen.py:113 IND CLOCK 14076
2026-03-01 03:39:27.470 [DEBUG] clck_gen.py:113 IND CLOCK 14178
2026-03-01 03:39:27.935 [DEBUG] clck_gen.py:113 IND CLOCK 14280
2026-03-01 03:39:28.407 [DEBUG] clck_gen.py:113 IND CLOCK 14382
2026-03-01 03:39:28.874 [DEBUG] clck_gen.py:113 IND CLOCK 14484
2026-03-01 03:39:29.345 [DEBUG] clck_gen.py:113 IND CLOCK 14586
2026-03-01 03:39:29.670 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:39:29.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:39:29.684 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:39:29.684 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:39:29.684 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:39:29.701 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:39:29.701 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:39:29.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:39:29.708 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:39:29.708 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:39:29.708 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:39:29.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:39:29.710 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:39:29.710 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:39:29.710 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:39:29.710 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:39:29.710 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:39:29.715 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:39:29.715 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:39:29.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:39:29.715 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:39:29.814 [DEBUG] clck_gen.py:113 IND CLOCK 14688
2026-03-01 03:39:30.286 [DEBUG] clck_gen.py:113 IND CLOCK 14790
2026-03-01 03:39:30.757 [DEBUG] clck_gen.py:113 IND CLOCK 14892
2026-03-01 03:39:31.229 [DEBUG] clck_gen.py:113 IND CLOCK 14994
2026-03-01 03:39:31.700 [DEBUG] clck_gen.py:113 IND CLOCK 15096
2026-03-01 03:39:32.171 [DEBUG] clck_gen.py:113 IND CLOCK 15198
2026-03-01 03:39:32.638 [DEBUG] clck_gen.py:113 IND CLOCK 15300
2026-03-01 03:39:33.107 [DEBUG] clck_gen.py:113 IND CLOCK 15402
2026-03-01 03:39:33.579 [DEBUG] clck_gen.py:113 IND CLOCK 15504
2026-03-01 03:39:34.050 [DEBUG] clck_gen.py:113 IND CLOCK 15606
2026-03-01 03:39:34.521 [DEBUG] clck_gen.py:113 IND CLOCK 15708
2026-03-01 03:39:34.992 [DEBUG] clck_gen.py:113 IND CLOCK 15810
2026-03-01 03:39:35.461 [DEBUG] clck_gen.py:113 IND CLOCK 15912
2026-03-01 03:39:35.924 [DEBUG] clck_gen.py:113 IND CLOCK 16014
2026-03-01 03:39:36.388 [DEBUG] clck_gen.py:113 IND CLOCK 16116
2026-03-01 03:39:36.851 [DEBUG] clck_gen.py:113 IND CLOCK 16218
2026-03-01 03:39:37.316 [DEBUG] clck_gen.py:113 IND CLOCK 16320
2026-03-01 03:39:37.780 [DEBUG] clck_gen.py:113 IND CLOCK 16422
2026-03-01 03:39:38.242 [DEBUG] clck_gen.py:113 IND CLOCK 16524
2026-03-01 03:39:38.705 [DEBUG] clck_gen.py:113 IND CLOCK 16626
2026-03-01 03:39:39.169 [DEBUG] clck_gen.py:113 IND CLOCK 16728
2026-03-01 03:39:39.632 [DEBUG] clck_gen.py:113 IND CLOCK 16830
2026-03-01 03:39:40.094 [DEBUG] clck_gen.py:113 IND CLOCK 16932
2026-03-01 03:39:40.557 [DEBUG] clck_gen.py:113 IND CLOCK 17034
2026-03-01 03:39:41.019 [DEBUG] clck_gen.py:113 IND CLOCK 17136
2026-03-01 03:39:41.482 [DEBUG] clck_gen.py:113 IND CLOCK 17238
2026-03-01 03:39:41.944 [DEBUG] clck_gen.py:113 IND CLOCK 17340
2026-03-01 03:39:42.406 [DEBUG] clck_gen.py:113 IND CLOCK 17442
2026-03-01 03:39:42.871 [DEBUG] clck_gen.py:113 IND CLOCK 17544
2026-03-01 03:39:43.335 [DEBUG] clck_gen.py:113 IND CLOCK 17646
2026-03-01 03:39:43.799 [DEBUG] clck_gen.py:113 IND CLOCK 17748
2026-03-01 03:39:44.261 [DEBUG] clck_gen.py:113 IND CLOCK 17850
2026-03-01 03:39:44.724 [DEBUG] clck_gen.py:113 IND CLOCK 17952
2026-03-01 03:39:45.188 [DEBUG] clck_gen.py:113 IND CLOCK 18054
2026-03-01 03:39:45.651 [DEBUG] clck_gen.py:113 IND CLOCK 18156
2026-03-01 03:39:46.115 [DEBUG] clck_gen.py:113 IND CLOCK 18258
2026-03-01 03:39:46.579 [DEBUG] clck_gen.py:113 IND CLOCK 18360
2026-03-01 03:39:47.041 [DEBUG] clck_gen.py:113 IND CLOCK 18462
2026-03-01 03:39:47.505 [DEBUG] clck_gen.py:113 IND CLOCK 18564
2026-03-01 03:39:47.968 [DEBUG] clck_gen.py:113 IND CLOCK 18666
2026-03-01 03:39:48.431 [DEBUG] clck_gen.py:113 IND CLOCK 18768
2026-03-01 03:39:48.894 [DEBUG] clck_gen.py:113 IND CLOCK 18870
2026-03-01 03:39:49.358 [DEBUG] clck_gen.py:113 IND CLOCK 18972
2026-03-01 03:39:49.821 [DEBUG] clck_gen.py:113 IND CLOCK 19074
2026-03-01 03:39:50.290 [DEBUG] clck_gen.py:113 IND CLOCK 19176
2026-03-01 03:39:50.755 [DEBUG] clck_gen.py:113 IND CLOCK 19278
2026-03-01 03:39:51.223 [DEBUG] clck_gen.py:113 IND CLOCK 19380
2026-03-01 03:39:51.687 [DEBUG] clck_gen.py:113 IND CLOCK 19482
2026-03-01 03:39:52.151 [DEBUG] clck_gen.py:113 IND CLOCK 19584
2026-03-01 03:39:52.616 [DEBUG] clck_gen.py:113 IND CLOCK 19686
2026-03-01 03:39:53.087 [DEBUG] clck_gen.py:113 IND CLOCK 19788
2026-03-01 03:39:53.553 [DEBUG] clck_gen.py:113 IND CLOCK 19890
2026-03-01 03:39:54.017 [DEBUG] clck_gen.py:113 IND CLOCK 19992
2026-03-01 03:39:54.485 [DEBUG] clck_gen.py:113 IND CLOCK 20094
2026-03-01 03:39:54.949 [DEBUG] clck_gen.py:113 IND CLOCK 20196
2026-03-01 03:39:55.417 [DEBUG] clck_gen.py:113 IND CLOCK 20298
2026-03-01 03:39:55.887 [DEBUG] clck_gen.py:113 IND CLOCK 20400
2026-03-01 03:39:56.354 [DEBUG] clck_gen.py:113 IND CLOCK 20502
2026-03-01 03:39:56.823 [DEBUG] clck_gen.py:113 IND CLOCK 20604
2026-03-01 03:39:57.292 [DEBUG] clck_gen.py:113 IND CLOCK 20706
2026-03-01 03:39:57.759 [DEBUG] clck_gen.py:113 IND CLOCK 20808
2026-03-01 03:39:58.227 [DEBUG] clck_gen.py:113 IND CLOCK 20910
2026-03-01 03:39:58.693 [DEBUG] clck_gen.py:113 IND CLOCK 21012
2026-03-01 03:39:59.162 [DEBUG] clck_gen.py:113 IND CLOCK 21114
2026-03-01 03:39:59.628 [DEBUG] clck_gen.py:113 IND CLOCK 21216
2026-03-01 03:40:00.092 [DEBUG] clck_gen.py:113 IND CLOCK 21318
2026-03-01 03:40:00.558 [DEBUG] clck_gen.py:113 IND CLOCK 21420
2026-03-01 03:40:01.022 [DEBUG] clck_gen.py:113 IND CLOCK 21522
2026-03-01 03:40:01.492 [DEBUG] clck_gen.py:113 IND CLOCK 21624
2026-03-01 03:40:01.960 [DEBUG] clck_gen.py:113 IND CLOCK 21726
2026-03-01 03:40:02.424 [DEBUG] clck_gen.py:113 IND CLOCK 21828
2026-03-01 03:40:02.893 [DEBUG] clck_gen.py:113 IND CLOCK 21930
2026-03-01 03:40:03.363 [DEBUG] clck_gen.py:113 IND CLOCK 22032
2026-03-01 03:40:03.831 [DEBUG] clck_gen.py:113 IND CLOCK 22134
2026-03-01 03:40:04.297 [DEBUG] clck_gen.py:113 IND CLOCK 22236
2026-03-01 03:40:04.590 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:04.592 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:04.606 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:04.606 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:04.619 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:04.619 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:04.619 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:04.624 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:04.625 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:04.625 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:04.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:04.627 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:04.627 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:04.627 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:04.627 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:40:04.627 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:40:04.666 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:40:04.666 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:40:04.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:04.666 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:04.765 [DEBUG] clck_gen.py:113 IND CLOCK 22338
2026-03-01 03:40:05.232 [DEBUG] clck_gen.py:113 IND CLOCK 22440
2026-03-01 03:40:05.698 [DEBUG] clck_gen.py:113 IND CLOCK 22542
2026-03-01 03:40:06.167 [DEBUG] clck_gen.py:113 IND CLOCK 22644
2026-03-01 03:40:06.635 [DEBUG] clck_gen.py:113 IND CLOCK 22746
2026-03-01 03:40:07.105 [DEBUG] clck_gen.py:113 IND CLOCK 22848
2026-03-01 03:40:07.571 [DEBUG] clck_gen.py:113 IND CLOCK 22950
2026-03-01 03:40:08.035 [DEBUG] clck_gen.py:113 IND CLOCK 23052
2026-03-01 03:40:08.500 [DEBUG] clck_gen.py:113 IND CLOCK 23154
2026-03-01 03:40:08.964 [DEBUG] clck_gen.py:113 IND CLOCK 23256
2026-03-01 03:40:09.085 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:09.085 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:09.085 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:40:09.090 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:09.090 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:09.090 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:09.090 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:09.091 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:09.091 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:09.091 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:40:09.091 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:40:09.091 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:40:09.091 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:09.091 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:14.092 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:40:14.092 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:40:14.093 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:14.093 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:14.093 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:14.093 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:14.099 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:14.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:40:14.100 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:14.100 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:40:14.100 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:40:14.101 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:40:14.101 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:40:14.101 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:40:14.101 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:14.101 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:14.101 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:40:14.101 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:40:14.101 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:40:14.101 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:14.102 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:40:14.102 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:40:14.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:40:14.102 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:14.102 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:14.102 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:40:14.102 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:40:14.102 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:40:14.102 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:14.103 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:40:14.104 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:40:14.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:40:14.104 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:14.104 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:14.104 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:40:14.104 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:40:14.104 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:40:14.104 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:40:14.106 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:40:14.106 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:40:14.106 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.106 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:14.107 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:14.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.108 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:14.108 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:14.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.108 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:14.108 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:14.108 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:40:14.108 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:40:14.108 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:40:19.118 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:40:19.118 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:40:19.118 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:19.119 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:19.119 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:19.119 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:19.126 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:19.127 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:40:19.127 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:19.127 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:40:19.127 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:40:19.130 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:40:19.130 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:40:19.131 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:40:19.131 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:19.131 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:19.131 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:40:19.132 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:40:19.132 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:40:19.132 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:19.134 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:40:19.134 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:40:19.134 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:40:19.135 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:19.135 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:19.135 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:40:19.135 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:40:19.135 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:40:19.136 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:19.137 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:40:19.137 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:40:19.137 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:40:19.137 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:19.137 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:19.138 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:40:19.138 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:40:19.138 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:40:19.138 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:19.141 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:40:19.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:40:19.141 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:40:19.141 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:40:19.141 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:40:19.141 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:40:19.142 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:40:19.142 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:40:19.142 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.142 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.143 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:19.147 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:40:19.611 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:40:19.661 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:40:19.663 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:19.663 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:40:19.665 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:40:19.682 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:19.682 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:19.683 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:19.697 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:19.697 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:19.698 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:19.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:19.701 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:19.701 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:19.701 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:19.701 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:40:19.701 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:40:19.747 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:19.747 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:19.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:19.747 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:20.075 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:40:20.144 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:20.144 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:20.145 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:20.145 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:20.539 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:40:21.004 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:40:21.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:21.122 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:21.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:21.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:21.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:21.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:21.129 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:21.135 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:21.135 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:21.135 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:21.135 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:21.137 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:21.137 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:21.137 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:21.137 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:40:21.137 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:40:21.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:21.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:21.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:21.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:21.181 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:40:21.181 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:40:21.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:21.182 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:21.467 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:40:21.933 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:40:22.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:22.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:22.146 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:22.146 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:22.396 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:40:22.859 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:40:23.145 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:23.145 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:23.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:23.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:23.324 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:40:23.387 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:23.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:23.389 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:23.389 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:23.389 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:40:23.395 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:23.395 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:23.395 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:23.400 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:23.400 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:23.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:23.401 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:23.402 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:23.402 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:23.402 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:23.403 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:40:23.403 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:40:23.410 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:23.410 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:23.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:23.410 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:23.789 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:40:24.146 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:24.146 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:24.147 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:24.147 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:24.253 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:40:24.718 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:40:25.183 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:40:25.648 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:40:26.114 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:40:26.580 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:40:26.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:26.729 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:26.731 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:26.731 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:26.737 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:26.737 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:26.737 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:26.742 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:26.742 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:26.742 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:26.743 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:26.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:26.744 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:26.744 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:26.744 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:40:26.744 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:40:26.757 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:40:26.757 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:40:26.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:26.757 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:27.045 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:40:27.511 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:40:27.974 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:40:28.054 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:28.054 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:28.054 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:40:28.055 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:28.055 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:28.055 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:28.055 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:28.056 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:28.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:28.056 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:40:28.056 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:40:28.056 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:40:28.056 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:28.057 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:33.058 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:40:33.058 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:40:33.059 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:33.059 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:33.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:33.059 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:33.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:40:33.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:40:33.063 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:33.063 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:40:33.063 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:40:33.064 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:40:33.064 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:40:33.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:40:33.065 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:33.065 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:40:33.065 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:40:33.065 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:40:33.065 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:40:33.065 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:33.066 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:40:33.066 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:40:33.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:40:33.066 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:33.066 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:40:33.066 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:40:33.066 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:40:33.066 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:40:33.066 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:33.067 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:40:33.067 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:40:33.067 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:40:33.067 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:40:33.067 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:40:33.067 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:40:33.068 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:40:33.068 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:40:33.068 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:40:33.070 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:40:33.070 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:40:33.070 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.070 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.071 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:40:33.075 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:40:33.541 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:40:33.584 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:40:33.585 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:40:33.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:33.585 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:40:33.592 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:33.592 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:33.592 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:33.598 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:33.598 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:33.598 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:33.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:33.601 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:33.601 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:33.601 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:33.601 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:40:33.601 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:40:33.629 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:33.629 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:33.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:33.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:34.004 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:40:34.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:34.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:34.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:34.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:34.466 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:40:34.930 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:40:35.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:35.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:35.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:35.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:35.392 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:40:35.858 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:40:36.073 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:36.073 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:36.073 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:36.073 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:36.324 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:40:36.788 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:40:37.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:37.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:37.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:37.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:37.252 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:40:37.715 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:40:38.074 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:40:38.074 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:40:38.074 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:40:38.074 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:40:38.178 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:40:38.641 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:40:39.106 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:40:39.570 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:40:40.034 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:40:40.500 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:40:40.966 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:40:41.431 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:40:41.897 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:40:42.362 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:40:42.828 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:40:43.292 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:40:43.757 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:40:44.222 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:40:44.687 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:40:45.152 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:40:45.615 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:40:46.078 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:40:46.541 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:40:47.004 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:40:47.466 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:40:47.932 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:40:48.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:48.214 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:48.215 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:48.215 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:48.222 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:48.222 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:48.222 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:48.227 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:40:48.227 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:40:48.228 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:40:48.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:40:48.230 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:48.230 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:40:48.230 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:40:48.230 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:40:48.230 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:40:48.255 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:40:48.255 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:40:48.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:48.255 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:40:48.396 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:40:48.859 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:40:49.321 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:40:49.786 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:40:50.250 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:40:50.714 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:40:51.180 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:40:51.645 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:40:52.107 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:40:52.571 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:40:53.034 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:40:53.496 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:40:53.961 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:40:54.426 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:40:54.891 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:40:55.355 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:40:55.819 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:40:56.283 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:40:56.747 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:40:57.210 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:40:57.675 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:40:58.138 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:40:58.602 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:40:59.065 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:40:59.528 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:40:59.990 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:41:00.453 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:41:00.916 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:41:01.379 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:41:01.841 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:41:02.305 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:41:02.769 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:41:03.103 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:03.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:03.105 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:03.105 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:03.105 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:41:03.112 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:03.112 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:03.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:03.117 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:03.117 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:03.118 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:03.118 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:03.119 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:03.119 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:03.119 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:03.119 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:41:03.120 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:41:03.135 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:03.136 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:03.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:03.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:03.231 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:41:03.693 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:41:04.156 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:41:04.619 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:41:05.082 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:41:05.547 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:41:06.009 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:41:06.472 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:41:06.934 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 03:41:07.397 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 03:41:07.861 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 03:41:08.326 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 03:41:08.792 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 03:41:09.256 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 03:41:09.718 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 03:41:10.181 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 03:41:10.646 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 03:41:11.112 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 03:41:11.577 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 03:41:12.043 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 03:41:12.509 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 03:41:12.974 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 03:41:13.439 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 03:41:13.903 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 03:41:14.369 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 03:41:14.832 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 03:41:15.296 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 03:41:15.761 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 03:41:16.223 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 03:41:16.688 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 03:41:17.121 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:17.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:17.122 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:17.122 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:17.129 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:17.129 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:17.130 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:17.136 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:17.136 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:17.136 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:17.137 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:17.138 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:17.138 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:17.138 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:17.138 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:41:17.138 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:41:17.151 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 03:41:17.152 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:41:17.152 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:41:17.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:17.152 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:17.615 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 03:41:18.079 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 03:41:18.542 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 03:41:19.006 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 03:41:19.471 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 03:41:19.935 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 03:41:20.324 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:20.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:20.324 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:41:20.326 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:41:20.326 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:41:20.326 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:41:20.326 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:41:20.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:41:20.327 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:41:20.327 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:41:20.328 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:41:20.328 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:41:20.328 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:41:20.328 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:41:20.328 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10389 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:41:20.328 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10389 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:41:20.328 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10389 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:41:20.328 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10389 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:41:20.328 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10389 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:41:20.328 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10389 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:41:25.337 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:41:25.337 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:41:25.337 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:41:25.337 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:41:25.337 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:41:25.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:41:25.340 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:41:25.341 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:41:25.341 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:41:25.341 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:41:25.341 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:41:25.342 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:41:25.342 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:41:25.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:41:25.342 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:41:25.342 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:41:25.342 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:41:25.342 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:41:25.342 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:41:25.342 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:41:25.344 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:41:25.344 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:41:25.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:41:25.344 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:41:25.344 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:41:25.344 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:41:25.344 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:41:25.344 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:41:25.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:41:25.346 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:41:25.346 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:41:25.346 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:41:25.346 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:41:25.346 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:41:25.346 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:41:25.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:41:25.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:41:25.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.350 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:41:25.350 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:41:25.350 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.350 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:41:25.351 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:41:25.355 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:41:25.818 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:41:25.864 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:41:25.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:25.865 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:41:25.866 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:41:25.874 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:25.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:25.875 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:25.881 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:25.881 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:25.881 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:25.882 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:25.884 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:25.884 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:25.884 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:25.884 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:41:25.884 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:41:25.907 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:25.907 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:25.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:25.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:26.281 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:41:26.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:41:26.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:41:26.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:41:26.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:41:26.744 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:41:27.207 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:41:27.354 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:41:27.354 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:41:27.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:41:27.354 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:41:27.670 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:41:28.133 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:41:28.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:41:28.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:41:28.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:41:28.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:41:28.598 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:41:29.061 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:41:29.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:41:29.355 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:41:29.355 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:41:29.355 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:41:29.524 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:41:29.988 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:41:30.355 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:41:30.356 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:41:30.356 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:41:30.356 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:41:30.452 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:41:30.915 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:41:31.378 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:41:31.841 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:41:32.304 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:41:32.767 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:41:33.230 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:41:33.692 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:41:34.155 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:41:34.618 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:41:35.080 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:41:35.544 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:41:35.734 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:35.735 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:35.736 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:35.736 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:35.744 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:35.744 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:35.744 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:35.751 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:35.751 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:35.751 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:35.752 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:35.753 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:35.753 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:35.753 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:35.753 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:41:35.753 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:41:35.775 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:41:35.775 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:41:35.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:35.775 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:36.007 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:41:36.471 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:41:36.936 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:41:37.399 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:41:37.861 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:41:38.323 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:41:38.785 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:41:39.248 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:41:39.712 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:41:40.177 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:41:40.640 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:41:41.104 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:41:41.567 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:41:42.030 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:41:42.494 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:41:42.957 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:41:43.420 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:41:43.884 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:41:44.348 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:41:44.812 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:41:45.275 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:41:45.738 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:41:45.888 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:45.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:45.890 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:45.890 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:45.890 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:41:45.897 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:45.897 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:45.897 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:45.905 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:45.905 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:45.905 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:45.906 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:45.908 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:45.909 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:45.909 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:45.909 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:41:45.909 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:41:45.916 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:45.916 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:45.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:45.916 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:46.201 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:41:46.665 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:41:47.128 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:41:47.594 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:41:48.057 [DEBUG] clck_gen.py:113 IND CLOCK 4998
2026-03-01 03:41:48.520 [DEBUG] clck_gen.py:113 IND CLOCK 5100
2026-03-01 03:41:48.983 [DEBUG] clck_gen.py:113 IND CLOCK 5202
2026-03-01 03:41:49.446 [DEBUG] clck_gen.py:113 IND CLOCK 5304
2026-03-01 03:41:49.908 [DEBUG] clck_gen.py:113 IND CLOCK 5406
2026-03-01 03:41:50.371 [DEBUG] clck_gen.py:113 IND CLOCK 5508
2026-03-01 03:41:50.833 [DEBUG] clck_gen.py:113 IND CLOCK 5610
2026-03-01 03:41:51.296 [DEBUG] clck_gen.py:113 IND CLOCK 5712
2026-03-01 03:41:51.758 [DEBUG] clck_gen.py:113 IND CLOCK 5814
2026-03-01 03:41:52.221 [DEBUG] clck_gen.py:113 IND CLOCK 5916
2026-03-01 03:41:52.683 [DEBUG] clck_gen.py:113 IND CLOCK 6018
2026-03-01 03:41:52.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:52.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:52.715 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:52.715 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:52.722 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:52.722 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:52.723 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:52.729 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:41:52.729 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:41:52.729 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:41:52.730 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:41:52.731 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:52.731 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:41:52.731 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:41:52.731 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:41:52.731 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:41:52.769 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:41:52.769 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:41:52.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:52.769 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:41:53.145 [DEBUG] clck_gen.py:113 IND CLOCK 6120
2026-03-01 03:41:53.607 [DEBUG] clck_gen.py:113 IND CLOCK 6222
2026-03-01 03:41:54.069 [DEBUG] clck_gen.py:113 IND CLOCK 6324
2026-03-01 03:41:54.532 [DEBUG] clck_gen.py:113 IND CLOCK 6426
2026-03-01 03:41:54.998 [DEBUG] clck_gen.py:113 IND CLOCK 6528
2026-03-01 03:41:55.464 [DEBUG] clck_gen.py:113 IND CLOCK 6630
2026-03-01 03:41:55.929 [DEBUG] clck_gen.py:113 IND CLOCK 6732
2026-03-01 03:41:56.393 [DEBUG] clck_gen.py:113 IND CLOCK 6834
2026-03-01 03:41:56.858 [DEBUG] clck_gen.py:113 IND CLOCK 6936
2026-03-01 03:41:57.323 [DEBUG] clck_gen.py:113 IND CLOCK 7038
2026-03-01 03:41:57.788 [DEBUG] clck_gen.py:113 IND CLOCK 7140
2026-03-01 03:41:58.251 [DEBUG] clck_gen.py:113 IND CLOCK 7242
2026-03-01 03:41:58.714 [DEBUG] clck_gen.py:113 IND CLOCK 7344
2026-03-01 03:41:59.178 [DEBUG] clck_gen.py:113 IND CLOCK 7446
2026-03-01 03:41:59.641 [DEBUG] clck_gen.py:113 IND CLOCK 7548
2026-03-01 03:42:00.106 [DEBUG] clck_gen.py:113 IND CLOCK 7650
2026-03-01 03:42:00.569 [DEBUG] clck_gen.py:113 IND CLOCK 7752
2026-03-01 03:42:01.034 [DEBUG] clck_gen.py:113 IND CLOCK 7854
2026-03-01 03:42:01.499 [DEBUG] clck_gen.py:113 IND CLOCK 7956
2026-03-01 03:42:01.961 [DEBUG] clck_gen.py:113 IND CLOCK 8058
2026-03-01 03:42:02.423 [DEBUG] clck_gen.py:113 IND CLOCK 8160
2026-03-01 03:42:02.885 [DEBUG] clck_gen.py:113 IND CLOCK 8262
2026-03-01 03:42:03.348 [DEBUG] clck_gen.py:113 IND CLOCK 8364
2026-03-01 03:42:03.810 [DEBUG] clck_gen.py:113 IND CLOCK 8466
2026-03-01 03:42:04.272 [DEBUG] clck_gen.py:113 IND CLOCK 8568
2026-03-01 03:42:04.735 [DEBUG] clck_gen.py:113 IND CLOCK 8670
2026-03-01 03:42:05.198 [DEBUG] clck_gen.py:113 IND CLOCK 8772
2026-03-01 03:42:05.661 [DEBUG] clck_gen.py:113 IND CLOCK 8874
2026-03-01 03:42:06.128 [DEBUG] clck_gen.py:113 IND CLOCK 8976
2026-03-01 03:42:06.594 [DEBUG] clck_gen.py:113 IND CLOCK 9078
2026-03-01 03:42:07.058 [DEBUG] clck_gen.py:113 IND CLOCK 9180
2026-03-01 03:42:07.523 [DEBUG] clck_gen.py:113 IND CLOCK 9282
2026-03-01 03:42:07.987 [DEBUG] clck_gen.py:113 IND CLOCK 9384
2026-03-01 03:42:08.451 [DEBUG] clck_gen.py:113 IND CLOCK 9486
2026-03-01 03:42:08.916 [DEBUG] clck_gen.py:113 IND CLOCK 9588
2026-03-01 03:42:09.378 [DEBUG] clck_gen.py:113 IND CLOCK 9690
2026-03-01 03:42:09.841 [DEBUG] clck_gen.py:113 IND CLOCK 9792
2026-03-01 03:42:10.303 [DEBUG] clck_gen.py:113 IND CLOCK 9894
2026-03-01 03:42:10.765 [DEBUG] clck_gen.py:113 IND CLOCK 9996
2026-03-01 03:42:11.228 [DEBUG] clck_gen.py:113 IND CLOCK 10098
2026-03-01 03:42:11.691 [DEBUG] clck_gen.py:113 IND CLOCK 10200
2026-03-01 03:42:12.155 [DEBUG] clck_gen.py:113 IND CLOCK 10302
2026-03-01 03:42:12.620 [DEBUG] clck_gen.py:113 IND CLOCK 10404
2026-03-01 03:42:12.724 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:12.724 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:12.724 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:42:12.727 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:12.728 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:12.728 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:12.728 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:12.731 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:12.731 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:12.731 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:12.731 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:12.731 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:42:12.731 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:42:12.731 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:12.731 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=10430 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:42:17.740 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:42:17.740 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:42:17.740 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:17.740 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:17.740 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:17.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:17.752 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:17.753 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:42:17.753 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:17.754 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:42:17.754 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:42:17.756 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:42:17.756 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:42:17.756 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:42:17.756 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:17.757 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:17.757 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:42:17.757 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:42:17.757 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:42:17.757 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:17.758 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:42:17.758 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:42:17.758 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:42:17.759 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:17.759 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:17.759 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:42:17.759 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:42:17.759 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:42:17.759 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:17.760 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:42:17.760 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:42:17.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:42:17.760 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:17.760 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:17.760 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:42:17.760 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:42:17.760 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:42:17.761 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:17.763 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:42:17.763 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:42:17.763 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:42:17.763 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:42:17.764 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:42:17.764 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:42:17.764 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.764 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:17.765 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:17.769 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:42:18.234 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:42:18.286 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:42:18.286 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:42:18.287 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:42:18.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:18.297 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:18.297 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:18.297 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:18.311 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:18.311 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:18.312 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:18.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:18.318 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:18.318 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:18.318 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:18.318 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:18.318 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:18.325 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:18.325 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:18.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:18.325 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:18.630 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:18.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:18.634 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:18.634 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:18.647 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:18.647 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:18.647 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:18.652 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:18.652 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:18.653 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:18.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:18.654 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:18.654 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:18.654 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:18.654 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:18.654 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:18.703 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:42:18.704 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:42:18.705 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:42:18.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:18.705 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:18.767 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:18.767 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:18.767 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:18.768 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:19.175 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:42:19.183 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:19.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:19.188 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:19.188 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:19.188 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:42:19.207 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:19.207 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:19.207 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:19.212 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:19.213 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:19.213 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:19.213 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:19.214 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:19.214 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:19.214 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:19.214 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:19.214 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:19.263 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:19.263 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:19.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:19.263 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:19.646 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:42:19.768 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:19.768 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:19.769 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:19.769 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:20.033 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:20.035 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:20.039 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:20.039 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:20.053 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:20.053 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:20.053 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:20.059 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:20.059 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:20.059 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:20.060 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:20.061 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:20.061 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:20.061 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:20.061 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:20.061 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:20.112 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:42:20.112 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:42:20.112 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:20.113 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:20.117 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:42:20.587 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:42:20.769 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:20.769 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:20.770 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:20.770 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:21.060 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:42:21.531 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:42:21.770 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:21.771 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:21.771 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:21.771 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:22.003 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:42:22.477 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:42:22.772 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:22.772 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:22.772 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:22.772 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:22.949 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:42:23.423 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:42:23.890 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:42:24.143 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:24.144 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:24.148 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:24.148 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:24.148 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:42:24.154 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:24.154 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:24.154 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:24.154 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:24.155 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:24.155 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:24.155 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:24.155 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:24.155 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:42:24.155 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:42:24.155 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:42:29.166 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:42:29.166 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:42:29.167 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:29.167 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:29.167 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:29.167 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:29.173 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:29.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:42:29.174 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:29.174 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:42:29.174 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:42:29.175 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:42:29.175 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:42:29.175 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:42:29.175 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:29.175 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:29.175 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:42:29.176 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:42:29.176 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:42:29.176 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:29.177 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:42:29.177 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:42:29.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:42:29.177 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:29.177 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:29.177 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:42:29.177 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:42:29.177 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:42:29.177 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:29.178 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:42:29.179 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:42:29.179 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:42:29.179 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:29.179 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:29.179 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:42:29.179 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:42:29.179 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:42:29.179 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:42:29.181 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:42:29.181 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:42:29.181 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.181 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:29.182 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:29.186 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:42:29.658 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:42:29.694 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:42:29.695 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:42:29.695 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:42:29.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:29.702 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:29.702 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:29.703 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:29.713 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:29.713 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:29.714 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:29.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:29.719 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:29.719 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:29.719 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:29.719 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:29.719 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:29.749 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:29.750 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:29.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:29.750 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:30.129 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:42:30.184 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:30.184 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:30.185 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:30.185 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:30.602 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:42:31.074 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:42:31.186 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:31.186 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:31.186 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:31.186 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:31.548 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:42:32.020 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:42:32.187 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:32.187 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:32.187 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:32.187 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:32.494 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:42:32.958 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:32.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:32.964 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:32.964 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:32.966 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:42:32.982 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:32.982 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:32.982 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:32.988 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:32.988 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:32.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:32.989 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:32.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:32.990 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:32.990 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:32.990 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:32.990 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:33.010 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:42:33.010 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:42:33.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:33.010 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:33.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:33.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:33.188 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:33.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:33.433 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:42:33.904 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:42:34.190 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:34.190 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:34.190 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:34.190 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:34.375 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:42:34.849 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:42:35.321 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:42:35.793 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:42:36.266 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:42:36.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:36.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:36.353 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:36.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:36.354 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:42:36.365 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:36.365 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:36.365 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:36.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:36.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:36.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:36.370 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:36.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:36.371 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:36.371 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:36.372 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:36.372 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:36.400 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:36.401 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:36.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:36.401 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:36.737 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:42:37.210 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:42:37.683 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:42:38.153 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:42:38.624 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:42:39.095 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:42:39.568 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:42:39.955 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:39.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:39.961 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:39.961 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:39.981 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:39.981 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:39.981 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:39.986 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:39.987 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:39.987 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:39.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:39.988 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:39.988 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:39.988 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:39.988 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:39.988 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:40.035 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:42:40.035 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:42:40.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:40.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:40.040 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:42:40.513 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:42:40.985 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:42:41.459 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:42:41.931 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:42:42.403 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:42:42.875 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:42:43.347 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:42:43.819 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:42:44.291 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:42:44.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:44.372 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:44.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:44.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:44.377 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:42:44.384 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:44.384 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:44.384 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:44.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:44.385 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:44.385 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:44.386 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:42:44.386 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:42:44.386 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:42:44.386 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:44.386 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:49.395 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:42:49.395 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:42:49.395 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:49.395 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:49.395 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:49.396 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:49.402 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:42:49.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:42:49.402 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:49.402 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:42:49.402 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:42:49.405 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:42:49.405 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:42:49.405 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:42:49.405 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:49.406 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:42:49.406 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:42:49.406 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:42:49.406 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:42:49.406 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:49.409 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:42:49.409 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:42:49.409 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:42:49.409 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:49.409 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:42:49.409 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:42:49.410 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:42:49.410 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:42:49.410 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:49.412 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:42:49.412 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:42:49.412 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:42:49.412 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:42:49.413 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:42:49.413 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:42:49.413 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:42:49.413 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:42:49.413 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:49.416 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:42:49.417 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:42:49.417 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:42:49.417 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.417 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:42:49.418 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:42:49.419 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:42:49.422 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:42:49.894 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:42:49.941 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:42:49.944 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:42:49.945 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:42:49.945 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:49.963 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:49.963 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:49.964 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:49.975 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:49.975 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:49.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:49.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:49.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:49.979 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:49.979 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:49.979 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:49.979 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:49.983 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:49.983 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:49.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:49.984 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:50.349 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:50.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:50.354 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:50.354 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:50.360 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:42:50.370 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:50.370 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:50.371 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:50.377 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:50.377 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:50.377 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:50.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:50.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:50.379 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:50.379 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:50.379 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:50.379 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:50.400 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:42:50.400 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:42:50.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:50.400 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:50.420 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:50.420 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:50.420 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:50.421 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:50.824 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:42:50.954 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:50.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:50.960 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:50.960 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:50.960 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:42:50.972 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:50.972 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:50.972 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:50.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:50.979 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:50.979 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:50.979 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:50.980 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:50.980 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:50.980 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:50.980 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:50.980 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:51.005 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:51.005 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:51.005 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:51.006 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:51.289 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:42:51.422 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:51.422 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:51.422 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:51.423 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:51.755 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:42:51.910 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:51.911 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:51.915 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:51.916 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:51.928 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:51.929 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:51.929 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:51.934 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:42:51.934 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:42:51.934 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:42:51.934 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:42:51.935 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:51.935 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:42:51.935 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:42:51.936 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:42:51.936 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:42:51.990 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:42:51.990 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:42:51.990 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:51.991 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:42:52.221 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:42:52.423 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:52.423 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:52.423 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:52.424 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:52.690 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:42:53.154 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:42:53.424 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:53.424 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:53.424 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:53.425 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:53.619 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:42:54.083 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:42:54.425 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:42:54.426 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:42:54.426 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:42:54.426 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:42:54.547 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:42:55.012 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:42:55.480 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:42:55.946 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:42:56.417 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:42:56.890 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:42:57.360 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:42:57.825 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:42:58.289 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:42:58.753 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:42:59.218 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:42:59.683 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:43:00.147 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:43:00.612 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:43:01.078 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:43:01.550 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:43:02.022 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:43:02.494 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:43:02.967 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:43:03.439 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:43:03.912 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:43:04.383 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:43:04.851 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:43:05.324 [DEBUG] clck_gen.py:113 IND CLOCK 3468
2026-03-01 03:43:05.797 [DEBUG] clck_gen.py:113 IND CLOCK 3570
2026-03-01 03:43:06.265 [DEBUG] clck_gen.py:113 IND CLOCK 3672
2026-03-01 03:43:06.738 [DEBUG] clck_gen.py:113 IND CLOCK 3774
2026-03-01 03:43:07.210 [DEBUG] clck_gen.py:113 IND CLOCK 3876
2026-03-01 03:43:07.683 [DEBUG] clck_gen.py:113 IND CLOCK 3978
2026-03-01 03:43:08.155 [DEBUG] clck_gen.py:113 IND CLOCK 4080
2026-03-01 03:43:08.629 [DEBUG] clck_gen.py:113 IND CLOCK 4182
2026-03-01 03:43:09.101 [DEBUG] clck_gen.py:113 IND CLOCK 4284
2026-03-01 03:43:09.573 [DEBUG] clck_gen.py:113 IND CLOCK 4386
2026-03-01 03:43:10.046 [DEBUG] clck_gen.py:113 IND CLOCK 4488
2026-03-01 03:43:10.518 [DEBUG] clck_gen.py:113 IND CLOCK 4590
2026-03-01 03:43:10.990 [DEBUG] clck_gen.py:113 IND CLOCK 4692
2026-03-01 03:43:11.463 [DEBUG] clck_gen.py:113 IND CLOCK 4794
2026-03-01 03:43:11.932 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:11.932 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:11.933 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:43:11.935 [DEBUG] clck_gen.py:113 IND CLOCK 4896
2026-03-01 03:43:11.937 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:11.937 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:11.937 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:11.937 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:11.938 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:11.938 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:11.938 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:11.938 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:43:11.938 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:43:11.938 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:43:11.938 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:11.938 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4899 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:11.938 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4899 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:11.938 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4899 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:11.938 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=4899 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:16.947 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:43:16.948 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:43:16.948 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:16.948 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:16.948 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:16.948 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:16.964 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:16.965 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:43:16.965 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:16.965 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:43:16.965 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:43:16.971 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:43:16.971 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:43:16.971 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:43:16.971 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:16.971 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:16.971 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:43:16.972 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:43:16.972 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:43:16.972 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:16.976 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:43:16.976 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:43:16.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:43:16.976 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:16.976 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:16.976 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:43:16.976 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:43:16.976 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:43:16.977 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:16.979 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:43:16.979 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:43:16.979 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:43:16.979 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:16.980 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:16.980 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:43:16.980 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:43:16.980 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:43:16.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:43:16.984 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:43:16.985 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:43:16.985 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:43:16.985 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.985 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.987 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:16.990 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:43:17.462 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:43:17.503 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:43:17.504 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:43:17.505 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:43:17.506 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:17.513 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:17.513 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:17.513 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:17.523 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:17.523 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:17.524 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:17.524 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:17.527 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:17.527 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:17.527 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:17.527 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:17.527 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:17.554 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:17.554 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:17.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:17.555 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:17.929 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:43:17.989 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:17.989 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:17.990 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:17.992 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:18.400 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:43:18.874 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:43:18.990 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:18.991 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:18.991 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:18.993 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:19.347 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:43:19.818 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:43:19.991 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:19.992 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:19.992 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:19.994 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:20.290 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:43:20.379 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:20.381 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:20.385 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:20.385 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:20.402 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:20.402 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:20.403 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:20.409 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:20.409 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:20.409 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:20.410 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:20.411 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:20.411 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:20.411 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:20.411 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:20.411 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:20.424 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:43:20.424 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:43:20.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:20.425 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:20.760 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:43:20.993 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:20.993 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:20.993 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:20.995 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:21.233 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:43:21.706 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:43:21.994 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:21.994 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:21.995 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:21.996 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:22.179 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:43:22.652 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:43:23.125 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:43:23.588 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:43:24.059 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:43:24.533 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:43:24.948 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:24.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:24.952 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:24.952 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:24.952 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:43:24.967 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:24.967 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:24.967 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:24.974 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:24.974 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:24.974 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:24.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:24.975 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:24.975 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:24.975 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:24.975 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:24.975 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:25.002 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:43:25.003 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:25.003 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:25.003 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:25.004 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:25.471 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:43:25.942 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:43:26.413 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:43:26.884 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:43:27.357 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:43:27.828 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:43:28.300 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:43:28.772 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:43:29.245 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:43:29.717 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:43:30.189 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:43:30.663 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:43:31.135 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:43:31.608 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:43:31.763 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:31.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:31.768 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:31.769 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:31.788 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:31.788 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:31.789 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:31.795 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:31.795 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:31.795 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:31.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:31.797 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:31.797 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:31.797 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:31.797 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:31.797 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:31.841 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:43:31.841 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:43:31.841 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:31.842 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:32.078 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:43:32.551 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:43:32.632 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:32.632 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:32.632 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:43:32.635 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:32.635 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:32.635 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:32.635 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:32.636 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:32.636 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:32.636 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:32.636 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:32.636 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:43:32.636 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:43:32.636 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:43:37.648 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:43:37.648 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:43:37.649 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:37.649 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:37.649 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:37.649 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:37.659 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:37.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:43:37.660 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:37.660 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:43:37.660 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:43:37.662 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:43:37.663 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:43:37.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:43:37.663 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:37.663 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:37.663 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:43:37.663 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:43:37.663 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:43:37.663 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:37.665 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:43:37.665 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:43:37.665 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:43:37.665 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:37.666 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:37.666 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:43:37.666 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:43:37.666 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:43:37.666 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:37.667 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:43:37.667 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:43:37.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:43:37.668 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:37.668 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:37.668 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:43:37.668 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:43:37.668 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:43:37.668 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:37.670 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:43:37.670 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:43:37.670 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:43:37.670 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:43:37.670 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:43:37.671 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:43:37.671 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:43:37.671 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.671 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.672 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:37.676 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:43:38.141 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:43:38.195 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:43:38.196 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:43:38.198 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:43:38.198 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:38.218 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:38.218 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:38.219 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:38.242 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:38.242 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:38.243 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:38.245 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:38.250 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:38.251 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:38.251 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:38.251 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:38.251 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:38.281 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:38.281 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:38.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:38.281 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:38.609 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:43:38.673 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:38.673 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:38.674 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:38.674 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:39.080 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:43:39.550 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:43:39.674 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:39.675 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:39.675 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:39.675 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:40.013 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:40.015 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:40.019 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:40.019 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:40.021 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:43:40.034 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:40.034 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:40.034 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:40.041 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:40.041 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:40.041 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:40.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:40.043 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:40.043 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:40.043 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:40.043 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:40.043 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:40.064 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:43:40.064 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=5, maio=0, ma_len=4
2026-03-01 03:43:40.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:40.064 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:40.489 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:43:40.675 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:40.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:40.676 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:40.676 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:40.959 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:43:41.428 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:43:41.676 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:41.676 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:41.677 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:41.677 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:41.900 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:43:42.373 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:43:42.677 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:42.678 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:42.678 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:42.679 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:42.807 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:42.808 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:42.812 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:42.812 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:42.812 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:43:42.829 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:42.829 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:42.830 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:42.839 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:42.839 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:42.839 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:42.840 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:42.843 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:42.843 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:42.843 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:42.843 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:42.843 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:42.845 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:43:42.893 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:42.893 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:42.893 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:42.894 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:43.317 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:43:43.788 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:43:44.259 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:43:44.732 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:43:45.202 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:43:45.674 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:43:46.146 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:43:46.618 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:43:47.089 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:43:47.244 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:47.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:47.249 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:47.249 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:47.266 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:47.266 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:47.266 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:47.273 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:47.273 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:47.273 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:43:47.274 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:47.275 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:47.275 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:43:47.275 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:43:47.275 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:43:47.275 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:43:47.323 [DEBUG] ctrl_if_trx.py:162 (MS@172.18.36.22:6700) Recv SETFH cmd
2026-03-01 03:43:47.324 [INFO] transceiver.py:201 (MS@172.18.36.22:6700) Frequency hopping configured: hsn=6, maio=1, ma_len=2
2026-03-01 03:43:47.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:47.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:43:47.557 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:43:48.023 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:43:48.488 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:43:48.953 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:43:49.425 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:43:49.509 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:43:49.509 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:43:49.509 [INFO] transceiver.py:205 (MS@172.18.36.22:6700) Frequency hopping disabled
2026-03-01 03:43:49.514 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:49.515 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:49.515 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:49.515 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:49.516 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:49.516 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:49.516 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:49.516 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:43:49.516 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:43:49.516 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:43:49.516 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:49.516 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2571 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:49.516 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2571 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:49.516 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2571 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:49.516 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=2571 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:43:54.528 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:43:54.528 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:43:54.528 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:54.528 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:54.528 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:54.528 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:54.541 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:54.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:43:54.542 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:54.542 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:43:54.542 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:43:54.544 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:43:54.544 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:43:54.544 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:43:54.544 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:54.545 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:54.545 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:43:54.545 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:43:54.545 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:43:54.545 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:54.546 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:43:54.546 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:43:54.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:43:54.546 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:54.546 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:54.546 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:43:54.546 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:43:54.546 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:43:54.546 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:54.548 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:43:54.548 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:43:54.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:43:54.548 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:43:54.548 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:54.548 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:43:54.548 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:43:54.548 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:43:54.548 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.550 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:43:54.550 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:43:54.550 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:43:54.551 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.551 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:43:54.555 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:43:55.027 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:43:55.068 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:43:55.070 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.071 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:43:55.072 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:43:55.092 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.397 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.402 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.419 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.424 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.499 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:43:55.553 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:55.553 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:55.553 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:55.554 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:55.723 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.727 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.745 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.750 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:55.966 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:43:56.050 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:56.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:56.074 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:56.079 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:56.377 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:56.382 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:43:56.399 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:43:56.399 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:43:56.399 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:43:56.400 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:43:56.400 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:43:56.401 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:43:56.401 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:43:56.401 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:43:56.401 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:43:56.401 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:43:56.401 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:01.408 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:01.408 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:01.408 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:01.408 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:01.408 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:01.408 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:01.417 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:01.418 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:01.418 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:01.419 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:01.419 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:01.423 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:01.423 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:01.423 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:01.423 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:01.424 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:01.424 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:01.424 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:01.424 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:01.425 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:01.426 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:01.426 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:01.426 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:01.427 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:01.427 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:01.427 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:01.427 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:01.427 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:01.427 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:01.430 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:01.430 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:01.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:01.430 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:01.430 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:01.430 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:01.430 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:01.430 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:01.430 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.434 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:01.434 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:01.434 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:01.435 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.435 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:01.436 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:01.439 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:01.911 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:01.954 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:01.956 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:01.957 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:01.957 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:01.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:01.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.317 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.324 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.382 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:44:02.438 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:02.438 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:02.438 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:02.439 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:02.620 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.623 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.655 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.847 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:44:02.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.955 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.983 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:02.995 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:03.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:03.291 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:03.294 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:03.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:03.307 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:03.307 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:03.307 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:03.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:03.308 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:03.308 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:03.308 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:03.308 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:03.308 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:03.309 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:03.309 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:08.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:08.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:08.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:08.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:08.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:08.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:08.331 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:08.332 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:08.332 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:08.332 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:08.332 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:08.335 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:08.335 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:08.335 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:08.335 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:08.335 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:08.336 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:08.336 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:08.336 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:08.336 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:08.342 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:08.343 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:08.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:08.343 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:08.343 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:08.343 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:08.343 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:08.343 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:08.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:08.347 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:08.347 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:08.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:08.347 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:08.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:08.347 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:08.347 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:08.347 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:08.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:08.352 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:08.352 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:08.352 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:08.352 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:08.352 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.353 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:08.353 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:08.353 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:08.354 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.354 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:08.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:08.358 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:08.827 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:08.875 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:08.876 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:08.877 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:08.877 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:08.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:08.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.232 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.260 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.263 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.294 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:44:09.356 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:09.357 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:09.357 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:09.358 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:09.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.563 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.567 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.580 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.588 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.765 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:44:09.884 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.888 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.892 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.928 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:09.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:10.233 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:10.234 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:44:10.242 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:10.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:10.260 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:10.260 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:10.260 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:10.260 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:10.261 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:10.262 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:10.262 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:10.262 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:10.262 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:10.262 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:10.262 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:15.272 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:15.273 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:15.273 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:15.273 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:15.273 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:15.273 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:15.284 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:15.285 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:15.286 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:15.286 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:15.286 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:15.290 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:15.290 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:15.291 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:15.291 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:15.291 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:15.292 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:15.292 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:15.292 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:15.292 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:15.294 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:15.294 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:15.294 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:15.294 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:15.295 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:15.295 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:15.295 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:15.295 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:15.295 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:15.297 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:15.298 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:15.298 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:15.298 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:15.298 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:15.298 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:15.298 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:15.298 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:15.298 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:15.302 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:15.303 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:15.303 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:15.303 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:15.304 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:15.308 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:15.781 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:15.830 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:15.832 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:15.833 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:15.834 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:15.854 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:15.859 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.158 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.162 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.178 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.182 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.250 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:44:16.306 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:16.306 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:16.306 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:16.307 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:16.481 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.486 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.505 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.510 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.719 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:44:16.809 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.813 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.835 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:16.839 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:17.139 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:17.142 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:17.156 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:17.156 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:17.156 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:17.156 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:17.162 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:17.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:17.163 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:17.163 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:17.164 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:17.164 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:17.164 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:17.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=402 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.164 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=403 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.165 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.166 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.166 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:17.166 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=404 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:22.163 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:22.163 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:22.163 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:22.164 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:22.164 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:22.164 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:22.172 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:22.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:22.173 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:22.173 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:22.173 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:22.176 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:22.176 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:22.177 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:22.177 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:22.177 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:22.177 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:22.178 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:22.178 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:22.178 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:22.179 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:22.179 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:22.179 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:22.179 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:22.179 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:22.179 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:22.180 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:22.180 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:22.180 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:22.181 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:22.181 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:22.181 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:22.181 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:22.182 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:22.182 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:22.182 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:22.182 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:22.182 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:22.184 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:22.185 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:22.185 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:22.185 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:22.185 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.186 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:22.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.186 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.189 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:22.667 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:22.697 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:22.697 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:22.698 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:22.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:22.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:22.705 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:22.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.006 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.134 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:44:23.188 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:23.188 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:23.189 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:23.189 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:23.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.323 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.606 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:44:23.639 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.644 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.961 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.965 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:23.973 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:23.973 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:23.973 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:23.973 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:23.973 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:23.974 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:23.974 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:23.974 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:23.974 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:23.974 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:23.974 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:23.974 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=388 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:23.974 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=388 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:23.974 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=388 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:23.974 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=388 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:23.974 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=388 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:23.974 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=388 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:28.985 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:28.985 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:28.986 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:28.986 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:28.986 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:28.986 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:28.998 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:28.999 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:28.999 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:28.999 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:28.999 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:29.002 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:29.002 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:29.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:29.002 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:29.002 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:29.002 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:29.002 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:29.002 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:29.002 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:29.004 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:29.004 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:29.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:29.004 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:29.004 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:29.004 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:29.004 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:29.004 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:29.005 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:29.006 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:29.006 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:29.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:29.006 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:29.006 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:29.006 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:29.006 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:29.006 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:29.006 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:29.009 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:29.009 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:29.009 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:29.009 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:29.010 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:29.010 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:29.010 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.010 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.015 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:29.478 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:29.535 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:29.538 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:29.539 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.540 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:29.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:29.564 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.568 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.572 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.868 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.872 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.875 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.880 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.893 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.898 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.903 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.907 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:29.946 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:44:30.013 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:30.013 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:30.013 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:30.013 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:30.197 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.201 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.206 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.210 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.224 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.229 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.231 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.235 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.416 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:44:30.528 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.532 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.535 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.538 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.557 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.562 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.565 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.569 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.861 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.865 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.869 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.873 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:30.887 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:44:30.887 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:30.887 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:30.888 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:30.888 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:30.894 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:30.895 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:30.895 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:30.895 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:30.895 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:30.895 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:30.895 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:30.896 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=411 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:30.896 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=411 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:30.896 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=411 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:30.896 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=411 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:30.896 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=411 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:30.896 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=411 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:44:35.898 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:35.898 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:35.898 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:35.899 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:35.899 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:35.899 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:35.909 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:35.910 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:35.910 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:35.911 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:35.911 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:35.913 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:35.913 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:35.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:35.913 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:35.913 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:35.913 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:35.913 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:35.913 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:35.914 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:35.916 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:35.917 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:35.917 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:35.917 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:35.917 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:35.917 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:35.917 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:35.917 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:35.917 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:35.920 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:35.920 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:35.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:35.920 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:35.920 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:35.920 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:35.920 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:35.920 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:35.921 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:35.924 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:35.924 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:35.924 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:35.924 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:35.924 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.925 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:35.925 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:35.925 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:35.926 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.926 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:35.927 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:35.930 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:36.403 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:36.446 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:36.447 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:36.447 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:36.447 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:36.462 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.467 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.475 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.767 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.770 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.781 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.796 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.802 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.805 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:36.871 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:44:36.929 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:36.929 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:36.930 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:36.930 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:37.099 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.107 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.121 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.126 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.129 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.340 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:44:37.426 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.431 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.433 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.450 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.454 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.459 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.754 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.758 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.763 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:37.780 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:37.780 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:37.780 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:37.780 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:37.781 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:37.782 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:37.782 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:37.782 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:37.782 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:37.782 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:37.782 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:42.788 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:42.788 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:42.788 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:42.788 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:42.788 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:42.788 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:42.801 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:42.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:42.802 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:42.802 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:42.802 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:42.804 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:42.804 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:42.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:42.805 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:42.805 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:42.805 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:42.805 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:42.805 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:42.806 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:42.806 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:42.807 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:42.807 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:42.807 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:42.807 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:42.807 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:42.807 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:42.807 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:42.807 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:42.808 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:42.809 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:42.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:42.809 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:42.809 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:42.809 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:42.809 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:42.809 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:42.809 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:42.811 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:42.811 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:42.811 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:42.811 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.812 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:42.816 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:43.288 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:43.326 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:43.327 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:43.328 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:43.328 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.346 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.348 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.352 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.355 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.356 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.366 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.367 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.368 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.370 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.371 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.378 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.379 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.380 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.384 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.385 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.386 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.394 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.395 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.398 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.399 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.400 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:43.403 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:43.403 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:43.403 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:43.403 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:43.404 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:43.404 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:43.404 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:43.404 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:43.404 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:43.404 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:43.404 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:48.416 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:48.416 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:48.416 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:48.416 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:48.416 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:48.416 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:48.424 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:48.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:48.425 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:48.425 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:48.425 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:48.429 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:48.429 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:48.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:48.430 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:48.430 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:48.430 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:48.430 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:48.430 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:48.431 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:48.434 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:48.434 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:48.434 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:48.434 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:48.434 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:48.434 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:48.435 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:48.435 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:48.435 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:48.438 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:48.438 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:48.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:48.438 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:48.438 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:48.438 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:48.438 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:48.438 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:48.438 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.443 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:48.444 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:48.444 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:48.444 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.444 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:48.445 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:48.448 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:48.920 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:48.961 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:48.962 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:48.962 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:48.962 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.974 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.978 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.979 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.981 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.982 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.986 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.988 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.991 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.992 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:48.999 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.001 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.002 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.003 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.004 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.007 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.008 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.009 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.011 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.012 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.013 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.020 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.021 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.025 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.026 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.028 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.029 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.030 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.032 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.033 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.034 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.042 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.043 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.044 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.046 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.049 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.051 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.053 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.054 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.056 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.057 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.058 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:49.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:49.061 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:49.061 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:49.061 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:49.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:49.063 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:49.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:49.063 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:49.063 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:49.063 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:49.063 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:54.073 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:54.073 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:54.073 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:54.073 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:54.073 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:54.074 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:54.082 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:54.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:54.083 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:54.083 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:54.083 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:54.087 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:54.087 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:54.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:54.088 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:54.088 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:54.088 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:54.088 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:54.088 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:54.089 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:54.092 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:54.092 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:54.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:54.092 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:54.092 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:54.092 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:54.092 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:54.092 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:54.092 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:54.097 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:54.097 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:54.098 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:54.098 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:54.098 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:54.098 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:54.098 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:54.098 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:54.098 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:54.103 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:54.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:54.103 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:54.103 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:54.103 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:54.103 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:54.104 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:54.104 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:54.104 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.104 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.105 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.106 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:54.109 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:44:54.581 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:44:54.625 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:44:54.627 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:44:54.628 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:44:54.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.649 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.659 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.661 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.664 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.665 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.666 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.673 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.674 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.675 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.678 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.679 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.681 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.682 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.689 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.690 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.691 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.697 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.698 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.706 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.707 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.708 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.709 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.710 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.711 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.713 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.714 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.715 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:44:54.718 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:54.718 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:54.718 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:54.718 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:54.719 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:54.719 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:54.719 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:54.719 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:54.719 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:54.719 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:54.720 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:44:59.730 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:44:59.730 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:44:59.730 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:59.730 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:59.730 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:59.730 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:59.740 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:44:59.740 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:59.740 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:59.741 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:44:59.741 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:44:59.742 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:44:59.743 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:44:59.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:59.743 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:59.743 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:44:59.743 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:44:59.743 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:44:59.744 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:44:59.744 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:44:59.744 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:44:59.744 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:44:59.744 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:59.744 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:59.744 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:44:59.744 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:44:59.745 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:44:59.745 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:44:59.745 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:44:59.746 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:44:59.746 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:44:59.746 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:59.746 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:44:59.746 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:44:59.746 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:44:59.746 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:44:59.746 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:44:59.746 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.748 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:44:59.749 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:44:59.749 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:44:59.749 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:44:59.749 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:44:59.753 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:00.226 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:00.268 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:00.269 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:00.269 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:00.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.287 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.292 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.295 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.308 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.309 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.310 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.312 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.313 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.314 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.322 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.326 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.327 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.335 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.336 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.339 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.340 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:00.344 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:00.344 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:00.344 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:00.344 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:00.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:00.347 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:00.347 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:00.347 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:00.347 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:00.347 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:00.347 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:00.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=130 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:00.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=130 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:00.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=130 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:00.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=130 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:00.347 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=130 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:00.348 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=130 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:05.354 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:05.359 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:05.359 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:05.359 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:05.359 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:05.360 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:05.363 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:05.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:05.364 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:05.364 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:05.364 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:45:05.367 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:45:05.367 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:45:05.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:05.367 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:05.367 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:05.367 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:45:05.367 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:05.367 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:45:05.367 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:05.369 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:45:05.369 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:45:05.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:05.369 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:05.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:05.369 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:45:05.369 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:05.369 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:45:05.369 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:05.371 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:45:05.371 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:45:05.371 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:05.371 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:05.371 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:05.371 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:45:05.371 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:05.371 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:45:05.371 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.373 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:45:05.373 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:45:05.373 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:45:05.373 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.374 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.378 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:05.847 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:05.900 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:05.902 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:05.903 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:05.904 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:05.926 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.931 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.937 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.938 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.939 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.947 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.948 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.949 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.950 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.951 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.952 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.958 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.963 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.964 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.971 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.972 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.973 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.975 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.976 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.977 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:05.980 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:05.980 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:05.980 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:05.980 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:05.982 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:05.982 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:05.982 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:05.982 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:05.982 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:05.982 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:05.982 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:05.982 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:05.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:05.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:05.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:05.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:05.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:05.983 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=133 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:10.993 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:10.994 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:10.994 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:10.994 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:10.994 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:10.994 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:11.007 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:11.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:11.008 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:11.008 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:11.008 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:45:11.010 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:45:11.010 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:45:11.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:11.010 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:11.010 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:11.010 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:45:11.010 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:11.010 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:45:11.010 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:11.012 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:45:11.012 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:45:11.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:11.012 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:11.012 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:11.012 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:45:11.012 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:11.012 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:45:11.012 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:11.013 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:45:11.013 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:45:11.013 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:11.013 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:11.013 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:11.013 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:45:11.014 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:11.014 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:45:11.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:45:11.016 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:45:11.016 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:45:11.016 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.016 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:11.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.017 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:11.021 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:11.493 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:11.532 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:11.533 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.533 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:11.534 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:11.576 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:11.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.577 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.581 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.582 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.583 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.584 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.585 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.586 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.598 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.599 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.600 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.605 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.607 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.608 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.610 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.612 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.613 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.616 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.617 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.618 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.625 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.626 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.627 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.629 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.630 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.631 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.632 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.633 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.634 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.636 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.637 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.638 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.645 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.646 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.647 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.648 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.650 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.651 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.653 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.654 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.656 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.657 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.658 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:11.661 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:11.661 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:11.661 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:11.661 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:11.662 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:11.662 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:11.662 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:11.662 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:11.662 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:11.662 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:11.662 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:16.671 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:16.671 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:16.672 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:16.672 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:16.672 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:16.672 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:16.679 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:16.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:16.680 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:16.680 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:16.680 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:45:16.683 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:45:16.683 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:45:16.683 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:16.683 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:16.683 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:16.683 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:45:16.684 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:16.684 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:45:16.684 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:16.686 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:45:16.686 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:45:16.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:16.687 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:16.687 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:16.687 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:45:16.687 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:16.687 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:45:16.687 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:16.689 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:45:16.689 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:45:16.689 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:16.689 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:16.689 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:16.690 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:45:16.690 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:16.690 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:45:16.690 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:16.692 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.693 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:45:16.693 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:45:16.693 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:45:16.694 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.694 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:16.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.695 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:16.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.695 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:16.698 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:17.161 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:17.217 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:17.217 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:17.218 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:17.218 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.237 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:17.238 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.241 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.243 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.246 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.250 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.251 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.254 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.256 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.264 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.265 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.268 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.269 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.271 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.272 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.273 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.280 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.282 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.284 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.285 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.286 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.288 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.289 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.290 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.297 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.298 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.299 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.301 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.302 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.303 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.305 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.306 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.307 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:17.309 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:17.309 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:17.310 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:17.310 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:17.310 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:17.310 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:17.310 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:17.310 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:17.311 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:17.311 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:17.311 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:22.319 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:22.320 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:22.320 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:22.320 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:22.320 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:22.320 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:22.327 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:22.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:22.327 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:22.327 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:22.327 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:45:22.330 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:45:22.330 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:45:22.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:22.330 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:22.330 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:22.330 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:45:22.330 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:22.330 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:45:22.331 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:22.333 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:45:22.334 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:45:22.334 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:22.334 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:22.334 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:22.334 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:45:22.334 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:22.334 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:45:22.334 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:22.337 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:45:22.337 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:45:22.337 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:22.337 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:22.337 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:22.338 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:45:22.338 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:22.338 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:45:22.338 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.342 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:45:22.342 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:45:22.342 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:45:22.343 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.343 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:22.344 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:22.347 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:22.820 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:22.860 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:22.861 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:22.861 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:22.862 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:22.862 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:22.862 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:22.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:22.862 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:22.862 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:22.862 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:22.862 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:22.862 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:23.292 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:45:23.345 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:23.346 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:23.346 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:23.347 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:23.763 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:45:24.236 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:45:24.347 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:24.347 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:24.347 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:24.348 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:24.709 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:45:25.181 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:45:25.349 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:25.349 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:25.349 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:25.349 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:25.654 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:45:26.126 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:45:26.330 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:26.330 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:26.332 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:26.332 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:26.332 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:26.332 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:26.333 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:26.333 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:26.333 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:26.333 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:26.333 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:26.333 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:26.333 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:31.340 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:31.340 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:31.340 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:31.340 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:31.340 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:31.340 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:31.347 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:31.347 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:31.347 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:31.348 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:31.348 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:45:31.350 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:45:31.350 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:45:31.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:31.351 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:31.351 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:31.351 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:45:31.351 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:31.351 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:45:31.352 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:31.353 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:45:31.353 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:45:31.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:31.354 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:31.354 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:31.354 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:45:31.354 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:31.354 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:45:31.354 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:31.356 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:45:31.356 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:45:31.356 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:31.356 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:31.356 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:31.356 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:45:31.356 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:31.356 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:45:31.357 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:45:31.359 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:45:31.359 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:45:31.359 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.359 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.360 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:31.364 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:31.841 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:31.886 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:31.889 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:31.890 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:31.893 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:31.917 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:31.917 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:31.917 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:31.922 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:31.922 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:31.922 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:31.922 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:31.922 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:31.936 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 03:45:31.941 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:31.941 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:31.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:31.941 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:32.312 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:45:32.362 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:32.362 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:32.362 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:32.363 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:32.434 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:32.434 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:32.434 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:32.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:32.435 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:32.435 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:32.436 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:32.436 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:32.436 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:32.449 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:32.452 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:32.452 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:32.462 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:32.462 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:32.462 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:32.462 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:32.464 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:32.464 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:32.464 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:32.464 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:32.464 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:32.464 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:32.464 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:32.464 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=239 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:32.464 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=239 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:32.464 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=239 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:32.464 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=239 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:32.464 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=239 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:32.464 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=239 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:37.473 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:37.473 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:37.473 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:37.473 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:37.473 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:37.473 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:37.480 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:37.480 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:37.480 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:37.481 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:37.481 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:45:37.484 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:45:37.484 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:45:37.484 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:37.484 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:37.484 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:37.485 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:45:37.485 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:37.485 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:45:37.485 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:37.489 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:45:37.490 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:45:37.490 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:37.490 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:37.490 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:37.490 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:45:37.491 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:37.491 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:45:37.491 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:37.493 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:45:37.493 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:45:37.493 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:37.493 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:37.493 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:37.494 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:45:37.494 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:37.494 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:45:37.494 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:37.497 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:45:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:45:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:45:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:45:37.497 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:45:37.497 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:45:37.498 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:45:37.498 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.498 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:37.499 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:37.503 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:37.976 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:38.014 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:38.016 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:38.017 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:38.017 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:38.035 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:38.036 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:38.036 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:38.039 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:38.039 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:38.040 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:38.040 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:38.040 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:38.072 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 03:45:38.076 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:38.077 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:38.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:38.077 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:38.134 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:38.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:38.191 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:38.191 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:38.191 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:38.192 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:38.192 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:38.192 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:38.193 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:38.193 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:38.441 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:45:38.501 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:38.501 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:38.501 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:38.502 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:38.905 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:45:39.372 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:45:39.502 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:39.503 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:39.503 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:39.503 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:39.842 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:45:40.313 [DEBUG] clck_gen.py:113 IND CLOCK 612
2026-03-01 03:45:40.504 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:40.504 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:40.504 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:40.504 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:40.784 [DEBUG] clck_gen.py:113 IND CLOCK 714
2026-03-01 03:45:41.257 [DEBUG] clck_gen.py:113 IND CLOCK 816
2026-03-01 03:45:41.505 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:41.506 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:41.506 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:41.506 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:41.730 [DEBUG] clck_gen.py:113 IND CLOCK 918
2026-03-01 03:45:42.202 [DEBUG] clck_gen.py:113 IND CLOCK 1020
2026-03-01 03:45:42.506 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:42.507 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:42.507 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:42.507 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:42.673 [DEBUG] clck_gen.py:113 IND CLOCK 1122
2026-03-01 03:45:43.143 [DEBUG] clck_gen.py:113 IND CLOCK 1224
2026-03-01 03:45:43.611 [DEBUG] clck_gen.py:113 IND CLOCK 1326
2026-03-01 03:45:44.080 [DEBUG] clck_gen.py:113 IND CLOCK 1428
2026-03-01 03:45:44.551 [DEBUG] clck_gen.py:113 IND CLOCK 1530
2026-03-01 03:45:45.022 [DEBUG] clck_gen.py:113 IND CLOCK 1632
2026-03-01 03:45:45.492 [DEBUG] clck_gen.py:113 IND CLOCK 1734
2026-03-01 03:45:45.964 [DEBUG] clck_gen.py:113 IND CLOCK 1836
2026-03-01 03:45:46.434 [DEBUG] clck_gen.py:113 IND CLOCK 1938
2026-03-01 03:45:46.905 [DEBUG] clck_gen.py:113 IND CLOCK 2040
2026-03-01 03:45:47.376 [DEBUG] clck_gen.py:113 IND CLOCK 2142
2026-03-01 03:45:47.844 [DEBUG] clck_gen.py:113 IND CLOCK 2244
2026-03-01 03:45:48.310 [DEBUG] clck_gen.py:113 IND CLOCK 2346
2026-03-01 03:45:48.779 [DEBUG] clck_gen.py:113 IND CLOCK 2448
2026-03-01 03:45:49.252 [DEBUG] clck_gen.py:113 IND CLOCK 2550
2026-03-01 03:45:49.725 [DEBUG] clck_gen.py:113 IND CLOCK 2652
2026-03-01 03:45:50.197 [DEBUG] clck_gen.py:113 IND CLOCK 2754
2026-03-01 03:45:50.668 [DEBUG] clck_gen.py:113 IND CLOCK 2856
2026-03-01 03:45:51.138 [DEBUG] clck_gen.py:113 IND CLOCK 2958
2026-03-01 03:45:51.610 [DEBUG] clck_gen.py:113 IND CLOCK 3060
2026-03-01 03:45:52.083 [DEBUG] clck_gen.py:113 IND CLOCK 3162
2026-03-01 03:45:52.555 [DEBUG] clck_gen.py:113 IND CLOCK 3264
2026-03-01 03:45:53.028 [DEBUG] clck_gen.py:113 IND CLOCK 3366
2026-03-01 03:45:53.323 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:53.323 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:53.324 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:53.324 [WARNING] transceiver.py:257 (MS@172.18.36.22:6700) RX TRXD message (fn=3432 tn=7 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:53.324 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:53.341 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:53.341 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:53.341 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:53.341 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:53.341 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:53.351 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:53.352 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:53.352 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:53.358 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:53.358 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:53.358 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:53.359 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:53.361 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:53.362 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:53.362 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:53.362 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:53.362 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:53.362 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:53.362 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:53.362 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3440 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:53.362 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3440 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:53.362 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3440 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:53.362 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3440 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:53.362 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3440 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:53.362 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=3440 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:58.369 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:58.369 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:58.369 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:58.369 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:58.370 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:58.370 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:58.377 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:58.377 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:58.377 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:58.377 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:45:58.377 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:45:58.379 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:45:58.379 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:45:58.379 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:58.379 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:58.380 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:58.380 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:45:58.380 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:45:58.380 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:45:58.380 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:58.381 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:45:58.381 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:45:58.382 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:58.382 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:58.382 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:58.382 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:45:58.382 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:45:58.382 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:45:58.382 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:58.384 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:45:58.384 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:45:58.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:58.384 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:45:58.384 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:58.384 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:45:58.384 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:45:58.384 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:45:58.384 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:45:58.387 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:45:58.387 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:45:58.387 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.387 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.388 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:45:58.392 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:45:58.864 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:45:58.908 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:45:58.909 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:45:58.909 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:58.910 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:45:58.924 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:58.924 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:58.924 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:58.927 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:58.927 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:58.927 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:58.927 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:58.927 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:58.960 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 03:45:58.965 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:58.965 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:58.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:58.965 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:59.022 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:59.184 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 03:45:59.258 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:59.259 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:59.259 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:59.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:45:59.259 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:45:59.260 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:45:59.260 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:45:59.260 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:45:59.260 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:45:59.283 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:45:59.286 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:45:59.286 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:45:59.296 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:45:59.296 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:45:59.296 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:45:59.296 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:45:59.302 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:45:59.303 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:45:59.303 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:45:59.303 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:45:59.303 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:45:59.303 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:45:59.304 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:45:59.304 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=198 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.304 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=198 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.304 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=198 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.304 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=198 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.304 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=198 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.304 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=198 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:45:59.305 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=199 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:04.305 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:46:04.306 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:46:04.306 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:04.306 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:04.306 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:04.306 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:04.313 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:04.313 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:46:04.313 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:04.314 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:46:04.314 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:46:04.315 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:46:04.315 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:46:04.315 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:46:04.315 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:04.315 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:04.315 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:46:04.315 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:46:04.315 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:46:04.315 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:46:04.316 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:46:04.316 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:46:04.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:46:04.316 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:04.316 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:04.316 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:46:04.316 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:46:04.316 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:46:04.316 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:46:04.317 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:46:04.317 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:46:04.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:46:04.317 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:04.317 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:04.317 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:46:04.317 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:46:04.317 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:46:04.317 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.319 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:46:04.320 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:46:04.320 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:46:04.320 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.320 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:04.321 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:04.324 [DEBUG] clck_gen.py:113 IND CLOCK 0
2026-03-01 03:46:04.790 [DEBUG] clck_gen.py:113 IND CLOCK 102
2026-03-01 03:46:04.848 [DEBUG] fake_trx.py:278 (BTS@172.18.36.20:5700) Recv FAKE_TOA cmd
2026-03-01 03:46:04.850 [DEBUG] fake_trx.py:297 (BTS@172.18.36.20:5700) Recv FAKE_RSSI cmd
2026-03-01 03:46:04.850 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:46:04.850 [DEBUG] fake_trx.py:322 (BTS@172.18.36.20:5700) Recv FAKE_CI cmd
2026-03-01 03:46:04.873 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:46:04.874 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:46:04.874 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:46:04.878 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:46:04.879 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:46:04.879 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:46:04.879 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:46:04.879 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:46:04.933 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD HANDOVER
2026-03-01 03:46:04.938 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:46:04.938 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:46:04.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:46:04.939 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:46:05.262 [DEBUG] clck_gen.py:113 IND CLOCK 204
2026-03-01 03:46:05.322 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:46:05.322 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:46:05.323 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:46:05.323 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:46:05.733 [DEBUG] clck_gen.py:113 IND CLOCK 306
2026-03-01 03:46:06.204 [DEBUG] clck_gen.py:113 IND CLOCK 408
2026-03-01 03:46:06.323 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:46:06.323 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:46:06.324 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:46:06.324 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:46:06.677 [DEBUG] clck_gen.py:113 IND CLOCK 510
2026-03-01 03:46:06.944 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:46:06.945 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:46:06.945 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:46:06.945 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD ECHO
2026-03-01 03:46:06.961 [DEBUG] ctrl_if_trx.py:229 (MS@172.18.36.22:6700) Ignore CMD SETSLOT
2026-03-01 03:46:06.962 [DEBUG] ctrl_if_trx.py:124 (MS@172.18.36.22:6700) Recv RXTUNE cmd
2026-03-01 03:46:06.962 [DEBUG] ctrl_if_trx.py:131 (MS@172.18.36.22:6700) Recv TXTUNE cmd
2026-03-01 03:46:06.962 [DEBUG] ctrl_if_trx.py:97 (MS@172.18.36.22:6700) Recv POWERON CMD
2026-03-01 03:46:06.962 [INFO] ctrl_if_trx.py:109 (MS@172.18.36.22:6700) Starting transceiver...
2026-03-01 03:46:07.000 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD NOHANDOVER
2026-03-01 03:46:07.002 [DEBUG] ctrl_if_trx.py:115 (MS@172.18.36.22:6700) Recv POWEROFF cmd
2026-03-01 03:46:07.002 [INFO] ctrl_if_trx.py:117 (MS@172.18.36.22:6700) Stopping transceiver...
2026-03-01 03:46:07.014 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:46:07.014 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:46:07.014 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:46:07.014 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:46:07.017 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:07.017 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:07.017 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:07.017 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:07.017 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:46:07.017 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:46:07.017 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=0 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=1 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=2 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=3 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=4 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=5 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=6 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:07.017 [WARNING] transceiver.py:257 (BTS@172.18.36.20:5700) RX TRXD message (ver=1 fn=586 tn=7 bl=148 pwr=0), but transceiver is not running => dropping...
2026-03-01 03:46:12.019 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:46:12.019 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:46:12.019 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:12.020 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:12.020 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:12.020 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:12.029 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:12.029 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:46:12.030 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:12.030 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:46:12.030 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:46:12.033 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:46:12.033 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:46:12.034 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:46:12.034 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:12.034 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:12.034 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:46:12.035 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:46:12.035 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:46:12.035 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:46:12.038 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:46:12.038 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:46:12.039 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:46:12.039 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:12.039 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:12.039 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:46:12.039 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:46:12.039 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:46:12.039 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:46:12.043 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:46:12.043 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:46:12.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:46:12.043 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:12.043 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:12.043 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:46:12.043 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:46:12.043 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:46:12.043 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:46:12.046 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:46:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:46:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:46:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:46:12.046 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:46:12.046 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:46:12.047 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:46:12.047 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:46:12.047 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:12.047 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:12.048 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:46:12.048 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:46:12.048 [INFO] transceiver.py:246 Stopping clock generator
2026-03-01 03:46:17.052 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:46:17.052 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:46:17.052 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:17.052 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:17.052 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:17.052 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:17.054 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:17.055 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:46:17.055 [WARNING] ctrl_if_trx.py:196 (BTS@172.18.36.20:5700) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:17.055 [DEBUG] ctrl_if_trx.py:182 (BTS@172.18.36.20:5700) Recv SETFORMAT cmd
2026-03-01 03:46:17.055 [INFO] ctrl_if_trx.py:201 (BTS@172.18.36.20:5700) TRXD header version 1 -> 1
2026-03-01 03:46:17.056 [DEBUG] ctrl_if_trx.py:124 (TRX1@172.18.36.20:5700/1) Recv RXTUNE cmd
2026-03-01 03:46:17.056 [DEBUG] ctrl_if_trx.py:131 (TRX1@172.18.36.20:5700/1) Recv TXTUNE cmd
2026-03-01 03:46:17.056 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:46:17.056 [WARNING] ctrl_if_trx.py:196 (TRX1@172.18.36.20:5700/1) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:17.056 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:17.056 [DEBUG] ctrl_if_trx.py:215 (TRX1@172.18.36.20:5700/1) Recv NOMTXPOWER cmd
2026-03-01 03:46:17.057 [DEBUG] ctrl_if_trx.py:182 (TRX1@172.18.36.20:5700/1) Recv SETFORMAT cmd
2026-03-01 03:46:17.057 [INFO] ctrl_if_trx.py:201 (TRX1@172.18.36.20:5700/1) TRXD header version 1 -> 1
2026-03-01 03:46:17.057 [DEBUG] ctrl_if_trx.py:207 (TRX1@172.18.36.20:5700/1) Recv SETPOWER cmd
2026-03-01 03:46:17.057 [DEBUG] ctrl_if_trx.py:124 (TRX2@172.18.36.20:5700/2) Recv RXTUNE cmd
2026-03-01 03:46:17.057 [DEBUG] ctrl_if_trx.py:131 (TRX2@172.18.36.20:5700/2) Recv TXTUNE cmd
2026-03-01 03:46:17.057 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:46:17.057 [WARNING] ctrl_if_trx.py:196 (TRX2@172.18.36.20:5700/2) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:17.057 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:17.057 [DEBUG] ctrl_if_trx.py:215 (TRX2@172.18.36.20:5700/2) Recv NOMTXPOWER cmd
2026-03-01 03:46:17.058 [DEBUG] ctrl_if_trx.py:182 (TRX2@172.18.36.20:5700/2) Recv SETFORMAT cmd
2026-03-01 03:46:17.058 [INFO] ctrl_if_trx.py:201 (TRX2@172.18.36.20:5700/2) TRXD header version 1 -> 1
2026-03-01 03:46:17.058 [DEBUG] ctrl_if_trx.py:207 (TRX2@172.18.36.20:5700/2) Recv SETPOWER cmd
2026-03-01 03:46:17.059 [DEBUG] ctrl_if_trx.py:124 (TRX3@172.18.36.20:5700/3) Recv RXTUNE cmd
2026-03-01 03:46:17.059 [DEBUG] ctrl_if_trx.py:131 (TRX3@172.18.36.20:5700/3) Recv TXTUNE cmd
2026-03-01 03:46:17.059 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:46:17.059 [WARNING] ctrl_if_trx.py:196 (TRX3@172.18.36.20:5700/3) Requested TRXD header version 2 is not supported, suggesting 1...
2026-03-01 03:46:17.059 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:17.059 [DEBUG] ctrl_if_trx.py:215 (TRX3@172.18.36.20:5700/3) Recv NOMTXPOWER cmd
2026-03-01 03:46:17.059 [DEBUG] ctrl_if_trx.py:182 (TRX3@172.18.36.20:5700/3) Recv SETFORMAT cmd
2026-03-01 03:46:17.059 [INFO] ctrl_if_trx.py:201 (TRX3@172.18.36.20:5700/3) TRXD header version 1 -> 1
2026-03-01 03:46:17.059 [DEBUG] ctrl_if_trx.py:207 (TRX3@172.18.36.20:5700/3) Recv SETPOWER cmd
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:124 (BTS@172.18.36.20:5700) Recv RXTUNE cmd
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETTSC
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETTSC
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETTSC
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:131 (BTS@172.18.36.20:5700) Recv TXTUNE cmd
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETRXGAIN
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETRXGAIN
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETRXGAIN
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETTSC
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:215 (BTS@172.18.36.20:5700) Recv NOMTXPOWER cmd
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:207 (BTS@172.18.36.20:5700) Recv SETPOWER cmd
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.061 [DEBUG] ctrl_if_trx.py:97 (BTS@172.18.36.20:5700) Recv POWERON CMD
2026-03-01 03:46:17.061 [INFO] ctrl_if_trx.py:109 (BTS@172.18.36.20:5700) Starting transceiver...
2026-03-01 03:46:17.061 [INFO] transceiver.py:243 Starting clock generator
2026-03-01 03:46:17.062 [INFO] clck_gen.py:95 CLCKGen: Setting real time process scheduler to SCHED_RR, priority 31
2026-03-01 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETRXGAIN
2026-03-01 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.062 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX1@172.18.36.20:5700/1) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX2@172.18.36.20:5700/2) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:220 (TRX1@172.18.36.20:5700/1) Recv RFMUTE cmd
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:220 (TRX2@172.18.36.20:5700/2) Recv RFMUTE cmd
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (TRX3@172.18.36.20:5700/3) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:220 (TRX3@172.18.36.20:5700/3) Recv RFMUTE cmd
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:229 (BTS@172.18.36.20:5700) Ignore CMD SETSLOT
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:220 (BTS@172.18.36.20:5700) Recv RFMUTE cmd
2026-03-01 03:46:17.063 [DEBUG] ctrl_if_trx.py:115 (BTS@172.18.36.20:5700) Recv POWEROFF cmd
2026-03-01 03:46:17.063 [INFO] ctrl_if_trx.py:117 (BTS@172.18.36.20:5700) Stopping transceiver...
2026-03-01 03:46:17.063 [INFO] transceiver.py:246 Stopping clock generator